DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections – 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Independent Claim 1 recites an abstract idea directed to a group of mathematical concepts, under Step 2A Prong 1, according to the limitations, a circuit arrangement being configured:
to determine a byte error position signal indicating whether or not a byte of the binary sequence is erroneous, to determine a byte error correction value on the basis of which an erroneous byte position identified by the byte error position signal is able to be corrected, wherein the byte error correction value is determined by determining a first value, a second value, and a third value for each of at least three-byte positions according to a coefficient of a locator polynomial, to correct the at least one-byte error based on the byte error correction value.
The limitations recited in the Claims, which as drafted, are directed to a group of mathematical concepts. According to the 2019 Revised Patent Subject Matter Eligibility Guidance ("2019 PEG"), under their broadest reasonable interpretation, the limitations cover performance of mathematical concepts, such as, mathematical relationships, mathematical formulas or equations, and mathematical calculations.
If a claim limitation, under its broadest reasonable interpretation, covers performance of mathematical calculations, then it falls within the "Mathematical Concepts" of abstract ideas. For example, in Claim 1, the limitations "to determine at least one byte error position signal" and "to determine at least one byte error correction value" involves mathematical manipulations as a evident by the equations described in the specification (Equations 13-14 and 16-18), which is judicially excepted mathematical subject matter, and as such it falls within the "Mathematical Algorithms or Concepts" of abstract ideas. Accordingly, the claim is not eligible.
This judicial exception is not integrated into a practical application, under Step 2A Prong 2. In particular, the claims recite additional elements, such as, the additional generic computer element of the claimed parallel "circuit arrangement" does not add a meaningful limitation to the abstract idea. The claimed "circuit arrangement" (as recited in claim 1) amounts to simply implementing the abstract idea on a computer. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception.
The courts have recognized the storing and retrieving information in memory to be well-understood, routine, and conventional, computer functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. See MPEP 2106.05(d)(II). The Examiner finds the claimed "circuit arrangement' is recited at a high level of generality and its broadest reasonable interpretation is merely memory arranged in parallel. Therefore, the claims are not patent eligible.
Accordingly, these additional elements do not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea Accordingly, the claim is not eligible.
Independent claim 15 recites similar limitations as claim 1 and in addition, the claim does not recite any hardware tied the method and is rejected for similar reasons as well.
The dependent Claims 2-14 do not include additional elements that are sufficient amount more than the judicial exception. For example, dependent Claims 2-14 recite Mathematical equations or equations using word or mathematical symbols for solving byte error positions and therefore do not amount to significantly more than the judicial exception, because they are Mathematical expressions that can be calculated by a conventional computer used as a tool.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claims 1 and 15, line 7, which have the phrase “is able to be corrected” is not specific and vague. The rejection below will treat the phases “is able to be corrected” as --is corrected--.
Independent claim 15 is rejected for similar reasons and require corrections as well.
Regarding claims 9 and 11, line 2, which have the phrase “is able to be corrected” is not specific and vague. The rejection below will treat the phases “is able to be corrected” as --is corrected--.
Regarding claim 14, which have the phases “can correct”, are not specific and vague (for example the claim 14, the error code…can correct 3-byte errors, which the 3-byte errors can be or cannot be corrected with the error code).
Claim 1 recites the limitation “the byte error correction value is determined by determining a first value, a second value, and a third value for each of at least three-byte positions according to a coefficient of a locator polynomial, to correct the at least one-byte error based on the byte error correction value which does not particularly point out how the determined first, second, and third values for each of at least three-byte positions are being determine to achieve the cited result (the byte error correction value).
Respective dependent claims 2-14 are rejected at least based on dependency. Corrections are requested.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a) (1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention
Claims 1-15 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Ohira et al. “heren Ohira” (U.S. PN: 7,978,972).
Regarding claims 1 and 15, Ohira substantially teaches a circuit arrangement for correcting at least one byte error in a binary sequence comprising multiple bytes, the binary sequence being a codeword of an error code if there is no error, the circuit arrangement (see figures 11 and col. 8, lines 24-32), being configured to determine a byte error position signal indicating whether or not a byte of the binary sequence is erroneous to determine a byte error correction value on the basis of which an erroneous byte position identified by the byte error position signal is able to be corrected (see col. 9, lines 64-67 to col. 10, lines 1-7, col. 14, lines 4-54) wherein the byte error correction value is determined by determining a first value, a second value, and a third value for each of at least three-byte positions according to a coefficient of a locator polynomial to correct the at least one-byte error based on the byte error correction value (see col. 11, lines 22-67 to col. 12, lines 1- 38, col, 14, lines 4-54, col. 21, lines 20-32).
Regarding Claim 2, Ohira teaches which the first value comprises: a correction value A multiplied by a first constant, the first constant being determined by the erroneous byte position (see col. 7, lines 6-19, Col. 9, lines 45-52 and col. 17, lines 23-64).
Regarding Claim 3, Ohira teaches in which the third value comprises: a correction value C multiplied by a second constant, the second constant being determined by the erroneous byte position (see col. 7, lines 6-19, col. 9, lines 45-52 and col. 17, lines 23-64).
Regarding Claim 4, Ohira teaches in which the multiplications by the first constant and the second constant are multiplications in a Galois field GF(2m) where m ≥ 2 (see col. 10, lines 21-37 and col. 15, lines 13-35).
Regarding Claim 5, Ohira teaches in which the byte error correction value is determined in accordance with: where αL denotes the first constant, α2L denotes the second constant, A, C denotes the correction value A and the correction value C, respectively, B denotes the second value, and + denotes addition in the Galois field GF(2m) where m ≥ 2 (see col. 10, lines 21-37 and col. 15, lines 13-35).
Regarding Claim 6, Ohira teaches in which the correction value A, the correction value C, and the second value are the same for different byte positions (see col. 14, lines 16-21).
Regarding Claim 7, Ohira teaches in which the second constant is equal to the first constant squared (see col. 9, lines 45-52 and col. 17, lines 23-64).
Regarding Claim 8, Ohira teaches in which a correction is made for byte positions for which the byte error correction value is not equal to zero (see col. 9, lines 64-67 to col. 10, lines 1-7).
Regarding Claim 9, Ohira teaches in which a 3-byte error is able to be corrected using three-byte error position signals (see col. 14, lines 22-35).
Regarding Claim 10, Ohira teaches in which at least some byte error correction values are determined at overlapping times (see col. 14, lines 22-35).
Regarding Claim 11, Ohira teaches in which the byte error position signal is able to be determined using components of an error syndrome of the error code (see col. 9, lines 32-67 to 10, lines 1-14 and 12, lines 1-12).
Regarding Claim 12, Ohira teaches in which the byte error correction value is determined for a correct byte (see col. 14, lines 22-35).
Regarding Claim 13, Ohira teaches in which a 3-byte error is corrected (see col. 14, lines 22-35).
Regarding Claim 14, Ohira teaches in which the error code is a Reed-Solomon code in a Galois field GF(2m) where m ≥ 2 that can correct at least 3-byte errors (see col. 14, lines 22-35, col. 10, lines 21-37 and col. 15, lines 13-35).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Esaw T. Abraham whose telephone number is (571) 272-3812. The examiner can normally be reached on M-F 8am-4PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
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/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112