Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Response to Arguments
Applicant's arguments with respect to claims 1-14 have been considered but are moot in view of the new ground(s) of rejection. Claims 15-20 are either objected to or allowed as detailed below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1, 4, 5, and 7-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 8, and 10 of U.S. Patent No. 12,182,268 (hereafter, Dolezal) in view of U.S. PGPUB No. 2018/0217658, hereafter Bruhn.
Although the conflicting claims are not identical, they are not patentably distinct from each other because the subject matter claimed in the instant application is disclosed in the reference patent in view of fully disclosed in the reference patent in view of Bruhn as detailed below.
With respect to claim 1, Dolezal’s claim 1 teaches all of the limitations of instant claim 1 except the “steady-state” monitoring limitations.
However, Bruhn teaches detecting voltage spikes within an electronic device during a steady-state phase of operation of the device after device boot-up/initialization has taken place (Paragraph 37; “a processor (e.g. central processing unit (CPU)) with a load voltage circuit may detect load voltage spikes”; Paragraph 74; “Switching timing control may be performed after the initialization phase (in an operation phase, a steady-state phase, etc., for example) to adjust the switching timing as indicated by one or more detected voltage spikes.”)
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform the voltage transient detection process of Dolezal during stead-state operation, as taught be Bruhn, because voltage spikes can occur during normal operation of an electronic device and properly detecting and fixing the spike can avoid a fault state with the electronic device (Bruhn, Paragraph 37).
Instant claims 4 and 5 map to claims 8 and 10 of Dolezal.
Instant claims 7-9 are not disclosed in the claims of Dolezal, but are taught by Bruhn as follows:
Per Claim 7, Bruhn further discloses wherein monitoring comprises suspending a steady-state operation when an electrical transient is detected (Paragraphs 27, 37, and 103, Figure 8; If a load voltage spike is detected, the switching timing is suspended while a switching timing adjustment size is determined, see steps 802-808 of Figure 8.).
Per Claim 8, Bruhn further teaches passing control to a transient mitigation circuit when the electrical transient is detected (Paragraphs 57-63, switching timing controller 118).
Per Claim 9, Bruhn further teaches restoring the steady-state operation after the transient mitigation circuit releases control (Paragraph 104; “For instance, the electronic device 102 may add the switching timing adjustment size (e.g., time step) to or subtract the switching timing adjustment size from the switching timing (e.g., current set switching timing) for a next swing or cycle”.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 4, 5, and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivas et al. U.S. PGPUB No. 2019/0065751 in view of Bruhn, et al. U.S. PGPUB No. 2018/0217658.
Per Claim 1, Srinivas discloses a method, comprising: detecting a startup process on a device (Paragraph 30, Fig. 2; Numeral 200); delaying a portion of the startup process from handing over control to a startup firmware by processing delaying instructions (Paragraph 27; “The first instructions in the boot loader are a delay loop”.) and accounting for any electrical transient present on the device (Paragraph 30, Figure 2; Numeral 204; After device start-up, a process 204 waits until the power supply and clocks are stabilized.); and permitting the startup process to execute the delayed portion of the startup process, wherein the startup process passes control to the startup firmware after the processing of the delaying instructions is complete (Paragraph 34, Figure 2; De-assertion of the reset signal 230 releases the processor 116 from reset and causes the boot loader to begin execution.).
Srinivas does not specifically teach monitoring the device during steady-state operation for additional electrical transients.
However, Bruhn teaches detecting voltage spikes within an electronic device during a steady-state phase of operation of the device after device boot-up/initialization has taken place (Paragraph 37; “a processor (e.g. central processing unit (CPU)) with a load voltage circuit may detect load voltage spikes”; Paragraph 74; “Switching timing control may be performed after the initialization phase (in an operation phase, a steady-state phase, etc., for example) to adjust the switching timing as indicated by one or more detected voltage spikes.”)
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform the voltage transient detection process of Srinivas during stead-state operation, as taught be Bruhn, because voltage spikes can occur during normal operation of an electronic device and properly detecting and fixing the spike can avoid a fault state with the electronic device (Bruhn, Paragraph 37).
Per Claim 2, Srinivas discloses the method of claim 1, wherein detecting comprises identifying an event indicating that the device was restarted, powered on, or booted causing the startup process to initiate on the device (Paragraph 30, Figure 2; Power on event 200).
Per Claim 4, Srinivas discloses the method of claim 1, wherein delaying comprises utilizing circuitry of a microcontroller or a processor of the device to detect and to mitigate a particular electrical transient (Paragraph 17; The embedded device 100 can be a microcontroller; Paragraphs 17-20; Processor 116; Figure 1).
Per Claim 5, Srinivas discloses the method of claim 1, wherein permitting comprises executing the portion associated with the startup process causing control to pass to the startup firmware after the delaying instructions complete (Paragraph 34, Figure 2; De-assertion of the reset signal 230 releases the processor 116 from reset and causes the boot loader to begin execution.).
Per Claim 7, Bruhn further discloses wherein monitoring comprises suspending a steady-state operation when an electrical transient is detected (Paragraphs 27, 37, and 103, Figure 8; If a load voltage spike is detected, the switching timing is suspended while a switching timing adjustment size is determined, see steps 802-808 of Figure 8.).
Per Claim 8, Bruhn further teaches passing control to a transient mitigation circuit when the electrical transient is detected (Paragraphs 57-63, switching timing controller 118).
Per Claim 9, Bruhn further teaches restoring the steady-state operation after the transient mitigation circuit releases control (Paragraph 104; “For instance, the electronic device 102 may add the switching timing adjustment size (e.g., time step) to or subtract the switching timing adjustment size from the switching timing (e.g., current set switching timing) for a next swing or cycle”.).
* * * * * * * * *
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Srinivas et al. U.S. PGPUB No. 2019/0065751 in view of Bruhn, et al. U.S. PGPUB No. 2018/0217658 in further view of Nudelman et al. U.S. PGPUB No. 2022/0188147.
Per Claim 3, Srinivas discloses performing two separate delay loops (Paragraphs 27, 34, 37, 39, and 42), as opposed to nested loops.
However, Nudelman teaches that multiple separate loops of tasks/operations can be used interchangeably with nested loops (Paragraph 73)
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Srinivas’s multiple separate delay operation loops as part of a nested loop, as taught by Nudelman. This would have been obvious since it has been held that the simple substitution of one known element (nested loops) for another (separate/independent loops) to obtain predictable results is obvious to one of ordinary skill. See MPEP 2141, section III(B).
* * * * * * *
Claims 6, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivas et al. U.S. PGPUB No. 2019/0065751 in view of Bruhn, et al. U.S. PGPUB No. 2018/0217658 in further view of Lu et al. U.S. PGPUB No. 2017/0371388.
Per Claim 6, Srinivas discloses the bootloader (Paragraphs 26-28) but does not specifically mention the loading of BIOS for execution on the device.
However, Lu discloses both platform firmware (BIOS) and boot loader firmware (Paragraphs 16-18) performing checksum calculations at multiple steps of a firmware startup process (Paragraphs 16 and 18, Figure 2).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lu’s firmware checksum operations within the system startup routine of Srinivas/Bruhn because it ensures that the firmware being used to start the system has not been compromised.
Per Claims 10 and 11, Srinivas discloses performing a recursive delay loop that executes for a randomly selected number of times before the actual boot load instructions are executed (Paragraphs 27 and 34), but does not expressly teach performing a checksum calculation prior to moving to a next step of firmware startup.
However, Lu teaches performing checksum calculations at multiple steps of a firmware startup process (Paragraphs 16 and 18, Figure 2).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lu’s firmware checksum operations within the system startup routine of Srinivas because it ensures that the firmware being used to start the system has not been compromised.
* * * * * * * *
Claim 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivas et al. U.S. PGPUB No. 2019/0065751 in view of Nudelman et al. U.S. PGPUB No. 2022/0188147 in further view of Lu et al. U.S. PGPUB No. 2017/0371388.
Per Claim 12, Srinivas discloses a method, comprising: identifying initiation of a boot of a device (Paragraph 30, Fig. 2; Numeral 200); detecting an electrical transient during the boot (Paragraph 30, Figure 2; Numeral 204; After device start-up, a process 204 waits until the power supply and clocks are stabilized.); intentionally delaying executing of startup firmware for a delay time (Paragraph 27; “The first instructions in the boot loader are a delay loop”.); and permitting the startup process to execute the delayed portion of the startup process, wherein the startup process passes control to the startup firmware after the processing of the delaying instructions is complete (Paragraph 34, Figure 2; De-assertion of the reset signal 230 releases the processor 116 from reset and causes the boot loader to begin execution.).
Srinivas discloses performing two separate delay loops (Paragraphs 27, 34, 37, 39, and 42), as opposed to nested loops.
However, Nudelman teaches that multiple separate loops of tasks/operations can be used interchangeably with nested loops (Paragraph 73)
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to implement Srinivas’s multiple separate delay operation loops as part of a nested loop, as taught by Nudelman. This would have been obvious since it has been held that the simple substitution of one known element (nested loops) for another (separate/independent loops) to obtain predictable results is obvious to one of ordinary skill. See MPEP 2141, section III(B).
Srinivas discloses performing a recursive delay loop that executes for a randomly selected number of times before the actual boot load instructions are executed (Paragraphs 27 and 34), but does not expressly teach performing a checksum calculation prior to moving to a next step of firmware startup.
However, Lu teaches performing checksum calculations at multiple steps of a firmware startup process (Paragraphs 16 and 18, Figure 2).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate Lu’s firmware checksum operations within the system startup routine of Srinivas because it ensures that the firmware being used to start the system has not been compromised.
Per claim 13, Srinivas discloses the method of claim 12 wherein detecting comprises utilizing specialized circuitry to identify the electrical transient (Paragraph 17; The embedded device 100 can be a microcontroller; Paragraphs 17-20; Processor 116; Figure 1)
Per Claim 14, Srinivas discloses the method of claim 12, wherein processing further includes processing a no-operation instruction during each iteration of an inner loop for the nested loop set of instructions (Paragraph 27; “dummy instruction”, NOP). Please refer to the above rejection of claim 12 with respect to the nested loop teachings.
Allowable Subject Matter
Claims 19 and 20 are allowed.
Claims 15 and 16 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
- The following is a statement of reasons for the indication of allowable subject matter:
Per Claims 15, 16, and 19, no combination of Srinivas, Nudelman, Lu, Bruhn, and the prior art, when considered together, anticipate the combination of limitations presented by claims 15 or 16, when considered in combination with the limitations of claim 12, or the limitations of claim 19 in entirety. The limitations of these claims may have been rejected in other claim sets; however, it would not have been obvious to combine the teachings of each of the above prior art references to arrive at these specific combinations of limitations.
Claims 17 and 18 inherit the allowable subject matter of Claim 16.
- Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889. The examiner can normally be reached on M-F: 8-4:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner' s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175
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