DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5, 6, 8, 9, 14, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kataoka (JP-2004063989-A) in view of Otsuka (JP-2005051496-A) in view of Nix (EP-0361808-B1).
Regarding claim 1
Kataoka discloses
An integrated circuit ([0001]) comprising:
a plurality of first semiconductor intellectual property (IP) cores ([0002]);
a chip connection circuit ([0007]—[0010]);
a multiplexing circuit configured to select any one of the plurality of first semiconductor IP cores or the chip connection circuit as an input/output (I/O)
target based on an I/O target selection signal ([0010]—[0018], a selector is a form of a multiplexor);
Although strongly implied, Kataoka does not explicitly teach
“Chip connections with silicon vias or through-holes and a driver
And
a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit; and
a test control circuit configured to provide the I/O target selection signal to the multiplexing circuit”.
Otsuka, however, teaches
Chip connections with silicon vias or through-holes and a driver (¶ 1 under Drawing Description).
Kataoka in view of Otsuka do not teach
“a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit; and
a test control circuit configured to provide the I/O target selection signal to the multiplexing circuit.”
Nix, however, teaches
a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit; and
a test control circuit configured to provide the I/O target selection signal to the multiplexing circuit (¶ 7—18 under Description).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the “through-holes or vias and driver” as taught by Otsuka as well as the “control and multiplexing circuits” as taught by Nix in the circuit of Kataoka.
The justification for this modification would be to 1) have a driver to drive high-current applications, and use vias for area-efficient ways to connect components on different levels and 2) have a multiplexer to switch between IP cores and drive the testing control circuit.
Regarding claim 5
Kataoka in view of Otsaka in view of Nix teach the integrated circuit of claim 1,
Kataoka, applied to claim 5, further discloses
wherein: the plurality of first semiconductor IP cores comprise a test target semiconductor ([0020]—[0021]), and
the I/O target selection signal comprises a value for setting the test target semiconductor as the I/O target ( [0021]).
Regarding claim 6
Kataoka in view of Otsaka in view of Nix teach the integrated circuit of claim 1,
Kataoka, applied to claim 6, further teaches
further comprising an I/O circuit configured to electrically connect an external device with the multiplexing circuit ([0010]—[0018], a selector is a form of a multiplexor),
transmit a signal from the external device to the multiplexing circuit, and transmit a signal from the multiplexing circuit to the external device ([0010]—[0018], a selector is a form of a multiplexor).
Regarding claim 8
Kataoka in view of Otsaka in view of Nix teach the integrated circuit of claim 6,
Kataoka, applied to claim 8, further teaches
wherein the multiplexing circuit is configured to provide a signal from the I/O target to the I/O circuit, and provide a signal received from the I/O circuit to the I/O target ([0004]).
Regarding claim 9
Kataoka discloses
An integrated circuit comprising a first chip and a second chip, wherein the first chip ([0001]) comprises:
a plurality of first semiconductor intellectual property (IP) cores ([0002]);
a chip connection circuit ([0007]—[0010]);
a first multiplexing circuit configured to select any one of the plurality of first semiconductor IP cores or the chip connection circuit as a first input/output (I/O) target based on a first I/O target selection signal ([0010]—[0018], a selector is a form of a multiplexor);
wherein the second chip is arranged above the first chip (¶ 1 under [0002] & Prior Art) and comprises:
a plurality of second semiconductor IP cores ([0002]);
a second multiplexing circuit configured to select any one of the plurality of second semiconductor IP cores as a second I/O target, based on a second I/O target selection signal ([0010]—[0018], a selector is a form of a multiplexor); and
Kataoka does not teach
“Chip connections with silicon vias or through-holes and a driver
And
a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit; and
a first test control circuit configured to provide the first I/O target selection signal to the first multiplexing circuit, and
a test control circuit configured to provide the second I/O target selection signal to the second multiplexing circuit”.
Otsuka, however, teaches
Chip connections with silicon vias or through-holes and a driver (¶ 1 under Drawing Description).
Kataoka in view of Otsuka do not teach
“a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit; and
a first test control circuit configured to provide the first I/O target selection signal to the first multiplexing circuit, and
a test control circuit configured to provide the second I/O target selection signal to the second multiplexing circuit”.
Nix, however, teaches
a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit; and
a first test control circuit configured to provide the first I/O target selection signal to the first multiplexing circuit, and
a test control circuit configured to provide the second I/O target selection signal to the second multiplexing circuit (¶ 7—18 under Description).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the “through-holes or vias and driver” as taught by Otsuka as well as the “control and multiplexing circuits” as taught by Nix in the circuit of Kataoka.
The justification for this modification would be to 1) have a driver to drive high-current applications, and use vias for area-efficient ways to connect components on different levels and 2) have a multiplexer to switch between IP cores and drive the testing control circuit.
Regarding claim 14
Kataoka in view of Otsaka in view of Nix teach the integrated circuit of claim 9,
Kataoka, applied to claim 14, further teaches
wherein the first chip further comprises a first I/O circuit configured to electrically connect an external device with the first multiplexing circuit, transmit signals from the external device to the first multiplexing circuit, and transmit signals from the first multiplexing circuit to the external device ([0010]—[0018], a selector is a form of a multiplexor).
Regarding claim 18
Kataoka discloses
A test system (¶ 1 under [0002] & [Prior Art]) comprising:
an integrated circuit ([0001]); and
test equipment configured to test the integrated circuit ([0003]), wherein the integrated circuit comprises:
a plurality of first semiconductor intellectual property (IP) cores ([0002]);
a chip connection circuit ([0007]—[0010]),
a first multiplexing circuit configured to select any one of the plurality of first semiconductor IP cores or the chip connection circuit as a first input/output (I/O) target based on a first I/O target selection signal ([0010]—[0018], a selector is a form of a multiplexor);
Kataoka does not disclose
“Chip connections with silicon vias or through-holes and a driver
And
a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit;
a first test control circuit configured to provide the first I/O target selection signal to the first multiplexing circuit; and
a first chip including a first I/O circuit configured to electrically connect the test equipment and the first multiplexing circuit, transmit signals from the test equipment to the first multiplexing circuit, and transmit signals from the first multiplexing circuit to the test equipment”.
Otsaka, however, teaches
Chip connections with silicon vias or through-holes and a driver (¶ 1 under Drawing Description),
Kataoka in view of Otsaka do not teach
“a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit;
a first test control circuit configured to provide the first I/O target selection signal to the first multiplexing circuit; and
a first chip including a first I/O circuit configured to electrically connect the test equipment and the first multiplexing circuit, transmit signals from the test equipment to the first multiplexing circuit, and transmit signals from the first multiplexing circuit to the test equipment”.
Nix, however, teaches
a test enable circuit configured to provide a test enable signal to the chip connection circuit, based on a test mode of the integrated circuit;
a first test control circuit configured to provide the first I/O target selection signal to the first multiplexing circuit; and
a first chip including a first I/O circuit configured to electrically connect the test equipment and the first multiplexing circuit, transmit signals from the test
equipment to the first multiplexing circuit, and transmit signals from the first multiplexing circuit to the test equipment (¶ 7—18 under Description).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the “through-holes or vias
and driver” as taught by Otsuka as well as the “control and multiplexing circuits” as taught by Nix in the circuit of Kataoka.
The justification for this modification would be to 1) have a driver to drive high-current applications, and use vias for area-efficient ways to connect
components on different levels and 2) have a multiplexer to switch between IP cores and drive the testing control circuit.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kataoka (JP-2004063989-A) in view of Otsuka (JP-2005051496-A) in view of Nix (EP-0361808-B1) in view of Jose (EP-3671713-A1).
Regarding claim 2
Kataoka in view of Otsaka in view of Nix teach the integrated circuit of claim 1,
Otsaka, applied to claim 2, further teaches vias to connect the chip levels (¶ 1 under Drawing Description),
Kataoka in view of Otsaka in view of Nix do not teach
“wherein the receiver is configured to provide the multiplexing circuit with a signal received from the outside through the first through connection, and the driver is configured to output a signal output from the multiplexing circuit to the outside through the second through connection”.
Jose, however, teaches
wherein the receiver is configured to provide the multiplexing circuit with a signal received from the outside through the first through connection (¶ 3 under Summary), and the driver is configured to output a signal output from the multiplexing circuit to the outside through the second through connection (¶ 12 under Summary).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the “driver and multiplexing circuits connected” as taught by Jose in the circuit of Kataoka in view of Otsaka in view of Nix.
The justification for this modification would be to choose and drive the selected IP core.
Claim(s) 3, 4, 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kataoka (JP-2004063989-A) in view of Otsuka (JP-2005051496-A) in view of Nix (EP-0361808-B1) in view of Lin (EP-3361274-A1).
Regarding claim 3
Kataoka in view of Otsaka in view of Nix teach the integrated circuit of claim 1, wherein the test enable circuit further comprises:
Kataoka in view of Otsaka in view of Nix do not teach
“a test buffer controller configured to generate a buffer enable signal and the test enable signal; and
a test buffer configured to receive the test enable signal from the test buffer controller and provide the test enable signal to the receiver in response to the buffer enable signal,
wherein the test enable signal includes a first value”.
Lin, however, teaches
a test buffer controller configured to generate a buffer enable signal and the test enable signal (¶ 1 under Claims); and
a test buffer configured to receive the test enable signal from the test buffer controller and provide the test enable signal to the receiver in response to the buffer enable signal (¶ or line 19 under Claims),
wherein the test enable signal includes a first value (¶ or line 19 under Claims).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the “test enable signals and butter” as taught by Lin in the circuit of Kataoka in view of Otsaka in view of Nix.
The justification for this modification would be to coordinate the test enable signal with the buffer enable signal and store the relevant data.
Regarding claim 4
Kataoka in view of Otsaka in view of Nix in view of Lin teach the integrated circuit of claim 3,
Lin, applied to claim 4, further teaches
wherein the test buffer controller is configured to generate the buffer enable signal and the test enable signal when the integrated circuit operates in a first test mode (¶ 1 under BRIEF SUMMARY OF THE INVENTION), and
wherein the test buffer is configured to operate in a high-impedance state when the integrated circuit operates in a second test mode or in a normal mode (¶ 2 DETAILED DESCRIPTION OF THE INVENTION).
Regarding claim 19
Kataoka in view of Otsaka in view of Nix teach the test system of claim 18,
wherein the test enable circuit further comprises:
Kataoka in view of Otsaka in view of Nix do not teach
“a test buffer controller configured to generate a buffer enable signal and the test enable signal; and
a test buffer configured to receive the test enable signal from the test buffer controller and provide the test enable signal to the receiver in response to the buffer enable signal,
wherein the test enable signal includes a first value”.
Lin, however, discloses
a test buffer controller configured to generate a buffer enable signal and the test enable signal (¶ 1 under Claims); and
a test buffer configured to receive the test enable signal from the test buffer controller and provide the test enable signal to the receiver in response to the buffer enable signal (¶ or line 19 under Claims),
wherein the test enable signal includes a first value (¶ 22 under Claims).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the “test buffer coordinated with an enable signal” as taught by Lin in the system of Kataoka in view of Otsaka in view of Nix.
The justification for this modification would be to coordinate the test enable signal with the buffer enable signal and store the relevant data.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kataoka (JP-2004063989-A) in view of Otsuka (JP-2005051496-A) in view of Nix (EP-0361808-B1) in view of Kaplinsky (US-5164612-A).
Regarding claim 7
Kataoka in view of Otsaka in view of Nix teach the integrated circuit of claim 6,
Kataoka in view of Otsaka in view of Nix do not teach
“wherein a voltage of the signal provided by the multiplexing circuit to the I/O circuit is less than a voltage of the signal provided by the I/O circuit to the external device”.
Kaplinsky, however, teaches
wherein a voltage of the signal provided by the multiplexing circuit to the I/O circuit is less than a voltage of the signal provided by the I/O circuit to the external device (¶ or line 6 under Claim 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the “varying voltages” as taught by Kaplinsky in the circuit of Kataoka in view of Otsaka in view of Nix.
The justification for this modification would be to have a higher voltage/power for the driving circuit.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kataoka (JP-2004063989-A) in view of Otsuka (JP-2005051496-A) in view of Nix (EP-0361808-B1) in view of Young (CN-114402297-A).
Regarding claim 15
Kataoka in view of Otsaka in view of Nix teach the integrated circuit of claim 9,
Kataoka in view of Otsaka in view of Nix do not teach
“wherein the second chip further comprises a second I/O circuit configured to electrically connect the first chip with the second multiplexing circuit, transmit signals from the first chip to the second multiplexing circuit, and transmit signals from the second multiplexing circuit to the first chip”.
Young, however, teaches
wherein the second chip further comprises a second I/O circuit configured to electrically connect the first chip with the second multiplexing circuit (¶ 53 under Specific Implementation Examples), transmit signals from the first chip to the second multiplexing circuit, and transmit signals from the second multiplexing circuit to the first chip (Claim 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the “first and second chips
stacked with multiplexers” as taught by Young in the circuit of Kataoka in view of Otsaka in view of Nix.
The justification for this modification would be to create an IC that has higher component density without increasing size.
Allowable Subject Matter
Claims 10 – 13, 16, 17, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 10
Nothing in the prior art of record teaches or discloses
“a driver electrically connected to the second through silicon via and configured to provide a signal output from the first multiplexing circuit to the second chip through the second through silicon via”.
In conjunction with the rest of the claim language.
Regarding claim 11
The claim is allowable due to its dependency on objected-to claim 10.
Regarding claim 12
Nothing in the prior art of record teaches or discloses
“a test buffer controller configured to generate a buffer enable signal and the test enable signal based on a test mode of the integrated circuit; and
a test buffer configured to receive the test enable signal from the test buffer controller and provide the test enable signal to the receiver in response to the buffer enable signal”.
In conjunction with the rest of the claim language.
Regarding claim 13
The claim is allowable due to its dependency on objected-to claim 12.
Regarding claim 16
Nothing in the prior art of record teaches or discloses
“wherein the first I/O target selection signal includes a value for setting a test target semiconductor IP core selected from among the plurality of first semiconductor IP cores as the first I/O target when the integrated circuit operates in a test mode for testing the first chip”.
In conjunction with the rest of the claim language.
Regarding claim 17
Nothing in the prior art of record teaches or discloses
“wherein the first I/O target selection signal includes a value for setting the chip connection circuit as the first I/O target, and the second I/O target selection signal includes a value for setting a test target semiconductor IP core selected from among the plurality of second semiconductor IP cores as the second I/O target, when the integrated circuit operates in a test mode for testing the second chip”.
In conjunction with the rest of the claim language.
Regarding claim 20
Nothing in the prior art of record teaches or discloses
“a second test control circuit configured to provide the second I/O target selection signal to the second multiplexing circuit; and
a second I/O circuit configured to electrically connect the first chip with the second multiplexing circuit, transmit signals from the first chip to the second multiplexing circuit, and transmit signals from the second multiplexing circuit to the first chip,”
In conjunction with the rest of the claim language.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FREDERICK WENDEROTH whose telephone number is (571)270-1945. The examiner can normally be reached M-F 7 a.m. - 4 p.m.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Walter Lindsay can be reached at 571-272-1674. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing
in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WALTER L LINDSAY JR/Supervisory Patent Examiner, Art Unit 2852
/Frederick Wenderoth/
Examiner, Art Unit 2852
Prosecution Insights