DETAILED ACTION
This Office Action is in response to application 18/958261 filed on 11/25/2024. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/25/2024 has been acknowledged and is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
1. Claims 1-6, 8, 9, 11-17, 19, 20, are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2018/0139267) in view of Wang et al. (US 2025/0016116).
Regarding claim 1, Choi disclosed:
A system for network management (Paragraph 42, network architecture for a data center to communicate data in a network), the system comprising:
a switch (Paragraph 55, each node has routing/switching capabilities) to interconnect nodes (Figure 1B, 174, to from other nodes) via:
a first layer (Paragraph 16, first dimension) connecting:
a first cluster of the nodes (Figure 4, 410) into full-mesh-connected nodes (Paragraph 65, quad full mesh)(Paragraph 16, showing the quad full mesh network in a one-dimensional configuration (i.e., first layer). Paragraph 55, each node comprises routing and switching capabilities. Router 170 has communication links to/from other nodes. Paragraph 65, Figure 2A, the depicted quad full mesh network includes four nodes with six links);
a second cluster of the nodes (Figure 4A, 420) into full-mesh-connected nodes (Paragraph 65, Figure 2A, quad full mesh network with 4 nodes);
a third cluster of the nodes (Figure 4A, 440) into full-mesh-connected nodes (Paragraph 65, Figure 2A, the depicted quad full mesh network includes four nodes with six links); and
a fourth cluster of the nodes (Figure 4A, 430) into full-mesh-connected nodes (Paragraph 6, Figure 2A, the depicted quad full mesh network includes four nodes with six links); and
a second layer (Paragraph 20, second dimension) comprising inter-cluster connections to connect a first node (Figure 4A, N0) of the first cluster (Figure 4A, 410) to:
a first node (Figure 4A, N4) of the second cluster (Figure 4A, 420) by one hop (Paragraph 65, communication link) (Figure 4A, L0-4, Paragraph 65, each node is directly connected by one communication link to each other node); and
a first node (Figure 4A, N12) of the third cluster (Figure 4A, 440) by one hop (Figure 4A, N0 p3 to N12 p5, Paragraph 65, each node is directly connected by one communication link to each other node).
While Choi disclosed switches interconnecting the nodes (see above) and in practice, switches can reside on boards, Choi did not explicitly disclose a switch baseboard comprising switches to interconnect nodes.
However, in an analogous art, Wang disclosed a switch baseboard comprising switches to interconnect nodes (Figure 2, first switching chip 203 on first switching fabric board 10. Figure 7A showing a second switching chip 702 on the same first switching fabric board 10. Paragraph 63, the first switching fabric board is connected to the backplane through insertion or welding (i.e., switch baseboard)).
One of ordinary skill in the art would have been motivated to combine the teachings of Choi with Wang because the references involve full mesh structure, and as such, are within the same environment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the switch baseboard of Wang with the teachings of Choi in order to have forwarding times be small and short and have high efficiency (Wang, Paragraph 18).
Regarding claim 12, Choi disclosed:
A method for network management, the method comprising: receiving, by a switch (Paragraph 55, each node has routing/switching capabilities), data (Paragraph 55, packets) from a first node (Figure 4A, N0) of a set of nodes connected to the switch (Paragraph 55, each node has routing and switching capabilities, therefore, any of the nodes can be the switch. The router of each node is able to send and receive packets from other nodes); and
sending, by the switch, the data to a second node (Figure 4A, N13) of the set of nodes, the first node and the second node being separated by two hops (Paragraph 65, communication link) (Figure 4A, showing N0 in order to send a packet to N13, must first send the packet to N4 (i.e., first hop), then onto N13 (i.e., second hop). This is just one possible path, N0 to N8 to N13 also is two hops),
wherein the switch, interconnects the nodes of the set of nodes via (Figure 1B, 174, to from other nodes):
a first layer (Paragraph 16, first dimension) connecting: a first cluster of nodes (Figure 4A, 410) of the set of nodes into full-mesh-connected nodes (Paragraph 65, quad full mesh) comprising the first node as the first node of the first cluster (Figure 4A, N0 being part of full mesh 410) (Paragraph 16, showing the quad full mesh network in a one-dimensional configuration (i.e., first layer). Paragraph 55, each node comprises routing and switching capabilities. Router 170 (i.e., first layer) has communication links to/from other nodes. Paragraph 65, Figure 2A, the depicted quad full mesh network includes four nodes with six links);
a second cluster of nodes (Figure 4A, 420) of the set of nodes into full-mesh-connected nodes (Paragraph 65, quad full mesh);
a third cluster of nodes (Figure 4A, 440) of the set of nodes into full-mesh-connected nodes (Paragraph 65, quad full mesh) comprising the second node as a second node of the third cluster (Figure 4A, N13 is part of network 440); and
a fourth cluster of nodes (Figure 4A, 430) of the set of nodes into full-mesh-connected nodes(Paragraph 65, quad full mesh); and
a second layer (Paragraph 20, second dimension) comprising inter-cluster connections to connect the first node (Figure 4A, N0) of the first cluster (Figure 4A, 410) to a first node (Figure 4A, N12) of the third cluster (Figure 4A, 440) by one hop, the first node of the third cluster being connected to the second node (Figure 4A, N13) of the third cluster by one hop (Paragraph 65, communication link) (Figure 3, showing N12 connected to N13 through one communication link).
While Choi disclosed switches interconnecting the nodes (see above) and in practice, switches can reside on boards, Choi did not explicitly disclose a switch baseboard comprising switches to interconnect nodes.
However, in an analogous art, Wang disclosed a switch baseboard comprising switches to interconnect nodes (Figure 2, first switching chip 203 on first switching fabric board 10. Figure 7A showing a second switching chip 702 on the same first switching fabric board 10. Paragraph 63, the first switching fabric board is connected to the backplane through insertion or welding (i.e., switch baseboard)).
One of ordinary skill in the art would have been motivated to combine the teachings of Choi with Wang because the references involve full mesh structure, and as such, are within the same environment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the switch baseboard of Wang with the teachings of Choi in order to have forwarding times be small and short and have high efficiency (Wang, Paragraph 18).
Regarding claim 20, the claim is substantially similar to claim 12 and is rejected under the same rationale.
Regarding claims 2, 14, the limitations of claims 1, 12, have been addressed. Choi and Wang disclosed:
wherein the switches comprise a first switch comprising: a first set of ports associated with the first layer (Choi, Figure 2A, Paragraph 65, four nodes and six communication links in a one dimensional configuration. Ports P0-P2 connect to other nodes within the cluster); and
a second set of ports associated with the second layer (Choi, Figure 4A, Paragraph 73, communication links of the second dimension where each node is now connected to nodes that are outside of the cluster through ports P3-P5).
Regarding claims 3, 15, the limitations of claims 2, 14, have been addressed. Choi and Wang disclosed:
wherein the first set of ports are associated with a first bandwidth that is different from a second bandwidth associated with the second set of ports (Choi, Paragraph 94, service levels of communication links can vary in different quarters. Different allocations of bandwidth within a transmission medium occur such as the service levels varying between the different dimensions).
Regarding claims 4, 16, the limitations of claims 1, 12, have been addressed. Choi and Wang disclosed:
wherein the second layer further comprises inter-cluster connections to connect the first node of the first cluster to a first node of the fourth cluster by one hop (Choi, Figure 4A, N0 port P4 connected to N8 port P4 by one communication link).
Regarding claim 5, the limitations of claim 4 have been addressed. Choi and Wang disclosed:
wherein the second layer further comprises inter-cluster connections to connect: a second node (Choi, Figure 4A N1) of the first cluster (Choi, Figure 4A, 410) to:
a second node (Choi, Figure 4A, N5) of the second cluster by one hop (Choi, Figure 4A, N1 port p3 to N5 port p5) ;
a second node (Choi, Figure 4A, N13) of the third cluster (Choi, Figure 4A, 440) by one hop (Choi, Figure 4A, N1 port p5 to N13 port p3); and
a second node (Choi, Figure 4A, N9) of the fourth cluster (Choi, Figure 4A, 430) by one hop (Choi, Figure 4A, N1 port p4 to N9 port p4); and
a third node (Choi, Figure 4A, N3) of the first cluster (Choi, Figure 4A 410) to: a third node (Choi, Figure 4A, N7) of the second cluster by one hop (Choi, Figure 4A, N3 port p5 to N7 port p3);
a third node (Choi, Figure 4A, N15) of the third cluster (Choi, Figure 4A, 440) by one hop (Choi, Figure 4A, N3 port p3 to N15 port p5); and
a third node (Choi, Figure 4A, N11) of the fourth cluster (Choi, Figure 4A, 430) by one hop (Choi, Figure 4A, N3 port p4 to N11 port p4); and
a fourth node (Choi, Figure 4A, N2) of the first cluster (Cho, Figure 4A, 410) to: a fourth node (Choi, Figure 4A, N6) of the second cluster (Choi, Figure 4A, 420) by one hop (Choi, Figure 4A, N2 port p3 to N6 port p5);
a fourth node (Choi, Figure 4A, N14) of the third cluster (Choi, Figure 4A 440) by one hop (Choi, Figure 4A, N2 port p5 to N14 port p3); and
a fourth node (Choi, Figure 4A, N10) of the fourth cluster (Choi, Figure 4A, 430) by one hop (Choi, Figure 4A, N2 port p4 to N10 port p4).
Regarding claim 6, the limitations of claim 1 have been addressed. Choi and Wang disclosed:
wherein: the first layer comprises a first port having a first bandwidth; the second layer comprises a second port having a second bandwidth; and the second bandwidth is greater than the first bandwidth (Choi, Figure 2A, Paragraph 65, four nodes and six communication links in a one dimensional configuration. Ports P0-P2 connect to other nodes within the cluster. Figure 4A, Paragraph 73, communication links of the second dimension where each node is now connected to nodes that are outside of the cluster through ports P3-P5. Paragraph 94, service levels of communication links can vary in different quarters. Different allocations of bandwidth within a transmission medium occur such as the service levels varying between the different dimensions).
Regarding claim 8, the limitations of claim 1 have been addressed. Choi and Wang disclosed:
wherein the inter-cluster connections form hyper-torus connections between the nodes (Choi, Paragraph 49, quad node full mesh with dimension driven hyper-torus clustering architecture is provided).
Regarding claims 9, 17, the limitations of claims 1, 13, have been addressed. Choi and Wang disclosed:
wherein the nodes comprise memory and are interconnected to form a memory pool (Choi, Figure 1B showing that nodes comprise both working memory and memory in both the processing and router portions).
Regarding claims 11, 19, the limitations of claims 1, 13, have been addressed. Choi and Wang disclosed:
wherein: the switch baseboard (Wang, Figure 2, first switching chip 203 on first switching fabric board 10. Figure 7A showing a second switching chip 702 on the same first switching fabric board 10. Paragraph 63, the first switching fabric board is connected to the backplane through insertion or welding (i.e., switch baseboard)) is a first switch baseboard of n switch baseboards of the system, n being an integer greater than one (Wang, Figure 5 showing first-fourth switching boards); and the n switch baseboards support 16 x n nodes (Choi, Figure 6A showing 16 quad full mesh networks).
For motivation, please refer to claim 1.
Regarding claim 13, the limitations of claim 12 have been addressed. Choi and Wang disclosed:
wherein the second layer further comprises inter-cluster connections to connect the first node (Choi, Figure 4A, N0) of the first cluster (Choi, Figure 4A, 410) to: a first node (Choi, Figure 4A, N4) of the second cluster (Choi, Figure 4A, 420) by one hop (Choi, Figure 4A, N0 port p5 to N4 port p3 by one communication link); and
a first node (Choi, Figure 4A, N8) of the fourth cluster (Choi, Figure 4A, N8) by one hop (Choi, Figure 4A, N0 port p4 to N8 port p4 by one communication link).
2. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2018/0139267) in view of Wang et al. (US 2025/0016116) and Wong (US 2020/0336386).
Regarding claim 7, the limitations of claim 6 have been addressed. Choi and Wang disclosed:
wherein: the first layer comprises a third port (Choi, Figure 2A, port p2) having a third bandwidth that is less than the second bandwidth (Choi, Paragraph 49, when a link is assigned to a dimension such as the first dimension, it represents a length of the link where a lower dimension corresponds to shorter links which connects nodes that are closer together. A higher dimension corresponds to longer links that connect nodes further apart. Paragraph 94, service levels of communication links can vary in different quarters. Different allocations of bandwidth within a transmission medium occur such as the service levels varying between the different dimensions, for example, shorter links would require less bandwidth than longer links).
While Choi and Wang disclosed multiplexing (Choi, Paragraph 48), Choi and Wang did not explicitly disclose the first port is configured to send a first signal to a bundling-circuit; the third port is configured to send a second signal to the bundling-circuit; and an output of the bundling-circuit is connected to the second port.
However, in an analogous art, Wong disclosed the first port is configured to send a first signal to a bundling-circuit; the third port is configured to send a second signal to the bundling-circuit; and an output of the bundling-circuit is connected to the second port (Paragraph 9, traffic aggregation with multiplexing frames or packets. Data aggregation through multiplexing (i.e., bundling circuit) from different data streams (i.e., signal) ensure higher utilization of the communication channels and efficient management of cost. Data switching is based on aggregation where each port (i.e., third port) is connected and aggregated from all other ports. The data is aggregated before transmitting on to uplink (i.e., second port)).
One of ordinary skill in the art would have been motivated to combine the teachings of Choi and Wang with Wong because the references involve full mesh structure, and as such, are within the same environment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the bundling-circuit of Wong with the teachings of Choi and Wang in order to improve efficiency (Wong, Paragraph 4).
3. Claims 10, 18, are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2018/0139267) in view of Wang et al. (US 2025/0016116) and Jain et al. (US 2022/0029929).
Regarding claims 10, 18, the limitations of claims 1, 13, have been addressed. Choi and Wang did not explicitly disclose:
wherein the switch baseboard is configured to support a cache-coherent protocol.
However, in an analogous art, Jain disclosed wherein the switch baseboard is configured to support a cache-coherent protocol (Paragraph 24, nodes are connected to multiple system switches. Switches can be top of rack, end of row, or middle of rack. Paragraph 26, the system switches include ports that are connected to other ports in the system. The switches utilize Compute Express Link (CXL). Paragraph 100, utilizing CCIX. See applicant’s specification, paragraph 65, defining ‘cache-coherent’ as utilizing CXL or CCIX).
One of ordinary skill in the art would have been motivated to combine the teachings of Choi and Wang with Jain because the references involve full mesh structure, and as such, are within the same environment.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the cache-coherent protocol of Jain with the teachings of Choi and Wang in order to improve optimize nodes and reduce transit time (Jain, Paragraph 28).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Steven C. Nguyen whose telephone number is (571)270-5663. The examiner can normally be reached M-F 7AM - 3PM and alternatively, through e-mail at Steven.Nguyen2@USPTO.gov.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christopher Parry can be reached at 571-272-8328. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.C.N/ Examiner, Art Unit 2451
/Chris Parry/ Supervisory Patent Examiner, Art Unit 2451
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