DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 18, 2026 has been entered.
Response to Arguments
Applicant's arguments with respect to claim 1 have been considered but are moot in view of the new ground(s) of rejection. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “first storage unit”, “supply unit”, “first photoelectric conversion unit”, “second storage unit”, “first control unit”, “second photoelectric conversion unit”, “third storage unit”, and “second control unit”, in claims 1-3, 6, 9, 11-12, and 14-15.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5 and 8-10 of U.S. Patent No. 11,800,252. Although the claims at issue are not identical, they are not patentably distinct from each other because:
Instant Application Claims
Claims of US Patent 11,800,252
1. An image sensor comprising:
a current source circuit that includes
(i) a first storage unit that stores a voltage that is based on a current supplied from a power supply circuit and
(ii) a supply unit that supplies a current that is based on the voltage stored in the first storage unit; and
a first pixel circuit that includes
(i) a first pixel that has a first photoelectric conversion unit that converts light into an electric charge,
(ii) a first storage circuit that has
(a) a second storage unit that stores a voltage that is based on the current supplied from the supply unit and
(b) a first control unit that controls a connection between the supply unit and the second storage unit, and
(iii) a first current source for supplying, to the first pixel, a current that is based on the voltage stored in the second storage unit.
1. An image sensor, comprising:
an electric current source circuit, the electric current source circuit comprising:
a first storage unit that stores a voltage based on an electric current from a power supply circuit; and
a power supply unit that supplies the electric current stored in the first storage unit;
a first pixel circuit, the first pixel circuit comprising:
a first pixel having a first photoelectric conversion unit that converts light into an electric charge;
a first storage circuit having a second storage unit that stores a voltage based on the electric current from the power supply unit, and
a first control unit that controls a connection between the power supply unit and the second storage unit; and
a first electric current source for supplying an electric current based on the voltage stored in the second storage unit to the first pixel; …
2. The image sensor according to claim 1, wherein
the first control unit includes at least a first switch and a second switch connected in series between the supply unit and the second storage unit.
2. The image sensor according to claim 1, wherein:
the first control unit has at least a first switch and a second switch that are connected in series between the power supply unit and the second storage unit; …
3. The image sensor according to claim 2, wherein:
the first switch is positioned between the supply unit and the second storage unit, and is located closer to the supply unit than to the second switch, and
the first control unit turns off the second switch before turning off the first switch when disconnecting the supply unit and the second storage unit.
3. The image sensor according to claim 2, wherein:
the first switch is provided closer to the power supply unit in comparison with the second switch between the power supply unit and the second storage unit;
the third switch is provided closer to the power supply unit in comparison with the fourth switch between the power supply unit and the third storage unit; …
4. The image sensor according to claim 3, wherein:
the first current source includes a first transistor that has a drain portion connected to the first pixel and a gate portion connected to the first storage circuit, and
the drain portion of the first transistor is connected to the gate portion of the first transistor via the second switch.
4. The image sensor according to claim 2, wherein:
the first electric current source includes a first transistor having a drain part connected to the first pixel and a gate part connected to the first storage circuit;
…
the drain part of the first transistor is connected to the gate part of the first transistor via the second switch; …
5. The image sensor according to claim 4, wherein the drain portion of the first transistor is connected to the supply portion via the first switch.
5. The image sensor according to claim 4, wherein:
the drain part of the first transistor is connected to the power supply unit via the first switch; …
6. The image sensor according to claim 1, further comprising
a first signal line to which is output a first signal, the first signal being read out from the first pixel and being generated by the electric charge converted by the first photoelectric conversion unit,
wherein the first current source is connected to the first pixel via the first signal line.
8. The image sensor according to claim 6, further comprising:
a first signal line through which the first signal read by the first readout circuit is output; and …
wherein:
the first electric current source is connected to the first pixel via the first signal line; …
7. The image sensor according to claim 1, wherein:
the first photoelectric conversion unit is disposed on a first semiconductor substrate, and
the first storage circuit is disposed on a second semiconductor substrate.
9. The image sensor according to claim 1, wherein:
the first photoelectric conversion unit … are provided on a first semiconductor substrate;
the first storage circuit … are provided on a second semiconductor substrate; …
8. The image sensor according to claim 7, wherein the first semiconductor substrate is stacked on the second semiconductor substrate.
9. …
the first semiconductor substrate is stacked by the second semiconductor substrate.
9. The image sensor according to claim 1, further comprising a second pixel circuit that includes
(i) a second pixel that has a second photoelectric conversion unit that converts light into an electric charge,
(ii) a second storage circuit that has
(a) a third storage unit that stores a voltage that is based on the current supplied from the supply unit and
(b) a second control unit that controls a connection between the supply unit and the third storage unit, and
(iii) a second current source for supplying, to the second pixel, a current that is based on the voltage stored in the third storage unit,
wherein the first pixel circuit and the second pixel circuit are aligned with each other in a column direction.
1. … a second pixel circuit, the second pixel circuit comprising:
a second pixel having a second photoelectric conversion unit that converts light into an electric charge;
a second storage circuit having a third storage unit that stores a voltage based on the electric current from the power supply unit and
a second control unit that controls a connection between the power supply unit and the third storage unit; and
a second electric current source for supplying an electric current based on the voltage stored in the third storage unit to the second pixel,
wherein:
the first pixel circuit and the second pixel circuit are provided side by side in a vertical direction within a column.
10. The image sensor according to claim 9, wherein the first pixel circuit and the second pixel circuit are arranged adjacent to each other in the column direction.
1. … wherein:
the first pixel circuit and the second pixel circuit are provided side by side in a vertical direction within a column.
11. The image sensor according to claim 9, wherein:
the first control unit includes at least a first switch and a second switch connected in series between the supply unit and the second storage unit, and
the second control unit includes at least a third switch and a fourth switch connected in series between the supply unit and the third storage unit.
2. The image sensor according to claim 1, wherein:
the first control unit has at least a first switch and a second switch that are connected in series between the power supply unit and the second storage unit; and
the second control unit has at least a third switch and a fourth switch that are connected in series between the power supply unit and the third storage unit.
12. The image sensor according to claim 11, wherein:
the first switch is disposed between the supply unit and the second storage unit, closer to the supply unit than to the second switch;
the third switch is disposed between the supply unit and the third storage unit, closer to the supply unit than to the fourth switch;
the first control unit turns off the second switch before turning off the first switch when disconnecting the supply unit and the second storage unit; and
the second control unit turns off the fourth switch before turning off the third switch when disconnecting the supply unit and the third storage unit.
3. The image sensor according to claim 2, wherein:
the first switch is provided closer to the power supply unit in comparison with the second switch between the power supply unit and the second storage unit;
the third switch is provided closer to the power supply unit in comparison with the fourth switch between the power supply unit and the third storage unit;
the first control unit turns off the second switch before the first switch when the first control unit disconnects the power supply unit and the second storage unit; and
the second control unit turns off the fourth switch before the third switch when the second control unit disconnects the power supply unit and the third storage unit.
13. The image sensor according to claim 12, wherein:
the first current source includes a first transistor that has a drain portion connected to the first pixel and a gate portion connected to the first storage circuit,
the second current source includes a second transistor that has a drain portion connected to the second pixel and a gate portion connected to the second storage circuit,
the drain portion of the first transistor is connected to the gate portion of the first transistor via the second switch, and
the drain portion of the second transistor is connected to the gate portion of the second transistor via the fourth switch.
4. The image sensor according to claim 2, wherein:
the first electric current source includes a first transistor having a drain part connected to the first pixel and a gate part connected to the first storage circuit;
the second electric current source includes a second transistor having a drain part connected to the second pixel and a gate part connected to the second storage circuit;
the drain part of the first transistor is connected to the gate part of the first transistor via the second switch; and
the drain part of the second transistor is connected to the gate part of the second transistor via the fourth switch.
14. The image sensor according to claim 13, wherein:
the drain portion of the first transistor is connected to the supply unit via the first switch, and
the drain portion of the second transistor is connected to the supply unit via the third switch.
5. The image sensor according to claim 4, wherein:
the drain part of the first transistor is connected to the power supply unit via the first switch; and
the drain part of the second transistor is connected to the power supply unit via the third switch.
15. The image sensor according to claim 9, further comprising:
a first signal line to which is output a first signal, the first signal being read out from the first pixel and being generated by the charge converted by the first photoelectric conversion unit; and
a second signal line to which is output a second signal, the second signal being read out from the second pixel and being generated by the charge converted by the second photoelectric conversion unit, wherein
the first current source is connected to the first pixel via the first signal line, and
the second current source is connected to the second pixel via the second signal line.
8. The image sensor according to claim 6, further comprising:
a first signal line through which the first signal read by the first readout circuit is output; and
a second signal line through which the second signal read by the second readout circuit is output, wherein:
the first electric current source is connected to the first pixel via the first signal line; and
the second electric current source is connected to the second pixel via the second signal line.
16. The image sensor according to claim 9, wherein:
the first photoelectric conversion unit and the second photoelectric conversion unit are disposed on a first semiconductor substrate, and
the first storage circuit and the second storage circuit are disposed on a second semiconductor substrate.
9. The image sensor according to claim 1, wherein:
the first photoelectric conversion unit and the second photoelectric conversion unit are provided on a first semiconductor substrate;
the first storage circuit and the second storage circuit are provided on a second semiconductor substrate; …
17. The image sensor according to claim 16, wherein the first semiconductor substrate is stacked on the second semiconductor substrate.
9. …
the first semiconductor substrate is stacked by the second semiconductor substrate.
18. An imaging device comprising the image sensor according to claim 1.
10. An image device, comprising: the image sensor according to claim 1.
In view of the foregoing, Claims 1-18 of the pending application are an obvious variant and encompassed by claims 1-5 and 8-10 of US Patent 11,800,252.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Sony (JP 2006-186467), in view of Hikosaka et al. (US Pub. 2014/0263966). The Examiner notes that with respect to the Sony reference, the citations provided below refer to the machine translation of the reference.
In regard to claim 1, note Sony discloses an image sensor, comprising a current source circuit (paragraphs 0154-0156, and figure 7: 410) that includes a supply unit that supplies a current (paragraphs 0154-0156, and figure 7: 416), and a first pixel circuit that includes a first pixel that has a first photoelectric conversion unit that converts light into an electric charge (paragraphs 0058, 0092, and figures 1-2: 3, 32), a first storage circuit that has a second storage unit (figure 7: 404) that stores a voltage that is based on the current supplied from the supply unit (figure 7: 416), and a first control unit that controls a connection between the supply unit and the second storage unit (paragraphs 0156-0160, and figure 7: 404, 406, 407, 416; the switches 406 and 407 are connected in series with one another, and are controlled in order to control the connection between the power supply unit 416 and the second storage unit 404), and a first current source for supplying, to the first pixel, a current that is based on the voltage stored in the second storage unit (paragraphs 0156-0160, and figure 7: 402, 404; the transistor 402 is considered to be an electric current source that supplies the pixel with an electric current on the vertical signal line based on the voltage stored in the storage unit 404).
Therefore, it can be seen that the primary reference fails to explicitly disclose that a first storage unit that stores a voltage that is based on a current supplied from a power supply circuit, and that the supply unit supplies a current that is based on the voltage stored in the first storage unit
In analogous art, Hikosaka discloses an image sensor having an electric current source circuit that supplies an electric current to the pixel circuit (paragraphs 0131-0134, 0139, and figure 19: 229, 234, 239), wherein the electric current source circuit includes a first storage unit that stores a voltage that is based on a current supplied from a power supply circuit (paragraphs 0131-0134, 0139, and figure 19: 234, 239; the storage unit 234 stores a voltage based on the electric current from power supply 239), and a supply unit that supplies a current that is based on the voltage stored in the first storage unit to the pixel circuit (paragraphs 0131-0134, 0139, and figure 19: 234, 229; the power supply unit 229 supplies electric current to pixel circuit 230). Hikosaka teaches that the use of that the electric current source circuit that includes a first storage unit that stores a voltage that is based on a current supplied from a power supply circuit, and that the supply unit supplies a current that is based on the voltage stored in the first storage unit is preferred in order to reduce noise (paragraphs 0131-0133). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the primary reference such that the electric current source circuit includes a first storage unit that stores a voltage that is based on a current supplied from a power supply circuit, and that the supply unit supplies a current that is based on the voltage stored in the first storage unit in order to reduce noise, as suggested by Hikosaka.
In regard to claim 2, note Sony discloses that the first control unit includes at least a first switch and a second switch connected in series between the supply unit and the second storage unit (paragraphs 0156-0160, and figure 7: 404, 406, 407, 416; the switches 406 and 407 are connected in series with one another, and are controlled in order to control the connection between the power supply unit 416 and the second storage unit 404).
In regard to claim 3, note Sony discloses that the first switch is positioned between the supply unit and the second storage unit, and is located closer to the supply unit than to the second switch (paragraphs 0156-0160, and figure 7: 404, 406, 407, 416; the first switch 407 is closer to the power supply unit 416 than the second switch 406), and the first control unit turns off the second switch before turning off the first switch when disconnecting the supply unit and the second storage unit (paragraphs 0161, 0175, 0177, and figures 7-8: ΦA, ΦB, 406, 407; the first switch 407 is controlled by signal ΦA, and the second switch 406 is controlled by signal ΦB, wherein when disconnecting the power supply unit 416 and the storage unit 404, signal ΦB is stopped prior to signal ΦA, in order to turn off the second switch 406 prior to switch 407).
In regard to claim 4, note Sony discloses the first current source includes a first transistor that has a drain portion connected to the first pixel and a gate portion connected to the first storage circuit (paragraphs 0156-0160, and figure 7: 402, 404; the transistor 402 is considered to be an electric current source, wherein the drain is connected to pixel through the column line, and the gate is connected to the storage unit 404), and the drain portion of the first transistor is connected to the gate portion of the first transistor via the second switch (paragraphs 0156-0160, and figure 7: 402, 406; the drain of the electric current source transistor 402 is coupled to the gate through the second switch 406).
In regard to claim 5, note Sony discloses that the drain portion of the first transistor is connected to the supply portion via the first switch (paragraphs 0156-0160, and figure 7: 402, 407, 416; the drain of the transistor 402 is connected to the power supply unit 416 through the first switch 407).
In regard to claim 6, note Sony discloses a first signal line to which is output a first signal, the first signal being read out from the first pixel and being generated by the electric charge converted by the first photoelectric conversion unit (paragraphs 0089-0097, and figure 2: 53/18; the signal output by the pixel readout circuit is output to the vertical signal line 53/18), wherein the first current source is connected to the first pixel via the first signal line (paragraphs 0156-0160, and figure 7: 402, 404; the transistor 402 is considered to be the electric current source that supplies the pixel with an electric current on the vertical signal line).
In regard to claim 18, note Sony discloses an image device, comprising the image sensor according to claim 1 (paragraph 0056; the image sensor can be used within a camera).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Sony (JP 2006-186467), in view of Hikosaka et al. (US Pub. 2014/0263966), and further in view of Peng et al. (US Patent 9,270,906).
In regard to claim 7, note the primary reference of Sony discloses the use of an image sensor, as discussed with respect to claim 1 above. Therefore, it can be seen that the primary reference fails to explicitly disclose that the first photoelectric conversion unit is disposed on a first semiconductor substrate, and the first storage circuit is disposed on a second semiconductor substrate.
In analogous art, Peng discloses an image sensor in which the photoelectric conversion unit is provided on a first semiconductor substrate (column 6, lines 8-33, and figure 4: 17), and the storage circuit is provided on a second semiconductor substrate (column 6, lines 8-33, column 6, line 60 – column 7, line 6, and figure 4: 44). Peng teaches that the use of stacked semiconductor substrates in which the photoelectric conversion unit is provided on a first semiconductor substrate, and the storage circuit is provided on a second semiconductor substrate is preferred in order to improve the capture rate of the image sensor (column 1, lines 18-30, and column 3, lines 18-21). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the primary reference such that the first photoelectric conversion unit is disposed on a first semiconductor substrate, and the first storage circuit is disposed on a second semiconductor substrate, in order to improve the capture rate of the image sensor, as suggested by Peng.
In regard to claim 8, note Peng discloses that the first semiconductor substrate is stacked on the second semiconductor substrate (column 6, lines 8-33, and figure 4).
Allowable Subject Matter
Claims 9-17 would be allowable if rewritten to overcome the Double Patenting rejection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
This is a continuation of applicant's earlier Application No. 16/590,719. All claims are identical to, patentably indistinct from, or have unity of invention with the invention claimed in the earlier application (that is, restriction (including lack of unity) would not be proper) and could have been finally rejected on the grounds and art of record in the next Office action if they had been entered in the earlier application. Accordingly, THIS ACTION IS MADE FINAL even though it is a first action in this case. See MPEP § 706.07(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISS S YODER III whose telephone number is (571)272-7323. The examiner can normally be reached M-F 9:00-5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lin Ye can be reached at (571) 272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.Y./Examiner, Art Unit 2638
/LIN YE/Supervisory Patent Examiner, Art Unit 2638
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