DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 10644664)
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With respect to claim 1, Chen et al. (US 10644664) discloses a harmonics cancellation circuit, the circuit comprising: a plurality of capacitors (C1) having one end connected to a source node of a plurality of amplifiers (I-III)) receiving a plurality of quadrature phase signals, respectively; and a virtual ground (ground) to which another end of each of the plurality of capacitors (C1) is commonly connected, wherein the source node of the plurality of amplifiers is connected to a plurality of current controllers (110), respectively.
With respect to claim 2,Chen discloses the circuit of Claim 1, wherein: a first amplifier (i.e. I) among the plurality of amplifiers includes a first transistor (106) and a second transistor (108) that amplify a first quadrature phase signal (I+) (at input) among the plurality of quadrature phase signals, a source node of the first amplifier is connected to a source node of the first transistor, a source node of the second transistor, and a drain of a first current controller (110) among the plurality of current controllers, the first current controller controls a tail current of the source node of the first amplifier.
With respect to claim 3, Chen discloses the circuit of Claim 2, wherein: one end of a first capacitor (C1) among the plurality of capacitors is connected to the source node of the first amplifier (I), and another end of the first capacitor is connected to the virtual ground (GND).
With respect to claim 4, Chen discloses the circuit of Claim 1, wherein: a second amplifier (II) among the plurality of amplifiers includes a third transistor (106) and a fourth transistor (108) that amplify a second quadrature phase signal (I-) (at input) among the plurality of quadrature phase signals, a source node of the second amplifier is connected to a source node of the third transistor (106), a source node of the fourth transistor (108), and a drain of a second current controller (110) among the plurality of current controllers, the second current controller controls a tail current of the source node of the second amplifier.
With respect to claim 5, Chen (i.e. figure 4) discloses the circuit of Claim 4, wherein: one end of a second capacitor (C2) among the plurality of capacitors is connected to the source node of the second amplifier, and another end of the second capacitor is connected to the virtual ground (ground).
With respect to claim 6, Chen discloses the circuit of Claim 1, wherein: a third amplifier (III) among the plurality of amplifiers includes a fifth transistor (106) and a sixth transistor (108) that amplify a third quadrature phase signal (Q+) (input) among the plurality of quadrature phase signals, a source node of the third amplifier is connected to a source node of the fifth transistor, a source node of the sixth transistor, and a drain of a third current controller (110) among the plurality of current controllers, the third current controller controls a tail current of the source node of the third amplifier.
With respect to claim 7, Chen discloses the circuit of Claim 6, wherein: one end of a third capacitor (C3) among the plurality of capacitors is connected to the source node of the third amplifier, and another end of the third capacitor is connected to the virtual ground (ground).
With respect to claim 8, Chen discloses the circuit of Claim 1, wherein: a fourth amplifier (IV or IA) among the plurality of amplifiers includes a seventh transistor (106) and an eighth transistor (108) that amplify a fourth quadrature phase signal (Q-)(at input) among the plurality of quadrature phase signals, a source node of the fourth amplifier is connected to a source node of the seventh transistor, a source node of the eighth transistor, and a drain of a fourth current controller among the plurality of current controllers, the fourth current controller (OC or 110) controls a tail current of the source node of the fourth amplifier.
With respect to claim 9,Chen discloses the circuit of Claim 8, wherein: one end of a fourth capacitor (C1 connected via RD) among the plurality of capacitors is connected to the source node of the fourth amplifier (OC or IIIA), and another end of the fourth capacitor is connected to the virtual ground (ground).
With respect to claim 10, Chen discloses a differential vector synthesizer, the synthesizer comprising: a plurality of amplifiers (I-IIIA or I-OC) that amplify a plurality of quadrature phase signals (at input), respectively; a plurality of current controllers (110 and OC) that control a tail current of a source node of the plurality of amplifiers, respectively; a plurality of capacitors (C1 or C1-C3) having one end connected to the source node of the plurality of amplifiers, respectively; and a virtual ground (at ground) to which another end of each of the plurality of capacitors is commonly connected.
With respect to claim 11, Chen discloses the synthesizer of Claim 10, wherein: a first amplifier (I) among the plurality of amplifiers includes a first transistor (106) and a second transistor (108) that amplify a first quadrature phase signal (I+) (at input) among the plurality of quadrature phase signals, a source node of the first amplifier is connected to a source node of the first transistor, a source node of the second transistor, and a drain of a first current controller among the plurality of current controllers, one end of a first capacitor (C1) among the plurality of capacitors is connected to the source node of the first amplifier, and another end of the first capacitor is connected to the virtual ground.(at ground)
With respect to claim 12, Chen discloses the synthesizer of Claim 10, wherein: a second amplifier (II) among the plurality of amplifiers includes a third transistor (106) and a fourth transistor (108) that amplify a second quadrature phase signal (I-)(at input) among the plurality of quadrature phase signals, a source node of the second amplifier is connected to a source node of the third transistor, a source node of the fourth transistor, and a drain of a second current (110) controller among the plurality of current controllers, one end of a second capacitor (C2) among the plurality of capacitors is connected to the source node of the second amplifier, and another end of the second capacitor is connected to the virtual ground (at ground).
With respect to claim 13, Chen discloses the synthesizer of Claim 10, wherein: a third amplifier (III) among the plurality of amplifiers includes a fifth transistor(106) and a sixth transistor (108) that amplify a third quadrature phase signal (Q-H) (at input) among the plurality of quadrature phase signals, a source node of the third amplifier is connected to a source node of the fifth transistor, a source node of the sixth transistor, and a drain of a third current controller (110) among the plurality of current controllers, one end of a third capacitor (C3) among the plurality of capacitors is connected to the source node of the third amplifier, and another end of the third capacitor is connected to the virtual ground (at ground).
With respect to claim 14, Chen discloses the synthesizer of Claim 10, wherein: a fourth amplifier (IV/OC or IIIA) among the plurality of amplifiers includes a seventh transistor (106) and an eighth transistor (108) that amplify a fourth quadrature phase signal (Q-) (at input) among the plurality of quadrature phase signals, a source node of the fourth amplifier is connected to a source node of the seventh transistor, a source node of the eighth transistor, and a drain of a fourth current controller among the plurality of current controllers ,one end of a fourth capacitor (C1 connected via RD) among the plurality of capacitors is connected to 4 the source node of the fourth amplifier, and another end of the fourth capacitor is connected to the virtual ground (at ground).
Response to Arguments
Applicant's arguments filed 3/23/2026 have been fully considered but they are not persuasive.
Applciant argues the capacitors are not connected to the drains of the amplifiers. The Examiner disagrees. The capacitors are connected to the drains through 106 and 108 respectively. Furthermore, it would be obvious to use PMOS instead of NMOS in the circuit which would produce a direct connection of the capacitors to the drains of the transistors. As such the current rejection anticipates the claim language and would be obvious over a direct connection between the drains and the capacitors.
Allowable Subject Matter
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
With respect to claim 15, the prior art of record fails to suggest or disclose a radio frequency integrated circuit comprising: a synthesizer that synthesizes a plurality of amplified quadrature phase signals to output an output signal; and at least one digital to analog converter (DAC) that controls a phase and a gain of the output signal, wherein one end of a plurality of capacitors is connected to the source node of the plurality of amplifiers, respectively, and an other end of each of the plurality of capacitors is commonly connected to a virtual ground.
Here, the DAC as disclosed with relation the quadrature and connections to the amplifiers is not shown in the prior art as disclosed.
Claims 16-20 are allowable based on the dependence of claim 15.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849
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