DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichikawa et al. (US 6,285,235 B1) in view of Ohi et al. (US 2004/0027762 A1).
Regarding claim 1, Ichikawa et al. teach a system (gate control circuit 113; FIG. 18) comprising:
a semiconductor element (IGBT 1; FIG. 18) including
a gate (terminal G; FIG. 18),
a first main terminal that is a source or an emitter (terminal E; FIG. 18), and
a second main terminal that is a drain or a collector (terminal C; FIG. 18);
a push-pull circuit (transistors 23A and 23B; FIG. 18);
a gate resistance provided in the push-pull circuit or between the push-pull circuit and the gate (gate resistor 4; FIG. 18);
a capacitor coupled in parallel with the gate resistance (capacitor 6A; FIG. 18; when diode 5A turns on, capacitor 6A is effectively parallel to gate resistor 4).
Further regarding claim 1, Ichikawa et al. do not teach the system is a degradation diagnosis system; and
a degradation diagnosis device configured to diagnose degradation of the semiconductor element based on a capacitor voltage that is generated across the capacitor.
Further regarding claim 1, Ohi et al. teach a degradation diagnosis system (the IGBT 11 is turned on with the IGBT short-circuited; [0107]; Figs 21-22; a drive circuit for driving a power semiconductor device comprising a gate charge detector 19; FIG. 23); and
a degradation diagnosis device configured to diagnose degradation of a semiconductor element based on a capacitor voltage that is generated across a capacitor (a CR circuit that consist of the resistor 57 and the capacitor 58 integrates a gate current Ig flowing in an IGBt; [0112]; FIG. 23; the AND circuit 56 sends out a signal at a High level indicating the detection of an abnormality; [0115]) for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate the system is a degradation diagnosis system; and a degradation diagnosis device configured to diagnose degradation of the semiconductor element based on a capacitor voltage that is generated across the capacitor, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 2, Ichikawa et al. do not teach wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element based on a voltage value, in a case where the capacitor voltage is equal to a voltage between the gate and the first main terminal.
Further regarding claim 2, Ohi et al. teach the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element based on a voltage value, in a case where the capacitor voltage is equal to a voltage between the gate and the first main terminal (voltage across capacitor 58; FIG. 23; voltage divider using resistor 36 and resistor 37 divides Vge when the emitter terminal is connected to ground) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element based on a voltage value, in a case where the capacitor voltage is equal to a voltage between the gate and the first main terminal, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 3, Ichikawa et al. do not teach wherein the voltage value is a maximum value of the capacitor voltage.
Further regarding claim 3, Ohi et al. teach the voltage value is a maximum value of the capacitor voltage (because the voltage delivered from the differential amplifier 59 doesn’t exceed the reference voltage applied to the comparator 38 even after the time t5 when a short circuit occurs in the IGBT 11, the output signal of the comparator 38 becomes a Low level and a signal at a High level is delivered from the inverter 55 to the AND circuit 56; [0115]) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the voltage value is a maximum value of the capacitor voltage, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 4, Ichikawa et al. do not teach a peak hold circuit configured to hold the maximum value of the capacitor voltage during a predetermined time period, wherein the voltage value is the maximum value held by the peak hold circuit.
Further regarding claim 4, Ohi et al. teach a peak hold circuit configured to hold the maximum value of the capacitor voltage during a predetermined time period, wherein the voltage value is the maximum value held by the peak hold circuit (a time period during which a sampler 16 allows the detection process of detecting the amount of gate charge; [0105]; the maximum voltage at the capacitor 58 is held and sampled with a predetermined RC decay time; FIG. 23) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate a peak hold circuit configured to hold the maximum value of the capacitor voltage during a predetermined time period, wherein the voltage value is the maximum value held by the peak hold circuit, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 5, Ichikawa et al. do not teach wherein the peak hold circuit is configured to sample the maximum value in an operating cycle of the semiconductor element.
Further regarding claim 5, Ohi et al. teach the peak hold circuit is configured to sample the maximum value in an operating cycle of the semiconductor element (Vg cycles On and OFF; FIG. 11; a time period during which a sampler 16 allows the detection process of detecting the amount of gate charge; [0105]; the maximum voltage at the capacitor 58 is held and sampled with a predetermined RC decay time; FIG. 23) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate a peak hold circuit configured to hold the maximum value of the capacitor voltage during a predetermined time period, wherein the voltage value is the maximum value held by the peak hold circuit, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 6, Ichikawa et al. do not teach wherein the operating cycle is a zero-crossing period of an output voltage or an output current of the semiconductor element.
Further regarding claim 6, Ohi et al. teach the operating cycle is a zero-crossing period of an output voltage or an output current of the semiconductor element (Vg cycles ON and OFF; FIG. 11) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the operating cycle is a zero-crossing period of an output voltage or an output current of the semiconductor element, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 7, Ichikawa et al. do not teach wherein the operating cycle is a carrier cycle of the semiconductor element.
Further regarding claim 7, Ohi et al. teach the operating cycle is a carrier cycle of the semiconductor element (Vg cycles ON and OFF; FIG. 11) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the operating cycle is a carrier cycle of the semiconductor element, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 8, Ichikawa et al. do not teach wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element based on the capacitor voltage and information related to the semiconductor element.
Further regarding claim 8, Ohi et al. teach the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element based on the capacitor voltage and information related to the semiconductor element (integral of gate current or amount of charge and V1 and V2; Figs 21-23) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element based on the capacitor voltage and information related to the semiconductor element, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 9, Ichikawa et al. do not teach wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, upon occurrence of a condition in which the information related to the semiconductor element satisfies a predetermined condition.
Further regarding claim 9, Ohi et al. teach the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, upon occurrence of a condition in which the information related to the semiconductor element satisfies a predetermined condition (when the amount of gate charge is equal to or less than a reference value, recognizing that an abnormality occurs in the IGBT 11; [0105]) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, upon occurrence of a condition in which the information related to the semiconductor element satisfies a predetermined condition, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 10, Ichikawa et al. do not teach wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, by comparing the capacitor voltage with a threshold that is set based on the information related to the semiconductor element.
Further regarding claim 10, Ohi et al. teach the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, by comparing the capacitor voltage with a threshold that is set based on the information related to the semiconductor element (reference voltage as defined by resistors 60 and 61 is based on information related to IGBT 11; FIG. 23) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, by comparing the capacitor voltage with a threshold that is set based on the information related to the semiconductor element, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 11, Ichikawa et al. do not teach wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element based on the information related to the semiconductor element, upon occurrence of a condition in which the capacitor voltage is greater than a constant threshold.
Further regarding claim 11, Ohi et al. teach the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element based on the information related to the semiconductor element, upon occurrence of a condition in which the capacitor voltage is greater than a constant threshold (because the voltage delivered from the differential amplifier 59 doesn’t exceed the reference voltage applied to the comparator 38 even after the time t5 when a short circuit occurs in the IGBT 11, the output signal of the comparator 38 becomes a Low level and a signal at a High level is delivered from the inverter 55 to the AND circuit 56; [0115]) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, by comparing the capacitor voltage with a threshold that is set based on the information related to the semiconductor element, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 12, Ichikawa et al. do not teach wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, upon occurrence of a condition in which the information related to the semiconductor element satisfies a predetermined condition, in conjunction with a condition in which the capacitor voltage is greater than a constant threshold.
Further regarding claim 12, Ohi et al. teach the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, upon occurrence of a condition in which the information related to the semiconductor element satisfies a predetermined condition, in conjunction with a condition in which the capacitor voltage is greater than a constant threshold (when the amount of gate charge is equal to or less than a reference value, recognizing that an abnormality occurs in the IGBT 11; [0105]; because the voltage delivered from the differential amplifier 59 doesn’t exceed the reference voltage applied to the comparator 38 even after the time t5 when a short circuit occurs in the IGBT 11, the output signal of the comparator 38 becomes a Low level and a signal at a High level is delivered from the inverter 55 to the AND circuit 56; [0115]) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the degradation diagnosis device is configured to diagnose the degradation of the semiconductor element, by comparing the capacitor voltage with a threshold that is set based on the information related to the semiconductor element, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 13, Ichikawa et al. teach a method (method of operating the gate control circuit 113; FIG. 18) comprising:
driving a semiconductor element (IGBT 1; FIG. 18) based on a capacitor voltage that is generated across a capacitor (capacitor 6A; FIG. 18), the capacitor being coupled in parallel with a gate resistance (when diode 5A turns on, capacitor 6A is effectively parallel to gate resistor 4; FIG. 18), and the gate resistance being provided in a push-pull circuit or between a push-pull circuit and a gate of the semiconductor element (transistors 23A and 23B; FIG. 18).
Further regarding claim 13, Ichikawa et al. do not teach the method is a degradation diagnosis method; and the step of driving is a step for diagnosing degradation of the semiconductor element based on the capacitor voltage that is generated across the capacitor.
Further regarding claim 13, Ohi et al. teach a degradation diagnosis method (the IGBT 11 is turned on with the IGBT short-circuited; [0107]; Figs 21-22; a drive circuit for driving a power semiconductor device comprising a gate charge detector 19; FIG. 23); and a step for diagnosing degradation of a semiconductor element based on a capacitor voltage that is generated across a capacitor (a CR circuit that consist of the resistor 57 and the capacitor 58 integrates a gate current Ig flowing in an IGBt; [0112]; FIG. 23; the AND circuit 56 sends out a signal at a High level indicating the detection of an abnormality; [0115]) for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate the method is a degradation diagnosis method; and the step of driving is a step for diagnosing degradation of the semiconductor element based on the capacitor voltage that is generated across the capacitor, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 14, Ichikawa et al. teach a power converter (circuit diagram of a power converter circuit; FIG. 25) comprising:
a semiconductor element (IGBT 1; FIG. 18) including
a gate (terminal G; FIG. 18),
a first main terminal that is a source or an emitter (terminal E; FIG. 18), and
a second main terminal that is a drain or a collector (terminal C; FIG. 18);
a push-pull circuit (transistors 23A and 23B; FIG. 18);
a gate resistance provided in the push-pull circuit or between the push-pull circuit and the gate (gate resistor 4; FIG. 18);
a capacitor coupled in parallel with the gate resistance (capacitor 6A; FIG. 18; when diode 5A turns on, capacitor 6A is effectively parallel to gate resistor 4).
Further regarding claim 14, Ichikawa et al. do not teach a degradation diagnosis device configured to diagnose degradation of the semiconductor element based on a capacitor voltage that is generated across the capacitor; and a peak hold circuit configured to hold a maximum value of the capacitor voltage during a predetermined time period, in an operating cycle of the semiconductor element.
Further regarding claim 14, Ohi et al. teach a degradation diagnosis device configured to diagnose degradation of a semiconductor element based on a capacitor voltage that is generated across a capacitor (a CR circuit that consist of the resistor 57 and the capacitor 58 integrates a gate current Ig flowing in an IGBt; [0112]; FIG. 23; the AND circuit 56 sends out a signal at a High level indicating the detection of an abnormality; [0115]); and a peak hold circuit configured to hold a maximum value of the capacitor voltage during a predetermined time period, in an operating cycle of the semiconductor element (a time period during which a sampler 16 allows the detection process of detecting the amount of gate charge; [0105]; the maximum voltage at the capacitor 58 is held and sampled with a predetermined RC decay time; FIG. 23) for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate a degradation diagnosis device configured to diagnose degradation of the semiconductor element based on a capacitor voltage that is generated across the capacitor; and a peak hold circuit configured to hold a maximum value of the capacitor voltage during a predetermined time period, in an operating cycle of the semiconductor element, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Regarding claim 15, Ichikawa et al. do not teach wherein the operating cycle is a zero-crossing period of an output voltage or an output current of the semiconductor element.
Further regarding claim 15, Ohi et al. teach the operating cycle is a zero-crossing period of an output voltage or an output current of the semiconductor element (Vg cycles ON and OFF; FIG. 11) protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to incorporate wherein the operating cycle is a zero-crossing period of an output voltage or an output current of the semiconductor element, as taught by Ohi et al., into Ichikawa et al. for the purpose of protecting the power semiconductor device upon recognizing an occurrence of an abnormality in the power semiconductor device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENDRICK X LIU whose telephone number is (571)270-3798. The examiner can normally be reached MWFSa 10am-8pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Douglas X Rodriguez can be reached at (571) 431-0716. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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28 August 2026
/KENDRICK X LIU/Examiner, Art Unit 2853
/DOUGLAS X RODRIGUEZ/Supervisory Patent Examiner, Art Unit 2853
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