Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 17 June 2026 for application number 19/958,602.
Claims 1 – 10 are currently amended.
Claims 1 – 13 are presented for examination.
Response to Amendment
Applicant’s amendment filed 17 June 2026 is sufficient to overcome the rejection of claims 1 – 13 based upon the currently amended independent claim 1 and arguments.
Response to Arguments
Applicant’s arguments, filed 17 June 2026, with respect to the rejection(s) of claim(s) 1 – 13 under 35 USC § 103 have been fully considered and are persuasive based upon the currently amended independent claim 1 and arguments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Son et al., US Pub. No. 2023/0251781 A1.
Son, in combination with the prior art of record, reads on the claim limitations based upon the current claim language for independent claim 1. Please see the new grounds of rejection below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. [hereafter as Bang], US Pub. No. 2022/0051714 A1 in view of Kim et al. [hereafter as Kim], US Pub. No. 2023/0123963 A1 and further in view of Son et al. [hereafter as Son], US Pub. No. 2023/0251781 A1.
As per claim 1, Bang discloses an operating method of a semiconductor device, the method comprising:
receiving a read command [“The control logic circuit 150 may receive a command CMD from the external device (e.g., a memory controller 10 of FIG. 17)...”] [para. 0040] [“read operation of the nonvolatile memory device 100”] [para. 0041];
sensing a memory cell adjacent to a target memory cell of the read command [“Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.”] [Abstract] [paras. 0006 and 0008];
sensing the target [selected] memory cell at a first sensing time [“Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.”] [Abstract] [paras. 0006 and 0008] [“…sensed by using different read voltages at different times…”] [para. 0082] [para. 0085];
sensing the target memory cell at a second sensing time [“…the nonvolatile memory device 100 may latch data stored in the selected memory cells at least two times at main sensing latches of the page buffers PB0 to PBn−1.”] [para. 0084] [“Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.”] [Abstract] [paras. 0006 and 0008] [“…sensed by using different read voltages at different times…”] [para. 0082] [para. 0085]; and
outputting, as data, a value sensed at the first sensing time or a value sensed at the second sensing time [“The data block 370 may be connected to the sensing node SO. The data block 370 may receive data stored in the main sensing latch 350 and the adjacent sensing latch 360 through the sensing node SO. In an embodiment, the data block 370 may be implemented with a latch capable of storing data input thereto. The data block 370 may transmit the input data to the data input/output circuit 140 in response to a latch data output signal SLD.”] [para. 0065].
However, Bang does not explicitly disclose outputting on the basis of a sensing value of the memory cell adjacent to the target memory cell;
wherein the value sense at the first sensing time and the values sensed at the second sensing time are stored in different latches.
Kim teaches outputting on the basis of a sensing value of the memory cell adjacent to the target memory cell [“Pieces of data are read from memory cells experiencing word line coupling from an adjacent word line by changing a recovery read level to be applied to a selected word line or changing a develop time of the sensing node on the basis of a programming status of pieces of data of at least one of word lines adjacent to the selected word line and an operating parameter of the non-volatile memory device, thereby achieving a performance improvement.”] [para. 0069].
Bang and Kim are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Bang with Kim in order to modify Bang for “outputting on the basis of a sensing value of the memory cell adjacent to the target memory cell” as taught by Kim. One of ordinary skill in the art would be motivated to combine Bang with Kim before the effective filing date of the claimed invention to improve a system through “changing a recovery read level to be applied to a selected word line or changing a develop time of the sensing node on the basis of a programming status of pieces of data of at least one of word lines adjacent to the selected word line and an operating parameter of the non-volatile memory device, thereby achieving a performance improvement.” [Kim, para. 0069].
However, Bang and Kim do not explicitly disclose wherein the value sense at the first sensing time and the values sensed at the second sensing time are stored in different latches.
Son teaches wherein the value sense at the first sensing time and the values sensed at the second sensing time are stored in different latches [“The first to third latch signals LS1, LS2, and LS3 may be respectively provided to the first to third latches 131, 132, and 133 at different points in time. For example, the first latch signal LS1 may be provided to the first latch 131 at a first point in time such that the first latch 131 latches a voltage level of the sensing node SO at the first point in time. The second latch signal LS2 may be provided to the second latch 132 at a second point in time such that the second latch 132 latches a voltage level of the sensing node SO at the second point in time. The third latch signal LS3 may be provided to the third latch 133 at a third point in time such that the third latch 133 latches a voltage level of the sensing node SO at the third point in time. The first to third points in time may be different from each other. For example, the first point in time may occur before the second point in time and the second point in time may occur before the third point in time.”] [para. 0137].
Bang, Kim, and Son are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Bang and Kim with Son in order to modify Bang and Kim for “outputting on the basis of a sensing value of the memory cell adjacent to the target memory cell” as taught by Son. One of ordinary skill in the art would be motivated to combine Bang and Kim with Son before the effective filing date of the claimed invention to improve a system where a “non-volatile memory device … may secure a maximum read window through the initial program operation, and thus the performance of read may be improved.” [Son, para. 0113].
As per claim 2, Bang in view of Kim and further in view of Son discloses the method of claim 1, Bang discloses wherein the first sensing and the second sensing of the target memory cell occur at different times [“…the nonvolatile memory device 100 may latch data stored in the selected memory cells at least two times at main sensing latches of the page buffers PB0 to PBn−1.”] [para. 0084] [“Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.”] [Abstract] [paras. 0006 and 0008] [“…sensed by using different read voltages at different times…”] [para. 0082] [para. 0085].
As per claim 3, Bang in view of Kim and further in view of Son discloses the method of claim 2, Bang discloses wherein the first sensing time is different from the second sensing time in an amount of time elapsed from precharging the sensing node [“Only sensing nodes corresponding to the first bit lines may be precharged in the time interval Ti1, and only sensing nodes corresponding to the second bit lines may be precharged in the time interval Ti2.”] [para. 0112].
As per claim 4, Bang in view of Kim and further in view of Son discloses the method of claim 2, Bang discloses wherein the sensing node is electrically connected to a bit line during a read operation [“…in the case where a sensing node corresponds to a first bit line connected to a memory cell having a threshold voltage close to the read voltage VRD1,…”] [para. 0102], and a plurality of latches are sequentially connected to the sensing node [“For example, each of the main sensing latches (e.g., 350) of the page buffers PB0 to PBn−1 may sense data stored in the corresponding selected memory cell based on a change in a voltage level of the corresponding sensing node and may store a logical value corresponding to the sensed data as a main sensing result. Below, the main sensing result may be expressed by “S”, In operation S215, the nonvolatile memory device 100 may dump data stored in the adjacent sensing latches.”] [paras. 0117 – 0116].
As per claim 5, Bang in view of Kim and further in view of Son discloses the method of claim 1, Bang discloses wherein the memory cell adjacent to the target memory cell and the target memory cell are electrically connected to a same bit line but are electrically connected to different word lines [“According to some embodiments, a nonvolatile memory device may include a memory cell array that includes memory cells arranged in rows and columns, a row decoder circuit that is connected to the rows of the memory cells through word lines, the row decoder circuit selects a first word line of the word lines connected to adjacent memory cells adjacent to selected memory cells and a second word line of the word lines connected to the selected memory cells, and a page buffer circuit that is connected to the columns of the memory cells through bit lines and including first latches and second latches. The page buffer circuit may respectively latch first sensing values, which are based on data stored in the adjacent memory cells, at the first latches and may respectively latch second sensing values, which are based on data stored in the selected memory cells, at the second latches at least two times.”] [para. 0006] [Fig. 2].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. [hereafter as Bang], US Pub. No. 2022/0051714 A1 in view of Kim et al. [hereafter as Kim], US Pub. No. 2023/0123963 A1 and further in view of Son et al. [hereafter as Son], US Pub. No. 2023/0251781 A1 as applied to claim 1 above, and further in view of Park et al. [hereafter as Park], US Patent No. 6,804,150 B2.
As per claim 6, Bang in view of Kim and further in view of Son discloses the method of claim 1, however Bang, Kim, and Son do not explicitly disclose wherein, when a plurality of word lines are sequentially driven and programmed, the memory cell adjacent to the target memory cell is programmed immediately after the target memory cell is programmed.
Park teaches wherein, when a plurality of word lines are sequentially driven and programmed, the memory cell adjacent to the target memory cell is programmed immediately after the target memory cell is programmed [“a control electrode of the second select transistor are connected to the first select line, the word lines, and the second select line, respectively, a select line driver for sequentially supplying a first select voltage and a second select voltage, lower than the first select voltage, to the first select line during a program operation of the memory cell”] [claim 9].
Bang, Kim, Son, and Park are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Bang, Kim, and Son with Park in order to modify Bang, Kim, and Son “wherein, when a plurality of word lines are sequentially driven and programmed, the memory cell adjacent to the target memory cell is programmed immediately after the target memory cell is programmed” as taught by Park. One of ordinary skill in the art would be motivated to combine Bang, Kim, and Son with Park before the effective filing date of the claimed invention to improve a system “to alleviate … program interference … the program inhibition characteristic of unselected memory cell transistors may be improved, and the possibility of program failure may be reduced.” [Park, col. 10, lines 47-52].
Conclusion
STATUS OF CLAIMS IN THE APPLICATION
CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1 – 13 have received a second action on the merits and are subject of a second action final. Claim 1 – 6 are rejected under a 103 rejection. Claims 7 – 13 are allowed.
CLAIMS ALLOWED IN THE APPLICATION
Per the instant office action, claims 7 – 13 are considered allowed.
The following is a statement of reasons for the indication of allowable subject matter: for
independent claim 7 the prior art of record, neither anticipates, nor renders obvious
a page buffer outputting a second or third sensed value that is stored in a respective second or third latch as data on the basis of a first sensed value that is stored in a first latch. The prior art of record (Son) teaches a second or third sensed value in a second or third latch, however it does not teach a page buffer outputting the second or third sensed value from the second or third latch as data on the basis of the first sensed value stored in the first latch. Claims 8 – 10 depend from claim 7 and would be allowable.
The following is a statement of reasons for the indication of allowable subject matter: for
independent claim 11 the prior art of record, neither anticipates, nor renders obvious
a page buffer that has a third latch that senses a third voltage value of a sensing node that is formed by a second word line, where the third voltage is sensed at a different time from when the second voltage value is sensed. The prior art of record (Son) teaches sensing voltage values at different time, however it does not teach a third latch that senses a third voltage value of a sensing node that is formed by a second word line. Claims 12 and 13 depend from claim 11 and would be allowable.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/EW/Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135
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