Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received on 25 November 2024 for application number 18/958,602. The Office hereby acknowledges receipt of the following and placed of record in file: Oath/Declaration, Abstract, Specification, Drawings, and Claims.
Claims 1 – 13 are presented for examination.
Priority
As required by M.P.E.P. 201.14(c), acknowledgement is made of applicant’s claim for priority based on the application filed on 05 August 2024 (KR10-2024-0103585).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 25 November 2024 was filed on the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 5 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. [hereafter as Bang], US Pub. No. 2022/0051714 A1 in view of Kim et al. [hereafter as Kim], US Pub. No. 2023/0123963 A1.
As per claim 1, Bang discloses an operating method of a semiconductor device, the method comprising:
receiving a read command [“The control logic circuit 150 may receive a command CMD from the external device (e.g., a memory controller 10 of FIG. 17)...”] [para. 0040] [“read operation of the nonvolatile memory device 100”] [para. 0041];
sensing a memory cell adjacent to a target memory cell of the read command [“Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.”] [Abstract] [paras. 0006 and 0008];
sensing the target [selected] memory cell at a first sensing time [“Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.”] [Abstract] [paras. 0006 and 0008] [“…sensed by using different read voltages at different times…”] [para. 0082] [para. 0085];
sensing the target memory cell at a second sensing time [“…the nonvolatile memory device 100 may latch data stored in the selected memory cells at least two times at main sensing latches of the page buffers PB0 to PBn−1.”] [para. 0084] [“Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.”] [Abstract] [paras. 0006 and 0008] [“…sensed by using different read voltages at different times…”] [para. 0082] [para. 0085]; and
outputting, as data, a value sensed at the first sensing time or a value sensed at the second sensing time [“The data block 370 may be connected to the sensing node SO. The data block 370 may receive data stored in the main sensing latch 350 and the adjacent sensing latch 360 through the sensing node SO. In an embodiment, the data block 370 may be implemented with a latch capable of storing data input thereto. The data block 370 may transmit the input data to the data input/output circuit 140 in response to a latch data output signal SLD.”] [para. 0065].
However, Bang does not explicitly disclose outputting on the basis of a sensing value of the memory cell adjacent to the target memory cell.
Kim teaches outputting on the basis of a sensing value of the memory cell adjacent to the target memory cell [“Pieces of data are read from memory cells experiencing word line coupling from an adjacent word line by changing a recovery read level to be applied to a selected word line or changing a develop time of the sensing node on the basis of a programming status of pieces of data of at least one of word lines adjacent to the selected word line and an operating parameter of the non-volatile memory device, thereby achieving a performance improvement.”] [para. 0069].
Bang and Kim are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Bang with Kim in order to modify Bang for “outputting on the basis of a sensing value of the memory cell adjacent to the target memory cell” as taught by Kim. One of ordinary skill in the art would be motivated to combine Bang with Kim before the effective filing date of the claimed invention to improve a system through “changing a recovery read level to be applied to a selected word line or changing a develop time of the sensing node on the basis of a programming status of pieces of data of at least one of word lines adjacent to the selected word line and an operating parameter of the non-volatile memory device, thereby achieving a performance improvement.” [Kim, para. 0069].
As per claim 2, Bang in view of Kim discloses the operating method of a semiconductor device of claim 1, Bang discloses wherein the first sensing and the second sensing of the target memory cell occur at different times [“…the nonvolatile memory device 100 may latch data stored in the selected memory cells at least two times at main sensing latches of the page buffers PB0 to PBn−1.”] [para. 0084] [“Disclosed are a nonvolatile memory device and a read method of the nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a row decoder circuit, and a page buffer circuit including first latches and second latches. The page buffer circuit respectively latches first sensing values, which are based on data stored in adjacent memory cells, at the first latches and respectively latches second sensing values, which are based on data stored in selected memory cells, at the second latches at least two times.”] [Abstract] [paras. 0006 and 0008] [“…sensed by using different read voltages at different times…”] [para. 0082] [para. 0085].
As per claim 3, Bang in view of Kim discloses the operating method of a semiconductor device of claim 2, Bang discloses wherein the first sensing time is different from the second sensing time in an amount of time elapsed from precharging the sensing node [“Only sensing nodes corresponding to the first bit lines may be precharged in the time interval Ti1, and only sensing nodes corresponding to the second bit lines may be precharged in the time interval Ti2.”] [para. 0112].
As per claim 4, Bang in view of Kim discloses the operating method of a semiconductor device of claim 2, Bang discloses wherein the sensing node is electrically connected to a bit line during a read operation [“…in the case where a sensing node corresponds to a first bit line connected to a memory cell having a threshold voltage close to the read voltage VRD1,…”] [para. 0102], and a plurality of latches are sequentially connected to the sensing node [“For example, each of the main sensing latches (e.g., 350) of the page buffers PB0 to PBn−1 may sense data stored in the corresponding selected memory cell based on a change in a voltage level of the corresponding sensing node and may store a logical value corresponding to the sensed data as a main sensing result. Below, the main sensing result may be expressed by “S”, In operation S215, the nonvolatile memory device 100 may dump data stored in the adjacent sensing latches.”] [paras. 0117 – 0116].
As per claim 5, Bang in view of Kim discloses the operating method of a semiconductor device of claim 1, Bang discloses wherein the memory cell adjacent to the target memory cell and the target memory cell are electrically connected to a same bit line but are electrically connected to different word lines [“According to some embodiments, a nonvolatile memory device may include a memory cell array that includes memory cells arranged in rows and columns, a row decoder circuit that is connected to the rows of the memory cells through word lines, the row decoder circuit selects a first word line of the word lines connected to adjacent memory cells adjacent to selected memory cells and a second word line of the word lines connected to the selected memory cells, and a page buffer circuit that is connected to the columns of the memory cells through bit lines and including first latches and second latches. The page buffer circuit may respectively latch first sensing values, which are based on data stored in the adjacent memory cells, at the first latches and may respectively latch second sensing values, which are based on data stored in the selected memory cells, at the second latches at least two times.”] [para. 0006] [Fig. 2].
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. [hereafter as Bang], US Pub. No. 2022/0051714 A1 in view of Kim et al. [hereafter as Kim], US Pub. No. 2023/0123963 A1 as applied to claim 1, and further in view of Park et al. [hereafter as Park], US Patent No. 6,804,150 B2.
As per claim 6, Bang in view of Kim discloses the operating method of a semiconductor device of claim 1, however Bang and Kim do not explicitly disclose wherein, when a plurality of word lines are sequentially driven and programmed, the memory cell adjacent to the target memory cell is programmed immediately after the target memory cell is programmed.
Park teaches wherein, when a plurality of word lines are sequentially driven and programmed, the memory cell adjacent to the target memory cell is programmed immediately after the target memory cell is programmed [“a control electrode of the second select transistor are connected to the first select line, the word lines, and the second select line, respectively, a select line driver for sequentially supplying a first select voltage and a second select voltage, lower than the first select voltage, to the first select line during a program operation of the memory cell”] [claim 9].
Bang, Kim, and Park are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Bang and Kim with Park in order to modify Bang and Kim “wherein, when a plurality of word lines are sequentially driven and programmed, the memory cell adjacent to the target memory cell is programmed immediately after the target memory cell is programmed” as taught by Park. One of ordinary skill in the art would be motivated to combine Bang and Kim with Park before the effective filing date of the claimed invention to improve a system “to alleviate … program interference … the program inhibition characteristic of unselected memory cell transistors may be improved, and the possibility of program failure may be reduced.” [Park, col. 10, lines 47-52].
Claims 7, 8, and 10 – 13 are rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. [hereafter as Bang], US Pub. No. 2022/0051714 A1 in view of Kim et al. [hereafter as Kim], US Pub. No. 2023/0123963 A1 and further in view of Takada et al. [hereafter as Takada], US Pub. No. 2017/0186484 A1.
As per claim 7, Bang discloses an operating method of a page buffer, the method comprising:
connecting a sensing node of the page buffer to a bit line during a read operation [“Referring to FIGS. 1 and 3, the page buffer PBr includes a bit line selection block 310, a bit line precharge block 320, a transistor MPASS, a sensing node precharge block 330, a latch block 340, a main sensing latch 350, an adjacent sensing latch 360, and a data block 370. The bit line selection block 310 may be connected between a bit line BLr corresponding to the page buffer PBr and a node N1. The bit line selection block 310 may receive a bit line selection signal BLSLT from the control logic circuit 150. In response to the bit line selection signal BLSLT, the bit line selection block 310 may electrically connect the bit line BLr and the node N1 or may electrically disconnect the bit line BLr from the node N1.”] [paras. 0046 – 0047] [“A read operation of the nonvolatile memory device 100 will be described with reference to FIGS. 1 to 3, 5A, 5B, 6, 7A, and 7B.”] [para. 0079];
sensing the sensing node by driving a first word line and storing a first sensed value in a first latch [“The page buffer circuit 130 may include a plurality of page buffers PB0 to PBn−1 (n being a natural number) respectively connected to the plurality of bit lines BL0 to BLn−1. Each of the plurality of page buffers PB0 to PBn−1 may apply a voltage to the corresponding bit line (or a bit line connected thereto). The plurality of page buffers PB0 to PBn−1 may sense data stored in memory cells connected to the corresponding bit lines BL0 to BLn−1 and may store the sensed data.”] [para. 0044] [“…The main sensing latch 350 may latch data stored in a selected memory cell, based on a change in a voltage level of the sensing node SO...”] [para. 0054] [para. 0184];
sensing the sensing node at a first time by driving a second word line and storing a second sensed value in a second latch [“In operation S100, the nonvolatile memory device 100 may read the adjacent memory cells connected to the adjacent word line WLk−1. For example, the row decoder circuit 120 of the nonvolatile memory device 100 may select (or activate) the adjacent word line WLk−1. The page buffer circuit 130 of the nonvolatile memory device 100 may sense data stored in the adjacent memory cells and may latch the sensed data at adjacent sensing latches, respectively.”] [para. 0104] [“The data block 370 may be connected to the sensing node SO. The data block 370 may receive data stored in the main sensing latch 350 and the adjacent sensing latch 360 through the sensing node SO. …”] [para. 0065] [para. 0184];
outputting the second sensed value stored in the second latch or the third sensed value stored in the third latch as data [“The data block 370 may be connected to the sensing node SO. The data block 370 may receive data stored in the main sensing latch 350 and the adjacent sensing latch 360 through the sensing node SO. In an embodiment, the data block 370 may be implemented with a latch capable of storing data input thereto. The data block 370 may transmit the input data to the data input/output circuit 140 in response to a latch data output signal SLD.”] [para. 0065] [“first latches and second latches, wherein the page buffer circuit is configured to: respectively latch first sensing values, which are based on data stored in the adjacent memory cells, at the first latches, and respectively latch second sensing values, which are based on data stored in the selected memory cells, at the second latches”] [claim 1].
However, Bang does not explicitly disclose sensing the sensing node at a second time after the storing of the sensed value in the first latch and storing a third sensed value in a third latch; and
outputting on the basis of the first sensed value stored in the first latch.
Kim teaches sensing the sensing node at a second time after the storing of the sensed value in the first latch and storing a third sensed value in a third latch [“…data recovery read scheduler 155 may store, in a first latch, information of one of a plurality of aggressor groups connected to the adjacent word line, store, in a second latch, data obtained by updating information of aggressor groups sensed up to a current point in time, store, in a third latch,…”] [para. 0042] [para. 0064].
Bang and Kim are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Bang with Kim in order to modify Bang for “sensing the sensing node at a second time after the storing of the sensed value in the first latch and storing a third sensed value in a third latch” as taught by Kim. One of ordinary skill in the art would be motivated to combine Bang with Kim before the effective filing date of the claimed invention to improve a system through “changing a recovery read level to be applied to a selected word line or changing a develop time of the sensing node on the basis of a programming status of pieces of data of at least one of word lines adjacent to the selected word line and an operating parameter of the non-volatile memory device, thereby achieving a performance improvement.” [Kim, para. 0069].
However, Bang and Kim do not explicitly disclose outputting on the basis of the first sensed value stored in the first latch.
Takada teaches outputting on the basis of the first sensed value stored in the first latch [“read circuit stores the first sensed value in the first latch circuit, …, outputs the first sensed value stored in the first latch circuit”] [claim 3] [“calculates the first sensed value and the second sensed value on the basis of the third sensed value stored in the first latch circuit and the data value stored in the second latch circuit, and outputs the calculated first sensed value and the calculated second sensed value.”] [claim 6].
Bang, Kim, and Takada are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Bang and Kim with Takada in order to modify Bang and Kim for “outputting on the basis of the first sensed value stored in the first latch” as taught by Takada. One of ordinary skill in the art would be motivated to combine Bang and Kim with Takada before the effective filing date of the claimed invention to improve a system where “the controller … can use the separated data acquired by the estimation process to generate the soft bit information, a calculation cost required for reading for acquiring the soft bit information can be reduced and high correction capability can be achieved.” [Takada, para. 0245].
As per claim 8, Bang in view of Kim and further in view of Takada disclose the operating method of a page buffer of claim 7, Bang discloses latches are each used to sense a voltage value of the sensing node [“The latch block 340 is connected to the sensing node SO and is connected to the main sensing latch 350 and the adjacent sensing latch 360. The latch block 340 may receive a latch signal SLAT from the control logic circuit 150. The latch block 340 may transfer a voltage level of the sensing node SO to the main sensing latch 350 and the adjacent sensing latch 360 in response to the latch signal SLAT. The latch block 340 may compare a voltage level of the sensing node SO with a reference voltage in response to the latch signal SLAT.”] [para. 0052].
Kim teaches wherein the first, second, and third latches are each used [“store, in a first latch, information of one of a plurality of aggressor groups connected to the adjacent word line, store, in a second latch, data obtained by updating information of aggressor groups sensed up to a current point in time, store, in a third latch”] [para. 0042] [“Referring to FIG. 6, information of three groups connected to an adjacent word line WLn-1 may be latched. A sensing operation for each of read levels VR_G1 and VR_G2 of two aggressor groups is performed, and sensed data may be stored in corresponding first latches. A read pass voltage VREAD may be applied to a selected word line. Thereafter, sensing operations using a read level VR in response to a sensing activation signal SEN may be consecutively performed on a memory cell connected to the selected word line in a state in which the read pass voltage VREAD is applied to the adjacent word line. Results of such sensing operations may be stored in second latches.”] [paras. 0071 – 0072].
.
As per claim 10, Bang in view of Kim and further in view of Takada disclose the operating method of a page buffer of claim 7, Bang discloses wherein the first time occurs before the second time [“In operation S200, the nonvolatile memory device 100 may read the selected memory cells connected to the selected word line WLk. For example, the nonvolatile memory device 100 may perform operation S200 based on a result of operation S100. Operation S200 will be more fully described later.”] [para. 0105] [Fig. 9].
Claim 11 is rejected with like reasoning as claims 1 and 7 above, except for the following remaining claim limitations:
a third latch that senses a third voltage value of the sensing node formed by the second word line, wherein the third voltage value is sensed at a different time from when the second voltage value is sensed.
Kim teaches a third latch that senses a voltage value formed by the second word line [“data of a memory cell connected to a selected word line may be read using a read level VR_3 for the third aggressor group, and the read data may be stored in the third latch S.”] [para. 0094], wherein the third voltage value is sensed at a different time from when the second voltage value is sensed [“sensing operations corresponding to a plurality of develop times at the same level VR. Therefore, a plurality of latch operations for sensing data may be performed.”] [para. 0090].
Claim 12, is rejected with like reasoning as claim 7 above.
As per claim 13, Bang in view of Kim and further in view of Takada disclose the page buffer of claim 11, Kim teaches wherein the third latch senses the third voltage value after the second latch senses the second voltage value [“read level VR_AG2 to obtain information of a second aggressor group, and then a sensing operation may be performed on a memory cell connected to an n-th word line (a selected word line WL) using a read level VR_2 for the second aggressor group.”] [para. 0082] [“performed on a memory cell connected to the selected word line in a state in which the read pass voltage VREAD is applied to the adjacent word line. Results of such sensing operations may be stored in second latches.”] [para. 0072] [“data of a memory cell connected to a selected word line may be read using a read level VR_3 for the third aggressor group, and the read data may be stored in the third latch S.”] [para. 0094].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bang et al. [hereafter as Bang], US Pub. No. 2022/0051714 A1 in view of Kim et al. [hereafter as Kim], US Pub. No. 2023/0123963 A1 and further in view of Takada et al. [hereafter as Takada], US Pub. No. 2017/0186484 A1 as applied to claim 7 above, and further in view of Dong et al. [hereafter as Dong], US Pub. No. 2025/0322878 A1.
As per claim 9, Bang in view of Kim and further in view of Takada disclose the operating method of a page buffer of claim 7, however Bang, Kim, and Takada do not explicitly disclose wherein the first word line is driven after the second word line is driven during a program operation.
Dong teaches wherein the first word line is driven after the second word line is driven during a program operation [“It is noted that, during a forward program scheme or a reverse program scheme, memory cells corresponding to first adjacent word line WLn−1 (e.g., first word line 1181 during the forward program scheme, or second word line 1185 during the reverse program scheme) are programmed before memory cells corresponding to selected word line WLn 1183”] [para. 0070].
Bang, Kim, Takada, and Dong are analogous art aimed to improve memory performance in storage systems.
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine Bang, Kim, and Takada with Dong in order to modify Bang, Kim, and Takada for “wherein the first word line is driven after the second word line is driven during a program operation” as taught by Dong. One of ordinary skill in the art would be motivated to combine Bang, Kim, and Takada with Dong before the effective filing date of the claimed invention to improve a system by “reducing the Esum loss and improving the reliability of the memory device.” [Dong, para. 0064].
Conclusion
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/EW/Examiner, Art Unit 2135 /JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135