CTNF 18/958,603 CTNF 82477 DETAILED ACTION This office action is in response to the application filed on 11/25/2024. Claims 1-20 are pending in the application and have been examined. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-3, 11-13, and 19-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Konigsburg (U.S. Patent 6,279,105) . Regarding claims 1, 11, and 19, Konigsburg discloses a device comprising: branch prediction circuitry comprising: comparison circuitry configured to: perform a first comparison between a first portion of a program counter value and a first portion of a cached address [Fig 4A; col. 5, lines 48-55; a first portion of the instruction address is compared to address values in the BTAC array]; and perform a second comparison between a second portion of the program counter value and a second portion of the cached address [Fig. 4A; col. 5, lines 48-55; a second portion of the instruction address is compared to tags within the BTAC array to determine a hit]; and control circuitry configured to determine whether to replace the program counter value with a target address associated with the cached address based on the first comparison and the second comparison [col. 6, lines 21-48; a hit in the BTAC array is used to determine whether the next fetch occurs at a sequentially incremented address or at an address retrieved from the BTAC]. Regarding claims 2, 12, and 20, Konigsburg discloses the device of claim 1, wherein the control circuitry is further configured to increment the program counter value based on the first comparison determining that the first portion of the program counter value does not match the first portion of the cached address or the second comparison determining that the second portion of the program counter value does not match the second portion of the cached address [col. 6, lines 21-48; when there is not a hit in the BTAC array, the system uses the next sequential address by incrementing the program counter]. Regarding claims 3 and 13, Konigsburg discloses the device of claim 2, wherein the program counter value is stored in a register coupled to the branch prediction circuitry [col. 4, lines 15-18; a register holds the instruction fetch address], wherein the program counter value includes an instruction address, wherein the first portion of the program counter value includes a first section of the instruction address, and wherein the second portion of the program counter value includes a second section of the instruction address [col. 5, lines 48-55; the instruction fetch address contains two portions that are used] . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 4-6, 8, 14-15, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Konigsburg in view of Reid (U.S. Publication 2019/0163902) . Regarding claims 4 and 14, Konigsburg does not disclose storing address portions in different tables, as claimed. However, Reid discloses a branch prediction system similar to that of Konigsburg, and further discloses branch prediction circuitry that includes a first memory and allocation circuitry, wherein the allocation circuitry is configured to cache addresses in the first memory and wherein, to cache the addresses in the first memory, the allocation circuitry is configured to: identify one or more branch instruction addresses, and for each branch instruction address of the one or more branch instruction addresses: identify a first section of the branch instruction address; cache the first section of the branch instruction address within a first table of the first memory, wherein the first section of the branch instruction address includes the first portion of the cached address, and wherein the first table is stored by a first location of the first memory [Fig. 11; paragraph 0149; a first portion of a branch address is stored in a branch target buffer]; identify a second section of the branch instruction address; and cache the second section of the branch instruction address within a second table of the first memory, wherein the second section of the branch instruction address includes the second portion of the cached address, and wherein the second table is stored by a second location of the first memory [Fig. 11; paragraph 0149; a second portion of a branch address is stored in a region table]. As disclosed by Reid [paragraph 0149], such a 2-table system allows for improved efficiency when operating a branch prediction cache such as the one disclosed by Konigsburg, and the use of such a technique would therefore have been obvious in the system of Konigsburg. Regarding claims 5 and 15, Reid in view of Konigsburg discloses the device of claim 4, wherein the first location of the first memory includes a local buffer configured to store the first table, and wherein to perform the first comparison, the comparison circuitry is configured to: identify a first entry of the first table based on a first index of the program counter value, wherein the first entry of the first table stores the first portion of the cached address [Konigsburg, Fig 4A; col. 5, lines 48-55; a first portion of the instruction address is compared to address values in the BTAC array]; and compare the first portion of the program counter value with the first portion of the cached address [Konigsburg, Fig 4A; col. 5, lines 48-55; a first portion of the instruction address is compared to address values in the BTAC array]. Regarding claim 6, Reid in view of Konigsburg discloses the device of claim 5, wherein the second location of the first memory includes a shared buffer configured to store the second table, wherein the comparison circuitry is configured to perform the second comparison when the first comparison determines that the first portion of the program counter value matches the first portion of the cached address, and wherein to perform the second comparison, the comparison circuitry is configured to: identify a first entry of the second table based on an address pointer stored by the first entry of the first table, wherein the first entry of the second table stores the second portion of the cached address [Konigsburg, Fig. 4A; col. 5, lines 48-55; a second portion of the instruction address is compared to tags within the BTAC array to determine a hit]; and compare the second portion of the program counter value with the second portion of the cached address [Konigsburg, Fig. 4A; col. 5, lines 48-55; a second portion of the instruction address is compared to tags within the BTAC array to determine a hit]. Regarding claims 8 and 17, Reid in view of Konigsburg discloses the device of claim 4, wherein the first location of the first memory includes a shared buffer configured to store the first table, and wherein to perform the first comparison, the comparison circuitry is configured to: identify a first entry of the first table based on a first index of the program counter value, wherein the first entry of the first table stores the first portion of the cached address [Konigsburg, Fig 4A; col. 5, lines 48-55; a first portion of the instruction address is compared to address values in the BTAC array]; and compare the first portion of the program counter value with the first portion of the cached address [Konigsburg, Fig 4A; col. 5, lines 48-55; a first portion of the instruction address is compared to address values in the BTAC array] . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 7, 9-10, 16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corey Faherty whose telephone number is (571)270-1319. The examiner can normally be reached weekdays between 7:30 and 4:00 ET, with every other Friday off. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571) 270-3995. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /COREY S FAHERTY/Primary Examiner, Art Unit 2183 Application/Control Number: 18/958,603 Page 2 Art Unit: 2183 Application/Control Number: 18/958,603 Page 3 Art Unit: 2183 Application/Control Number: 18/958,603 Page 4 Art Unit: 2183 Application/Control Number: 18/958,603 Page 5 Art Unit: 2183 Application/Control Number: 18/958,603 Page 6 Art Unit: 2183 Application/Control Number: 18/958,603 Page 7 Art Unit: 2183
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