Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/7/2026 has been entered.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 8/7/2026 and 7/7/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 20, 24-27, 30-33 and 36-39 are rejected under 35 U.S.C. 103 as being unpatentable over Desai (US 2014/0108766) in view of Dwiel et al. (US 2017/0371790) and further in view of Topham et al. (US 2002/0144078).
Regarding claim 20, Desai discloses an apparatus comprising: a plurality of processors, including a graphics processing unit (GPU) [see Fig. 1; CPU 140 & GPU 125]; and a memory for storage of data, including data for processing of pages by the GPU [see paragraph 25 & Fig. 1, GPU cache 130 & system memory 155]; and wherein, upon the GPU accessing a first page in processing of a current application and receiving a page fault indicating that the first page is not present in page translation entries [see paragraph 31; request from processor executing a process thread (particular software application) misses in translation buffer (TLB)], the plurality of processors are to perform page translation including:
identifying a set of sequential pages following the first page [see paragraph 31; virtual address translation for next sequential page identified], and requesting one or more page translations for the one or more sequential pages [see paragraph 31; address lookup request for one or more sequential page is sent and translations are prefetched].
Desai does not expressly disclose probing the set of sequential pages to identify one or more sequential pages that are not present in the page translation entries and are required in the processing of the application and requesting one or more page translations for the identified one or more sequential pages.
Dwiel discloses a memory system that implements prefetching. Upon a miss in a cache, sequential memory addresses are identified, and history is checked in order to determine whether a confidence exceeds a threshold to indicate that the sequential addresses will be needed for execution. When the confidence threshold is reached, prefetching of the sequential addresses is executed [See paragraphs 3-6; This confidence based prefetching is interpreted to be equivalent to the probing performed in the claim. The claim does not offer any insight into what the claimed probing entails, nor does the specification further describe a probing process. Therefore, when the confidence threshold is reached, the sequential addresses is deemed as required for processing the application].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the prefetching teachings of Dwiel in the system of Desai.
The motivation for doing so would have been to reduce cache pollution [see Dwiel, paragraph 6].
The combination of Desai and Dwiel discloses the apparatus of claim 1 as discussed above. Desai explicitly discloses “the TLB logic 220 sends a lookup request for the virtual address translation for the missed page, as well as the virtual address translation for the next sequential page” in paragraph 31.
However, the combination does not expressly disclose that the lookup for the next sequential page would include probing translations for the set of sequential pages and, upon receiving a not valid response for a sequential page, identifying the sequential page as being not present in the page translation entries.
Topham discloses an address translation system in which, upon a lookup for a translation, a valid bit is checked in the lookup table to determine if the translation is valid. If it is not valid, the miss handler loads the valid translation into the lookup table [see paragraph 84].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the validity check of Topham in the system of Desai and Dwiel.
The motivation for doing so would have been to ensure the virtual address is properly translated to a physical address using a valid translation [see Topham, paragraph 84].
Therefore, it would have been obvious to combine Dwiel and Topham with Desai for the benefits listed above, to obtain the invention as specified in claims 20, 24-27, 30-33 and 36-39.
Regarding claim 24, the combination discloses the apparatus of claim 20, wherein the page translation entries indicate translation of pages into virtual address space [see Desai, paragraph 30; TLB stores set of virtual to physical address translations].
Regarding claim 25, the combination discloses the apparatus of claim 20, wherein identifying one or more sequential pages that are required in the processing of the current
application includes obtaining a confirmation from software that the one or more sequential
pages are required [see Dwiel, paragraphs 5-6; wherein software determining a confidence threshold has been exceeded is interpreted as confirming the pages are required].
Regarding claim 26, the combination discloses the apparatus of claim 20, wherein requesting the one or more page translations includes requesting the one or more translations prior to needing the one or more sequential pages in processing of the current application [see Desai, paragraph 31; sequential address is fetched speculatively based on locality of references pattern].
Regarding claim 29, the combination discloses the apparatus of claim 20, wherein the one or more processors include a page probing engine including a page walker, and wherein probing the set of sequential pages includes the page walker to probe the translations for the set of sequential pages [see Desai, paragraph 30; a table walk unit 230 to retrieve the requested virtual address translation. As known to those of ordinary skill in the art, the table walk unit 230 accesses one or more translation tables 157 that are typically stored in the system memory 155 to identify the virtual-to-physical address translation].
Claims 27, 30-34 and 36-38 recite the same limitations as claims 20 and 24-26 and are rejected using the same citations and interpretations.
Claims 23, 29 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Desai in view of Dwiel and Topham, and further in view of Lee et al. (US 2008/0276066).
Regarding claim 23, the combination of Desai and Dwiel and Topham discloses the method of claim 20 as discussed above, including prefetching a plurality of pages discloses [see paragraph 32].
The combination does not expressly disclose requesting translation of multiple pages in parallel.
Lee discloses a virtual memory translation system in which a plurality of virtual address translation pre-fetches may be performed at the same time (parallel) [see paragraphs 26 & 32].
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to utilize the parallel pre-fetches of Lee in the system of Desai and Dwiel.
The motivation for doing so would have been that one of ordinary skill in the art would have recognized that the results of the combination were predictable (operations performed in parallel occur faster than those performed serially) [see MPEP 2143].
Therefore, it would have been obvious to combine Lee with Desai and Dwiel and Topham for the benefits listed above, to obtain the invention as specified in claims 23, 29 and 35.
Claims 29 and 35 recite the same limitations as claim 23 and are rejected using the same citations and interpretations.
Response to Arguments
Applicant’s arguments, filed 8/7/2026, with respect to the rejection(s) of claim(s) 20-22, 24, 26-28, 30, 32-34, 36 and 38 under Desai have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Topham.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN BERTRAM whose telephone number is (571)270-1377. The examiner can normally be reached M-F 8:30-5MNT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached at 571-272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RYAN BERTRAM/Primary Examiner, Art Unit 2137
