DETAILED ACTION
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-9 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakagawa (JP 2014-72466).
Regarding claim 1, Nakagawa discloses a printed wiring board (Fig. 2) comprising:
a first layer (layers forming top 8+5, Fig. 2) including a plurality of stacked conductor layers (5 and top 8 are conductor layers);
a second layer (bottom 8, Fig. 2) on which the first layer is stacked;
a plurality of first vias (4as and vias connecting 6 in Fig. 2) formed in the first layer;
a plurality of first pads (plurality of 6, Fig. 2) formed corresponding to the plurality of conductor layers in the first layer and connected to the first vias, respectively;
a plurality of ground patterns (8 can be used for ground or power supply) formed in the plurality of conductor layers and each having an opening (13b, 7b, 7a, Fig. 2) surrounding the first pad;
a second via (9S, Fig. 2) formed in the second layer, wherein the second via is a through-via that penetrates the second layer and is formed of a conductor (9S is a conductor that penetrates bottom 8 as shown in Fig. 2); and
a second pad (11s and/or pads above it in Fig. 2) formed on a surface of the second layer on a side (bottom side of top 8+5 in Fig. 2) of the first layer and connected to the first via and the second via (connected as shown in Fig. 2),
wherein the plurality of first pads and the second pad overlap in a plan view viewed in a direction in which the first layer and the second layer are stacked (overlap as shown in Fig. 2),
wherein the diameters of a plurality of the openings in the plurality of ground patterns are larger than the diameter of the second pad (openings 13b, 7b, 7a are greater than the pads below in bottom 8 as shown in Fig. 2), and
wherein the diameter of the opening farthest from the second layer is smaller than the diameter of the opening closest to the second layer (opening 13b is smaller than opening 7a as shown in Fig. 2).
Regarding claim 2, Nakagawa discloses the printed wiring board according to claim 1, and Nakagawa further discloses wherein of the plurality of openings, the opening farthest from the second layer has the smallest diameter (13b has smallest diameter, note there are two diameters types in Fig. 2).
Regarding claim 3, Nakagawa discloses the printed wiring board according to claim 1, and Nakagawa further discloses wherein the diameters of the plurality of openings are smaller the farther the openings are from the second layer (as shown in Fig. 2).
Regarding claim 4, Nakagawa discloses the printed wiring board according to claim 1, and Nakagawa further discloses wherein the diameters of at least two of the plurality of openings are equal to each other (13b and 7b are equal as shown in Fig. 2).
Regarding claim 5, Nakagawa discloses the printed wiring board according to claim 1, and Nakagawa further discloses wherein a diameter of the first pad is smaller than a diameter of the second pad (6 is smaller than 11s as shown in Fig. 2).
Regarding claim 7, Nakagawa discloses the printed wiring board according to claim 1, and Nakagawa further discloses wherein the second via is a via that penetrates the second layer (as shown in Fig. 2).
Regarding claim 8, Nakagawa discloses the printed wiring board according to claim 1, and Nakagawa further discloses a first wiring (12, Fig. 2) connected to the first pad surrounded by the opening farthest from the second layer.
Regarding claim 9, Nakagawa discloses the printed wiring board according to claim 1, and Nakagawa further discloses wherein the opening farthest from the second layer is formed in the ground pattern located at an outermost layer of the first layer (13 can be ground potential).
Regarding claim 12, Nakagawa discloses the printed wiring board according to claim 1, and Nakagawa further discloses a third pad (11s, Fig. 2) formed on a side of the second layer opposite to the first layer and connected to the second via; and
a second wiring (external connection pad 11 is connected to a wiring conductor of an external electric circuit board via a solder ball B2) connected to the third pad.
Regarding claim 13, Nakagawa discloses an electronic module (Fig. 1) comprising:
the printed wiring board (top 8+5+bottom 8, Figs. 1, 2) according to claim 1; and
a component (S, Fig. 1) mounted on the printed wiring board.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa, and further in view of Toda (WO2022/044856; can also refer to US 2023/0207593 for English version).
Regarding claim 6, Nakagawa teaches the printed wiring board according to claim 1. Nakagawa does not teach wherein a diameter of the first via is smaller than a diameter of the second via. However, Toda teaches a diameter of a first via (301, Fig. 7) is smaller than a diameter of a second via (300, Fig. 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have a diameter of the first via is smaller than a diameter of the second via in Nakagawa, as taught by Toda, in order to improve reliability and prevent cracking.
Regarding claim 14, Nakagawa teaches the printed wiring board according to claim 13. Nakagawa does not teach an electronic equipment comprising: a housing; and the electronic module according to claim 13 arranged inside the housing. However, Toda teaches an electronic equipment (Fig. 1) comprising: a housing (housing of 3, Fig. 1); and an electronic module (10, Figs. 1, 2) arrange inside the housing. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have an electronic equipment comprising: a housing; and the electronic module according to claim 13 arranged inside the housing in Nakagawa, as taught by Toda, in order to utilize the electronic module of Nakagawa in a functional consumer electronic equipment.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Nakagawa, and further in view of Examiner’s Official Notice (EON).
Regarding claim 15, Nakagawa teaches the printed wiring board according to claim 1. Nakagawa does not teach a video displaying apparatus comprising: a housing; a display unit that is arranged inside the housing and displays a video; the printed wiring board according to claim 1 arranged inside the housing; and a semiconductor device that is mounted on the printed wiring board and controls the display unit. However the Examiner hereby takes Official Notice of the conventionality of a video displaying apparatus comprising: a housing; a display unit that is arranged inside the housing and displays a video; the printed wiring board according to claim 1 arranged inside the housing; and a semiconductor device that is mounted on the printed wiring board and controls the display unit. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of EON with that of Nakagawa since doing so would, predictably, utilize the printed wiring board of Nakagawa in a functional consumer electronic equipment, such as a video display apparatus.
Allowable Subject Matter
Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re claims 10-11, prior arts do not teach or suggest the combination of the printed wiring board according to claim 10, in particular, wherein the second layer is a core layer, wherein the first layer includes a plurality of first insulating layers, each disposed between adjacent ones of the plurality of stacked conductor layers, and wherein the second layer includes at least one second insulating layer having a thickness greater than a thickness of each of the plurality of first insulating layers.
Response to Arguments
Applicant's arguments with respect to claims 1-9 and 12-15 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES WU whose telephone number is (571)270-7974. The examiner can normally be reached Monday - Friday, 9:00AM - 5:00PM.
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/JAMES WU/Primary Examiner, Art Unit 2841
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