DETAILED ACTION
Response to Amendment
This action is responsive to the Applicant's amendments filed on 06/18/26. Claims 1-20 remain pending in the application. Claims 1, 10, and 15 have been amended. Any examiner's note, objection, and rejection not repeated is withdrawn due to Applicant's amendment.
Response to Arguments
Applicant's arguments filed 06/18/26 have been fully considered but are not persuasive and the previous rejection under 103(a) and Double patenting rejection are maintained and further upon further consideration of the amended claims, a new ground(s) of rejection is made under 35 U.S.C. 112(a). The arguments related to the prior art are moot at this time.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL. The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), first paragraph:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1, 10, and 15 recites, “indicate, to the host device, an error in restoring the previously stored data, wherein the host device is configured to read the error,”
Nowhere in the specification does the applicant teach, “indicate, to the host device, an error in restoring the previously stored data, wherein the host device is configured to read the error”. The specification [0010] only teaches “The present subject matter provides memory modules and methods that can extend chip kill functionality such that the host system can identify failed non-volatile memory devices, restore corrupted data resulting from the non-volatile memory device failure, and in certain examples, continue to operate the system until the non-volatile memory device can be replaced”. Therefore, the claims introduce new matters not previously introduced. To satisfy the written description requirement, a patent specification must describe the claimed invention in sufficient detail that one skilled in the art can reasonably conclude that the inventor had possession of the claimed invention. See, e.g., Moba, B.V. v. Diamond Automation, Inc., 325 F.3d 1306, 1319, 66 USPQ2d 1429, 1438 (Fed.Cir. 2003); Vas-Cath, hw. v. Mahurkc,, 935 F.2d at 1563, 19 USPQ2d at 1116.
Double Patenting
The non-statutory double patenting rejection is based on a judicially created
doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the
unjustified or improper timewise extension of the "right to exclude" granted by a patent
and to prevent possible harassment by multiple assignees. A non-statutory obviousness-
type double patenting rejection is appropriate where the conflicting claims are not
identical, but at least one examined application claim is not patentably distinct from the
reference claim(s) because the examined application claim is either anticipated by, or
would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d
1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d
2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re
Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164
USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA
1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or
1.321(d) may be used to overcome an actual or provisional rejection based on a non -
statutory double patenting ground provided the conflicting application or patent either is
shown to be commonly owned with this application, or claims an invention made as a
result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a
terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with
37 CFR 3.73(b).
Claims 1-20 are rejected on the ground of non-statutory obviousness-type double
patenting as being unpatentable over claims 1-15 of U.S. Patent No. 10,162,569.
For example, claim 1 of the present application teaches "An apparatus,
comprising: volatile memory; non-volatile memory coupled to the volatile memory; and a
controller configured to: receive, from a host device, a control signal having a first state;
in response to the first state, restore previously-stored data from the non-volatile memory
to the volatile memory; indicate, to the host device, an error in restoring the previously-
stored data; and operate the volatile memory in response to a request based on the error
from the host device". Whereas claim 1 of Patent No. 10,162,569 teaches "An apparatus, comprising: a dynamic random access memory (DRAM); L non-volatile memory (NVM) coupled to the DRAM; L register that provides functionality to identify chip failure of the NVM associated with restoring data from the NVM to the DRAM following a loss of system power to the apparatus; L backup power source configured to provide power to the apparatus during a loss of system power to the apparatus to allow data transfer from the DRAM to the NVM; and controller configured to: receive from a host device, a first command that is based at least in part on a loss of system power to the apparatus: transfer data from the DRAM to the NVM based at least in part on receiving the first command from the host device; receive, from the host device, a second command that is based at least in part on the system power to the apparatus being re-established; restore the data from the NVM to the DRAM upon receiving the second command from the host device; identify chip failure of the NVM in the register, the chip failure based at least in part on restoring the data from the NVM to the DRAM; and operate the apparatus based at least in part on the chip failure identified and according to instructions from a host device"
Rationales:
Although the conflicting claims are not identical, they are not patentably distinct
from each other because the instant applicant's claim 1 broadens the scope of claim 1 of
the U.S. Patent No. 10,162,569 by eliminating several imitations "L register that provides
functionality to identify chip failure of the NVM associated with restoring data from the
NVM to the DRAM following a loss of system power to the apparatus; L backup power
source configured to provide power to the apparatus during a loss of system power to the
apparatus to allow data transfer from the DRAM to the NVM". It is obvious the
limitations of claim 1 of U.S. Patent No. 10,162,569 read on the limitations of claim 1 of
the instant application. Further, it has been held that the omission of an element and its
function is an obvious expedient if the remaining elements perform the same functions as
before. See /n re Karlson, 136 USPQ 184(CCPA 1963). Also note Ex parte Rainu, 168
USPQ 375 (BdPat App&int 1970); omission of a reference element whose function is not
needed would be obvious to one skilled in the art.
Claims 10 of the instant application and claim 1 of U.S. Patent No. 10,162,569 are
generally directed to different statutory embodiments of the same invention. That is,
claim 10 of the instant application is directed to a computer-readable medium while claim
1 of U.S. Patent No. 10,162,569 is directed to an apparatus. Although the conflicting
claims are not identical, they are not patentably distinct from each other because claim 10
of the instant application is the computer-readable medium version of the apparatus
limitations cited in claim 1 of U.S. patent no. 10,162,569. Therefore, the claims are
obvious variations of each other and not patentably distinct.
Claims 15 of the instant application and claim 1 of U.S. Patent No. 10,162,569 are
generally directed to different statutory embodiments of the same invention. That is,
claim 15 of the instant application is directed to a method while claim 1 of U.S. Patent
No. 10,162,569 is directed to an apparatus. Although the conflicting claims are not
identical, they are not patentably distinct from each other because claim 15 of the instant
application is the method version of the apparatus limitations cited in claim 1 of U.S.
patent no. 10,162,569. Therefore, the claims are obvious variations of each other and not
patentably distinct.
"A latter patent claim is not patentably distinct from an earlier patent claim if the latter
claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at
896, 225 USPQ at 651 (affirming a holding of obvious-type double patenting because
the claims at issue were obvious over claims in four prior art patents); In re Berg, 140
F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obvious type
double patenting where a patent application claim to a genus is anticipated by a patent
claim to a species within that genus). ELI LILLY AND COMPANY V BARR
LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON
PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Other parallel dependent claims of the instant application have corresponding issues with
the dependent claims of Patent No. 10,359,970 are also rejected under non-statutory
Obviously-type double patenting.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction
of the statutory basis for the rejection will not be considered a new ground of rejection if
the prior art relied upon, and the rationale supporting the rejection, would be the same
under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102 of this title, if the
differences between the claimed invention and the prior art are such that the claimed
invention as a whole would have been obvious before the effective filing date of the
claimed invention to a person having ordinary skill in the art to which the claimed
invention pertains. Patentability shall not be negated by the manner in which the
invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over
Sweere et al. "herein Sweere" (U.S. PN: 9,390,767) in view of Poojary et al. "herein Poojary" (U.S. PN: 10,942,815).
As per claim 1:
Sweere substantially teaches apparatus, comprising volatile memory; non-volatile
memory coupled to the volatile memory (see figures 28 and 31); and a controller configured to: receive, from a host device (see figures 28 and 31), a control signal having a first state; in response to the first state, restore previous data from the non- volatile memory to the volatile memory (see col. 7, lines 19-30, col. 8, lines 33-56, col. 9, lines 13-67 to col. 10, lines 1-14, and col. 22, lines 12-67 to col.23, lines 1-17). Sweere substantially teaches the claimed invention described in claim 1 (as indicated above).
However, Sweere does not explicitly teach indicating an error in restoring the previously stored data and operate the volatile memory in response to a request based on the error.
Poojary, in an analogous art, teaches indicating an error in restoring the previously stored data and operate the volatile memory in response to a request based on the error (See col. 44, lines 34-49).
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the invention to modify Sweere with the teachings of Poojary by
indicating an error in restoring the previously stored data and operate the volatile memory in response to a request based on the error. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention because one of ordinary skill in the art would have recognized that indicating an error in restoring the previously stored data and operate the volatile memory in response to a request based on the error would have improved the reliability of the memory system.
As per claim 2:
The combination of Sweere and Poojary in the above rejection teach wherein the
error is associated with non-volatile hardware (See col. 44, lines 34-49 in Poojary).
As per claim 3:
The combination of Sweere and Poojary in the above rejection teach wherein the
previously-stored data comprises error correction code (ECC) information (see col. 14,
lines 31-45 in Sweere)
As per claim 4:
The combination of Sweere and Poojary in the above rejection teach wherein the
controller is configured to communicate with the host device via a buffer, and wherein
the controller is disposed on a different die than the host device (see figure 32 element
3210 in Sweere).
As per claim 5:
The combination of Sweere and Poojary in the above rejection teach a plurality of
buffers coupled to the host device, wherein the plurality of buffers comprises the buffer
(see figure 32 element 3210 in Sweere).
As per claim 6:
The combination of Sweere and Poojary in the above rejection teach a flash
memory corresponding to the non-volatile memory (see col. 7, lines 19-48 in Sweere).
As per claim 7:
The combination of Sweere and Poojary in the above rejection teach wherein the
controller is configured to indicate the error in a memory region accessible to the host
device (See col. 44, lines 34-49 in Poojary).
As per claim 8:
The combination of Sweere and Poojary in the above rejection teach wherein the
controller is configured to receive an additional control signal from the host device; and
initiate transfer of data from the volatile memory to the non-volatile memory based on the
additional control signal (see col. 8, lines 26-32 in Sweere).
As per claim 9:
The combination of Sweere and Poojary in the above rejection teach wherein the
additional control signal indicates a power loss (see col. 6, lines 2-13 in Sweere).
As per claims 10, and 15:
These claims are directed to a method and computer readable medium and are
rejected for the same reasons as in claim 1.
As per claim 1 1:
The combination of Sweere and Poojary in the above rejection teach wherein the
first state corresponds to a return of power to the volatile memory (see col. 6, lines 2-13
in Sweere).
As per claim 12:
The combination of Sweere and Poojary in the above rejection teach wherein
indicating the error comprises indicating the error via a buffer accessible to the host
device (see figure 32 element 3210 in Sweere).
As per claim 13:
The combination of Sweere and Poojary in the above rejection teach wherein
restoring the previously-stored data comprises generating one or more memory-based
read signals, one or more memory-based write signals, or both (see col. 8, lines 23-32 in
Sweere).
As per claim 14:
The combination of Sweere and Poojary in the above rejection teach receiving an
additional control signal from the host device; and initiating transfer of data from the
volatile memory to the non-volatile memory based on the additional control signal (see
col. 8, lines 23-55 in Sweere).
As per claim 16:
The combination of Sweere and Poojary in the above rejection teach initiating a
transfer of data from the non-volatile memory to the volatile memory based on the
control signal having the first state (see col. 8, lines 23-55 in Sweere).
As per claim 17:
The combination of Sweere and Poojary in the above rejection teach wherein
indicating the error comprises indicating the error via a buffer accessible to the host
device (see figure 32 element 3210 in Sweere).
As per claim 18:
The combination of Sweere and Poojary in the above rejection teach wherein
restoring the previously-stored data comprises performing memory-based controller read
and write operations relative to flash memory comprising the non-volatile memory (see
col. 7, lines 19-48 in Sweere).
As per claim 19:
The combination of Sweere and Poojary in the above rejection teach receiving an
additional control signal from the host device; and initiating transfer of data from the
volatile memory to the non-volatile memory based on the additional control signal (see
col. 8, lines 23-55 in Sweere).
As per claim 20:
The combination of Sweere and Poojary in the above rejection teach wherein the
additional control signal indicates a power loss (see col. 6, lines 2-13 in Sweere).
Conclusion
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicants are reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for replying to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ESAW T ABRAHAM whose telephone number is (571)272-3812. The examiner can normally be reached on 8AM-4:30PM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner'ssupervisor, Albert DeCady can be reached on (571) 272-3819. The fax phone number for the organization where this application or proceeding is assigned is (703) 872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ESAW T ABRAHAM/Primary Examiner,
Art Unit 2112
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