Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
As required by M.P.E.P. 609 (C), the applicant’s submission of the information Disclosure Statement dated 08/11/2026 is acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. 609 C(2), a copy of the PTOL-1449 initialed and dated by the examiner is attached to the instant office action.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kubota et al. (Pub. No.: US 2003/0217246) in view of YAMAGUCHI et al. (US Pub. 2012/0044942).
Regarding independent claims 1, 8 and 16, Kubota discloses a method, comprising: determining a direction to transfer data from a first memory bank ([0103]: i.e., source memory bank) of a plurality of memory banks ([0103]: i.e, among four memory banks 112 to 115) to a second memory bank ([0103]: i.e., destination memory bank) of the plurality of memory banks ([0103]: i.e, among four memory banks 112 to 115) based on a command associated with bank-to-bank transfer (Fig.10 and [0102]-[0104]: at step S21, the data moving section 27 determines whether or not to move data. That is, whether or not it is time to move data is determined. Specifically, the data moving section 27 may determine that data should be moved at regular time intervals or when data is written to or deleted from the main memory 11. At step S22, the data moving section 27 determines the movement source memory bank from among four memory banks 112 to 115. Following step S22, at step S23, the data moving section 27 determines a movement destination memory bank. The movement destination memory bank is selected from among memory banks in which data are stored (i.e., memory banks which belong in the refresh region. The determination that “data should be moved” triggers the determination of the “movement source memory bank” and the movement destination memory bank”, which correspond to a command associated with bnak-to-bnak transfer, and define a direction to transfer data from the first memory bank to the second memory bank); and
transferring the data from the first memory bank ([0103]: i.e., source memory bank) to the second memory bank ([0103]: i.e., destination memory bank) via a bank-to-bank transfer bus (Fig.1: see shared bus between memory banks 112-115) according to the direction to transfer data from the first memory bank ([0103]: i.e., source memory bank) of the plurality of memory banks ([0103]: i.e, among four memory banks 112 to 115) to the second memory bank ([0103]: i.e., destination memory bank) of the plurality of memory banks ([0103]: i.e, among four memory banks 112 to 115) (Fig.10 and [0105]: At step S25, the data moving section 27 moves storage locations of all data stored in the movement source memory bank to the movement destination memory bank).
For claims 1 and 8, Kubota does not expressly disclose determining a direction to transfer data that minimizes time to transfer data.
However, YAMAGUCHI teaches determining a direction to transfer data that minimizes time to transfer data (Fig.12 and [0106]-[0109]: the low latency route selector collects the delay time of each route and “selects a route having the shortest delay time to the memory”; Fig.13 and [0112]-[0120]: a memory and a transmission route are selected based on evaluation value including the transmission delay time, and the transfer destination is determined based on the evaluation value)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate determining the direction of data transfer based on the transmission delay, as taught by YAMAGUCHI into the memory control of Kubota in order to select a route having the shortest delay time and thereby low latency transmission ([0109] & [0126])
For claim 16, Kubota does not expressly disclose determining a direction to transfer data that minimizes power consumption.
However, YAMAGUCHI further teaches determining a direction to transfer data that minimizes power consumption (Fig.13 and [0109]: the low latency route selector 210 selects a memory accommodating a high level of request for low latency (e.g., high-speed memory) and also selects a route having the shortest delay time to the memory; [0130]:the power consumption of the chip can be suppressed)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate shortest delay route selection, as taught by YAMAGUCHI into the memory control of Kubota in order to reduce transfer time and associated power consumption.
Regarding claim 2, Kubota teaches wherein transferring the data comprises: transferring the data from the bank-to-bank transfer bus to the second memory bank via at least one shared input/output (SIO) line (Fig.1: the line shared among memory banks 112-115 corresponds to the shared input/output (SIO) line).
Regarding claims 3 and 11, Kubota teaches coupling respective memory banks of the plurality of memory banks to the bank-to-bank transfer bus and to logic comprising a plurality of latches via a plurality of shared input/output lines, wherein transferring the data comprises: transferring the data from the plurality of latches to the second memory bank via at least one of the plurality of shared input/output lines (Fig.1 and [0101]-[0107]: the data moving section 27 determines the movement source memory bank from among four memory banks 112 to 115. Following step S22, at step S23, the data moving section 27 determines a movement destination memory bank. The movement destination memory bank is selected from among memory banks in which data are stored (i.e., memory banks which belong in the refresh region. And the data moving section 27 moves storage locations of all data stored in the movement source memory bank to the movement destination memory bank).
Regarding claims 4, 12 and 18, Kubota teaches configuring the bank-to-bank transfer bus to transfer the data from the first memory bank to the second memory bank based on a location of the first memory bank with respect to the bank-to-bank transfer bus and the second memory bank (Fig.1 and [0101]-[0107]: the data moving section 27 determines the movement source memory bank from among four memory banks 112 to 115. Following step S22, at step S23, the data moving section 27 determines a movement destination memory bank. The movement destination memory bank is selected from among memory banks in which data are stored (i.e., memory banks which belong in the refresh region. And the data moving section 27 moves storage locations of all data stored in the movement source memory bank to the movement destination memory bank).
Regarding claims 5, 13 and 19, Kubota teaches wherein transferring the data comprises: transferring the data from the first memory bank to the second memory bank via the bank-to-bank transfer bus according to the direction in response to a user input (Fig.10 and [0101]-[0107]: at step S21, the data moving section 27 determines whether or not to move data. That is, whether or not it is time to move data is determined. Specifically, the data moving section 27 may determine that data should be moved at regular time intervals or when data is written to or deleted from the main memory 11. At step S22, the data moving section 27 determines the movement source memory bank from among four memory banks 112 to 115. Following step S22, at step S23, the data moving section 27 determines a movement destination memory bank.).
Regarding claims 6, 14 and 20, Kubota teaches determining a second direction to transfer data from the first memory bank of the plurality of memory banks to a third memory bank of the plurality of memory banks based on a second command associated with bank-to-bank transfer, the second direction different than the direction; and transferring the data from the first memory bank to the third memory bank via the bank-to-bank transfer bus according to the second direction (Fig. 10 and [0107]: at the state as illustrated in FIG. 11, when the time to move data comes, the data moving section 27 determines the movement source memory bank (step S22 of FIG. 10). In this case, the memory bank 114 having bank number B3 is determined as the movement source memory bank. Then, the data moving section 27 determines a movement destination memory bank (step S23 of FIG. 10). The process in Fig.10 is repeatable with a different movement source memory bank and a different movement destination memory bank, thereby determining a second direction different from the first direction).
Regarding claims 7 and 15, Kubota teaches wherein the data comprises a bit that indicates the direction ([0105]: the data moving section 27 updates the memory information stored in the memory information storing section 24 so as to reflect the data movement performed at step S25. Because the memory information includes bit-level representations, the memory information comprises a bit that indicates the direction).
Regarding claim 9, Kubota teaches wherein the bank-to-bank transfer bus comprises a ring architecture (Fig.1 and [0048]-[0049]: the memory banks 112-115 are coupled by a shared internal line arrangement. The shared arrangement among multiple memory banks corresponds to a ring architecture for the bank-to-bank transfer bus).
Regarding claims 10 and 17, Kubota teaches a plurality of shared input/output lines coupling respective memory banks of the plurality of memory banks to the bank-to-bank transfer bus, wherein, to transfer the data (Fig.1 and [0101]-[0107]: the data moving section 27 determines the movement source memory bank from among four memory banks 112 to 115. Following step S22, at step S23, the data moving section 27 determines a movement destination memory bank. The movement destination memory bank is selected from among memory banks in which data are stored (i.e., memory banks which belong in the refresh region. And the data moving section 27 moves storage locations of all data stored in the movement source memory bank to the movement destination memory bank), the controller is configured to: transfer the data from the bank-to-bank transfer bus to the second memory bank via at least one SIO line of the plurality of shared input/output lines (Fig.1: the line shared among memory banks 112-115 corresponds to the shared input/output (SIO) line).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Le et al. (Pub. No.: US 2009/0138626) “SPI BANK ADDRESSING SCHEME FOR MEMORY DENSITIES ABOVE 128Mb”
Considered for teachings related generally to peripheral interface devices and the like, and in particular, to a system and method of addressing two or more banks of memory utilizing a single-bank serial peripheral interface device and a three-byte addressing protocol.
Does not disclose or suggest determining a direction to transfer data from a first memory bank of a plurality of memory banks to a second memory bank of the plurality of memory banks based on a command associated with bank-to-bank transfer; and transferring the data from the first memory bank to the second memory bank via a bank-to-bank transfer bus according to the direction to transfer data from the first memory bank of the plurality of memory banks to the second memory bank of the plurality of memory banks.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to Yong Choe at telephone number 571-270-1053 or email to yong.choe@uspto.gov. The examiner can normally be reached on M-F 8:00am to 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rutz, Jared Ian can be reached on (571) 272-5535. Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 whose telephone number is (571) 272-2100.
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/YONG J CHOE/Primary Examiner, Art Unit 2135
