DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
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Claims 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-9, and 12-16 of (U.S 12181941 B2) in view of Matsubayashi et al (US 20050048337 A1).
Regarding claims 21, 28 and 35 (instant application), combinations of the claims 1 and 4 (US patent above), combinations of claims 9 and 12 (US patent above) substantially disclose similar claim limitations (see mapping below).
However the (US U.S 12181941 B2) does not explicitly teach tune the learning system according to a difference between the generated estimate and a measured power consumption of the processor.
Matsubayashi et al teaches tune (see fig.2 element 203) the learning system (see fig.2 element 202 and para [0059] for…….FIG. 3 is an explanatory block diagram of the neural network model (Examiner note: a neural network is well known to one of ordinary skill the art to be functionally equivalent to a learning system) for use in the neuro-model-based estimation section 202 in FIG. 2. The neural network model 300 is hierarchical-type neural network model having three layers consisting of an input layer, an intermediate layer and an output layer) according to a difference between the generated estimate and a measured power consumption of the processor (see para [0061] for… the neural network model 300 is configured such that the weighting factor thereof is corrected through a learning control using a back-propagation learning process in accordance with the difference (error) between an estimated value and a corresponding actually measured value, to provide enhanced accuracy of the estimation and para [0063] for….. the learning control using a back-propagation learning process is performed for the neural network model 300 in accordance with the difference (error) between the estimated power-consumption value and an actual power-consumption value corresponding to the estimated power-consumption value (hereinafter referred to as "measured power-consumption value)).
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify the above US Patent to include tune the learning system according to a difference between the estimate and the measured power consumption to control different events in a power generation system and avoid response to rapid changes in the power consumption during frequent operations. Such modification would enhance a power consumption power generation system to accurate estimate power consumption and efficiently control the power generation so as to achieve a desirable energy saving performance.
18/959,244 (instant application)
U.S 12,181,941 B2
21. (New) A processor, comprising: a learning system;
and dynamic power estimation circuitry configured to: generate a set of weights for a plurality of values of the learning system to generate an estimate of power consumption of the processor;
and tune the learning system according to a difference between the generated estimate and a measured power consumption of the processor.
1. A system, comprising:
dynamic power estimation circuitry configured to: generate a first estimate of power consumption of a processing circuit using one or more weights; responsive to the first estimate differing from a measured power consumption of the processing circuit by at least a threshold amount: modify the one or more weights to generate one or more modified weights; and generate a second estimate of power consumption of the processing circuit using the one or more modified weights; and power management circuitry configured to adjust a power performance state of the processing circuit based on a power consumption estimate generated by the dynamic power estimation circuitry.
4. The system as recited in claim 1, wherein the dynamic power estimation circuitry is configured to adjust the one or more weights such that a difference between the second estimate and the measured power consumption is less than a difference between the first estimate and the measured power consumption.
28. (New) A method, comprising: generating, by a learning system implemented by dynamic power estimation circuitry of a processor, a set of weights for a plurality of values to generate an estimate of power consumption of the processor;
and tuning the learning system according to a difference between the generated estimate and a measured power consumption of the processor.
9. A method, comprising: generating a first estimate of power consumption of a processing circuit using one or more weights; responsive to determining the first estimate differs from a measured power consumption of the processing circuit by at least a threshold amount: modifying the one or more weights to generate one or more modified weights; and generating a second estimate of power consumption of the processing circuit using the one or more modified weights; and adjusting a power performance state of the processing circuit based on one of the first estimate and the second estimate
12. The method as recited in claim 9, further comprising adjusting the one or more weights such that a difference between the second estimate and the measured power consumption is less than a difference between the first estimate and the measured power consumption.
35. (New) A system comprising: processing circuitry, further comprising: a learning system;
and dynamic power estimation circuitry configured to: generate a set of weights for a plurality of values of the learning system to generate an estimate of power consumption of the processing circuitry;
and tune the learning system according to a difference between the generated estimate and a measured power consumption of the processing circuitry.
1. A system, comprising:
dynamic power estimation circuitry configured to: generate a first estimate of power consumption of a processing circuit using one or more weights; responsive to the first estimate differing from a measured power consumption of the processing circuit by at least a threshold amount: modify the one or more weights to generate one or more modified weights; and generate a second estimate of power consumption of the processing circuit using the one or more modified weights; and power management circuitry configured to adjust a power performance state of the processing circuit based on a power consumption estimate generated by the dynamic power estimation circuitry.
4. The system as recited in claim 1, wherein the dynamic power estimation circuitry is configured to adjust the one or more weights such that a difference between the second estimate and the measured power consumption is less than a difference between the first estimate and the measured power consumption.
Regarding claims 22, 29 and 36 (instant application), claim 1 of the above US patent substantially discloses similar claim limitations.
Regarding claims 23, 30 and 37 (instant application), claims 5 and 13 of the above US patent substantially disclose similar claim limitations.
Regarding claim 24, 31 and 38 (instant application), claims 6 and 14 of the above US patent substantially disclose similar claim limitations.
Regarding claims 25, 32 and 39 (instant application), claims 1 and 9 of the above US patent substantially disclose similar claim limitations.
Regarding claims 26, 33 (instant application), claims 7 and 15 of the above US patent substantially disclose similar claim limitations.
Regarding claims 27, 34 (instant application), claims 8 and 16 of the above US patent substantially disclose similar claim limitations.
Regarding claims 40 (instant application), combination of claims 7 and 8 or 15 and 16 of the above US patent substantially disclose similar claim limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 21-23, 28-30 and 35-37 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bajic et al (US 20130024713 A1 ) in view of Litichever et al (US 20210350237 A1).
As per claims 21, 28 and 35, Bajic et al teaches a processor, comprising: an adaptive weight training algorithm (see fig.2 205); and dynamic power estimation circuitry (see fig.2 element 200 para [0009] for….. a power management unit measuring a total dynamic power consumed by an integrated circuit device during operation of the integrated circuit device and para [0029] for… The power estimation and management system 200) configured to: generate a set of weights (see fig.2 elements W(n)) for a plurality of values (see fig.2 element X(n)) of the adaptive weight training system (see para [0030] for…. the linear combiner 203 multiplies the various accumulated activity values X[n] with respective weight factor values W[n] provided by the adaptive weight training unit 205 using representative multipliers M1 and M2) to generate an estimate of power consumption (see fig.2 element y(n)) of the processor (see para [0007] for…..the power management unit may be configured to independently control a performance of each of the processor cores based upon the estimation of the power consumed by various portions of each processor core and para [0030] for……The output energy value is multiplied by a squared voltage value to produce a corresponding total estimated power value Y[n]);
and generate new weight values (see fig.2 element E(n the adaptive weight training system according to a difference (see fig.2 element S1) between the generated estimate (see fig.2 element Y(n)) and a measured power consumption (see fig.2 element D(n)) of the processor (see para [0007] for…..the power management unit may be configured to independently control a performance of each of the processor cores based upon the estimation of the power consumed by various portions of each processor core and para for….[0032] The total estimated power value Y[n] is provided to the subtractor S1 along with the total measured dynamic power value D[n] to produce an error signal E[n], which represents the difference between the measured power and the estimated power values. This error value E[n] is used by the adaptive weight training unit 205 to generate new weight factor values Examiner note: one of ordinary skill in the art would know that generate new weight factor values is functionally equivalent to the claimed subject matter “tune”).
However Bajic et al does not explicitly teach the adaptive weight training algorithm is a learning system (algorithm) and tune the learning system (algorithm).
Litichever et al teaches the adaptive weight training is a learning system (algorithm) (see para [0196] for…. A class of statistical models is typically referred to as “Neural” if it contains sets of adaptive weights, i.e. numerical parameters that are tuned by a learning algorithm, and capability of approximating non-linear functions from their inputs. The adaptive weights can be thought of as connection strengths between neurons, which are activated during training and prediction).
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify Bajic to include a learning system in order to receive a plurality signals wherein the plurality signals would be associated with a plurality of processing signals output by at least one processor and adjust the system parameters. Furthermore interconnection between multiple processors would generate different power estimations and measurements based on data over time in response to new data and new results. Such modification would facilitate each processor to handled load of data and subsequently enhance the learning system to make predictions with high accuracy.
As per claims 22, 29 and 36 Bajic and Litichever in combination would teach further comprising: power management circuitry (see Bajic fig.1 element 21) configured to: adjust a power performance state (see para [0027] for…. The power management unit 21 may increase or decrease the frequency of one or more cores, increase or decrease the operating voltages of the cores, or otherwise control the operational state of the cores in an effort to optimize performance while staying within the thermal budget of the processing node 12 based upon the power being consumed by the processor cores 15) of the processor based on a power consumption estimate generated by the dynamic power estimation circuitry (see Bajic para [0021] for…. . In addition, as described further below, the power management unit 21 may be configured to control the power consumed by each core based upon power estimates provided by the power monitors 17A through 17D within each of processor cores 15A through 15D, respectively) in order to receive a plurality signals wherein the plurality signals would be associated with a plurality of processing signals output by at least one processor and adjust the system parameters. Furthermore interconnection between multiple processors would generate different power estimations and measurements based on data over time in response to new data and new results. Such modification would facilitate each processor to handled load of data and subsequently enhance the learning system to make predictions with high accuracy.
As per claims 23, 30 and 37 Bajic and Litichever in combination would teach wherein the dynamic power estimation circuitry is configured to generate power consumption estimates based at least in part on one or more events occurring within the processor (see Bajic para [0024] for….. to determine an estimated power consumed by each respective processor core 15 or portions thereof using, in one embodiment, digital power estimation techniques that take into account digital signal activity within each processor core 15 Examiner note: one of ordinary skill in the art would know that activity is functionally equivalent to the claimed subject matter “event”) in order to receive a plurality signals wherein the plurality signals would be associated with a plurality of processing signals output by at least one processor and adjust the system parameters. Furthermore interconnection between multiple processors would generate different power estimations and measurements based on data over time in response to new data and new results. Such modification would facilitate each processor to handled load of data and subsequently enhance the learning system to make predictions with high accuracy.
----Claim(s) 26 and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bajic et al (US 20130024713 A1 ) in view of Litichever et al (US 20210350237 A1) and in further view of Cao et al 10,387,774 B1.
As per claim 26 and 33, Bajic and Litichever in combination do not teach wherein the dynamic power estimation circuitry is configured to tune the learning system (algorithm) based on a stochastic gradient descent algorithm.
Cao et al teaches wherein the dynamic power estimation circuitry is configured to tune the learning system (algorithm) based on a stochastic gradient descent algorithm (see col.8, lines 10-14 for…. The whole network can be trained using a standard error back-propagation algorithm with a stochastic gradient descent.).
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify Bajic and Litichever to a stochastic gradient descent algorithm in order to receive a plurality signals wherein the plurality signals would be associated with a plurality of processing signals output by at least one processor and adjust the system parameters. Furthermore interconnection between multiple processors would generate different power estimations and measurements based on data over time in response to new data and new results. Such modification would facilitate each processor to handled load of data and subsequently enhance the learning system to make predictions with high accuracy.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20150026109 A1 or US 20130024713 A1.
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/EMMANUEL BAYARD/Primary Examiner, Art Unit 2633