DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to amendment, filed on 7/1/2026, in which claims 21-40 are pending. The applicant’s amendments have been fully considered but they are moot since the amendments have not overcome the double patenting rejection below. Hence this case is made final.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21-40 rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-9, and 12-16 of (U.S 12181941 B2) in view of Matsubayashi et al (US 20050048337 A1).
Regarding claims 21, 28 and 35 (instant application), combinations of the claims 1 and 4 (US patent above), combinations of claims 9 and 12 (US patent above) substantially disclose similar claim limitations (see mapping below).
However the (US U.S 12181941 B2) does not explicitly teach a learning system configured to update the set of responsive weights to a difference between the generated estimate and a measured power consumption of the processor.
Matsubayashi et al teaches tune (see fig.2 element 203) the learning system (see fig.2 element 202 and para [0059] for…….FIG. 3 is an explanatory block diagram of the neural network model (Examiner note: a neural network is well known to one of ordinary skill the art to be functionally equivalent to a learning system) for use in the neuro-model-based estimation section 202 in FIG. 2. The neural network model 300 is hierarchical-type neural network model having three layers consisting of an input layer, an intermediate layer and an output layer) according to a difference between the generated estimate and a measured power consumption of the processor (see para [0061] for… the neural network model 300 is configured such that the weighting factor thereof is corrected through a learning control using a back-propagation learning process in accordance with the difference (error) between an estimated value and a corresponding actually measured value, to provide enhanced accuracy of the estimation and para [0063] for….. the learning control using a back-propagation learning process is performed for the neural network model 300 in accordance with the difference (error) between the estimated power-consumption value and an actual power-consumption value corresponding to the estimated power-consumption value (hereinafter referred to as "measured power-consumption value)).
It would have been obvious to one of ordinary skill in the art, at the time of filing or before the effective filing date of the claimed invention, to modify the above US Patent to include tune the learning system according to a difference between the estimate and the measured power consumption to control different events in a power generation system and avoid response to rapid changes in the power consumption during frequent operations. Such modification would enhance a power consumption power generation system to accurate estimate power consumption and efficiently control the power generation so as to achieve a desirable energy saving performance.
18/959,244 (instant application)
U.S 12,181,941 B2
21. (New) A processor, comprising: a
and dynamic power estimation circuitry configured to: apply a set of weights for a plurality of counter values corresponding to execution events of the processor to generate an estimate of power consumption of the processor;
and a learning system configured to update the set of weights responsive to a difference between the generated estimate and a measured power consumption of the processor.
1. A system, comprising:
dynamic power estimation circuitry configured to: generate a first estimate of power consumption of a processing circuit using one or more weights; responsive to the first estimate differing from a measured power consumption of the processing circuit by at least a threshold amount: modify the one or more weights to generate one or more modified weights; and generate a second estimate of power consumption of the processing circuit using the one or more modified weights; and power management circuitry configured to adjust a power performance state of the processing circuit based on a power consumption estimate generated by the dynamic power estimation circuitry.
4. The system as recited in claim 1, wherein the dynamic power estimation circuitry is configured to adjust the one or more weights such that a difference between the second estimate and the measured power consumption is less than a difference between the first estimate and the measured power consumption.
28. (New) A method, comprising: applying dynamic power estimation circuitry of a processor, a set of weights to a plurality of counter values corresponding to execution events of the processor to generate an estimate of power consumption of the processor;
and updating the set of weights by learning system responsive to a difference between the generated estimate and a measured power consumption of the processor.
9. A method, comprising: generating a first estimate of power consumption of a processing circuit using one or more weights; responsive to determining the first estimate differs from a measured power consumption of the processing circuit by at least a threshold amount: modifying the one or more weights to generate one or more modified weights; and generating a second estimate of power consumption of the processing circuit using the one or more modified weights; and adjusting a power performance state of the processing circuit based on one of the first estimate and the second estimate
12. The method as recited in claim 9, further comprising adjusting the one or more weights such that a difference between the second estimate and the measured power consumption is less than a difference between the first estimate and the measured power consumption.
35. (New) A system comprising: processing circuitry, further comprising:
and dynamic power estimation circuitry configured to: apply a set of weights for a plurality of counter values corresponding to execution events of the processor to generate an estimate of power consumption of the processing circuitry;
and a learning system configured update the set of weights to a difference between the generated estimate and a measured power consumption of the processing circuitry.
1. A system, comprising:
dynamic power estimation circuitry configured to: generate a first estimate of power consumption of a processing circuit using one or more weights; responsive to the first estimate differing from a measured power consumption of the processing circuit by at least a threshold amount: modify the one or more weights to generate one or more modified weights; and generate a second estimate of power consumption of the processing circuit using the one or more modified weights; and power management circuitry configured to adjust a power performance state of the processing circuit based on a power consumption estimate generated by the dynamic power estimation circuitry.
4. The system as recited in claim 1, wherein the dynamic power estimation circuitry is configured to adjust the one or more weights such that a difference between the second estimate and the measured power consumption is less than a difference between the first estimate and the measured power consumption.
Regarding claims 22, 29 and 36 (instant application), claim 1 of the above US patent substantially discloses similar claim limitations.
Regarding claims 23, 30 and 37 (instant application), claims 5 and 13 of the above US patent substantially disclose similar claim limitations.
Regarding claim 24, 31 and 38 (instant application), claims 6 and 14 of the above US patent substantially disclose similar claim limitations.
Regarding claims 25, 32 and 39 (instant application), claims 1 and 9 of the above US patent substantially disclose similar claim limitations.
Regarding claims 26, 33 (instant application), claims 7 and 15 of the above US patent substantially disclose similar claim limitations.
Regarding claims 27, 34 (instant application), claims 8 and 16 of the above US patent substantially disclose similar claim limitations.
Regarding claims 40 (instant application), combination of claims 7 and 8 or 15 and 16 of the above US patent substantially disclose similar claim limitations.
Allowable Subject Matter
Claims 21-40 would be allowable if a terminal disclaimer is filed to overcome the double patenting rejection(s) in compliance with 37 CFR 1.321(b), set forth in this Office action.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 10386395 B1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMMANUEL BAYARD whose telephone number is (571)272-3016. The examiner can normally be reached 6-9.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ahn K Sam can be reached at 571-272-3044. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EMMANUEL BAYARD/Primary Examiner, Art Unit 2633
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