DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 01/29/2026. Claims 1-22 remain pending with claims 1, 12, 14-17 have been amended.
Response to Arguments
Applicant's arguments filed 01/29/2026 have been fully considered but they are not persuasive.
In the remarks, Applicant’s made two main arguments.
a) Yao fails to cure the deficiencies of Lee. As shown below in Figure of the Lee reference, Lee uses a light-shielding layer 3 providing a window 4 above a primary light-emitting element 21 while covering an auxiliary light-emitting element 22. By turning on both the primary light-emitting element 21 and auxiliary light-emitting element 22, a wider viewing angle is provide.
This argument is not persuasive, as Figure 5 of Lee does not even disclose or show that “a light-shielding layer 3 providing a window 4 above a primary light-emitting element 21 while covering an auxiliary light-emitting element 22. By turning on both the primary light-emitting element 21 and auxiliary light-emitting element 22, a wider viewing angle is provide.”.
b) Lee reference is not prior art under 35 U.S.C. § 102(a)(1) as Lee was published on July 4, 2024, whereas the earliest priority data of the present application is December 28, 2023. The priority application fully supports the features recited in the claims. Further, the Lee reference is not prior art under 35 U.S.C. § 102(a)(2) as the subject matter disclosed in Lee and the claimed invention, not later than the effective filing date of the claimed invention, were owned by LG Display Co., LTD, or subject to an obligation of assignment to LG Display Co., LTD. See 35 U.S.C. § 102(b)(2)(C).
This argument is not persuasive. First of all, Lee does qualify as a prior art under 35 U.S.C. § 102(a)(1) because the Applicants have not provided a certified copy of translation of Lee’s foreign priority document, therefore, Lee is usable as a prior art under 35 U.S.C. § 103 rejection. Furthermore, Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55 . When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12-16, 18-22 are rejected under 35 U.S.C. 103 as being unpatentable over Charisoulis et al (US 2023/0091644), hereinafter as Charisoulis, in view of Yao et al (US 2023/0100284), hereinafter as Yao, and further in viewing Lee et al (US 2024/0221670), hereinafter as Lee.
RE claims 1 and 15, Charisoulis discloses the invention substantially as claimed.
Charisoulis discloses that a display panel (see figure 7 and section [0038]; i.e., display panel 60) comprising: a plurality of data lines, a plurality of gate lines, a plurality of power lines, and a plurality of pixels disposed on a substrate (see figure 7 and sections [0038], [0039], [0040], [0041]; i.e., data lines DATA[0], DATA[1] – DATA[M]; gate lines row0, row1 – row_N; power supply 84 including power lines 90, 88, 86; plurality of pixels 80 disposed on substrate/display 18), wherein each of the plurality of pixels (see figure 7 and section [0039]; i.e., pixel 80) includes: a first light-emitting element (see figure 10 and section [0047]; i.e., each pixel 100 of pixels 80 includes first light-emitting element 112A); a second light-emitting element (see figure 10 and section [0047]; i.e., each pixel 100 of pixels 80 includes second light-emitting element 112B); a compensation part configured to supply a current to the first light-emitting element and the second light-emitting element (see figure 10 and sections [0050], [0052]; i.e., current source 105 to supply current to the first light-emitting element 112A and the second light-emitting element 112B, and if one of the LEDs 112A/112B becoming inefficient, e.g., current efficiency below a threshold efficiency, the other LED 112 may compensate), and a switch circuit configured to supply the current to the first light-emitting element (see figure 10 and sections [0050], [0052]; i.e., current source 105 to supply current to the first light-emitting element 112A) and supply the current to the second light-emitting element (see figure 10 and sections [0050], [0052]; i.e., current source 105 to supply current to the second light-emitting element 112B when the first light-emitting element 112A being turned off) or to supply the current to both of the first light-emitting element and the second light-emitting element (see figure 10 and sections [0050], [0052]; i.e., current source 105 to supply current to both first light-emitting element 112A and second light-emitting element 112B together).
However, Charisoulis does not specifically disclose that a switch circuit configured to receive a mode selection signal, supply the current to the first light-emitting element but not the second light-emitting element in a first mode of the mode selection signal, and supply the current to at least the second light-emitting element in a second mode of the mode selection signal.
From the same field of endeavor, Yao teaches that a pixel driving circuit 7 for driving pixels of a display panel, comprising of threshold compensation module 74, wherein the pixel driving circuit 7 being connected to mode control module 6, primary light-emitting element 21 and auxiliary light-emitting element 22 (see figure 7 and sections [0083], [0084]). While the pixel driving circuit 7 supplying current to the primary light-emitting element 21, the mode control module 6 is configured to assist the pixel driving circuit 7 to switch between sharing mode and anti-peeping mode by supplying current to the auxiliary light-emitting element 22 when compensation needed for the primary light-emitting element 21 as determined by the threshold compensation module 74, under sharing mode both primary light-emitting element 21 and auxiliary light-emitting element 22 emitting light, while under anti-peeping mode, only primary light-emitting element 21 emitting light (see sections [0089], [0090], [0087]). The motivation of Yao is to control the viewing angle range of a display panel, thereby improving the user experience (see section [0013]).
Charisoulis and Yao are combinable because they are from the same field of endeavor. It would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to modify Charisoulis by including the teaching from Yao in order to control the viewing angle range of a display panel, thereby improving the user experience.
Furthermore, Charisoulis in view of Yao do not disclose that a first lens providing a first viewing angle disposed over the first light-emitting element; and a second lens providing a second viewing angle different from the first viewing angle disposed over the second light-emitting element.
From the same field of endeavor, Lee teaches that a display panel 100 comprising of a plurality of sub-pixels 101 (see figure 1 and sections [0046], [0048]), a pixel circuit of each sub-pixel including a first light-emitting element EL1 and a second light-emitting element EL2 (see figure 2 and sections [0066], [0067]), and a first lens LENS1 disposed on the first light-emitting element EL1 may be a semi-cylindrical lens for widen viewing angle or a hemispherical cross section lens for narrow viewing angle (see figure 3 and section [0082]). The motivation of Lee is to provide a capability of switching between a share mode and a privacy mode (see section [0008]).
Charisoulis, Yao and Lee are combinable because they are from the same field of endeavor. It would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to modify Charisoulis in view of Yao by including the teaching from Lee in order to provide a capability of switching between a share mode and a privacy mode.
RE claim 2, Charisoulis in view of Yao and the rationale above disclose that each of the pixels 80 including a plurality of sub-pixels 82 (see Charisoulis, figure 7 and sections [0038], [0043]), wherein each of the sub-pixels 82 including first light-emitting element 112A, second light-emitting element 112B (see Charisoulis, figure 10 and sections [0047], [0052]), the compensation part 74, the switch circuit 7 (see Yao, figure 7 and sections [0038], [0084], [0087]), wherein the switch circuit 7 (see Yao, figure 7) including: a first pixel switch element 72 connected between the compensation part 74 and the first light-emitting element 22 and configured to be turned on/off in response to a first mode selection signal from mode control module 6 (see Yao, figure 7 and its associated depictions), a second pixel switch element 72 connected between the compensation part 74 and the second emitting element 22 and configured to be turned on/off in response to a second mode selection signal from mode control module 6 (see Yao, figure 7 and its associated depictions), wherein the mode control part 6 is further configured to output the first mode selection signal and the second mode selection signal (see Yao, figure 7 and its associated depictions), and wherein, in the first mode, the first light-emitting element 21 is activated to emit light by a current supplied through the first pixel switch element 72 (see Yao, figure 7 and its associated depictions), and wherein, in the second mode, the second light-emitting element 22 is activated to emit light by a current supplied through the second pixel switch element 72 (see Yao, figure 7 and its associated depictions).
RE claim 3, Charisoulis in view of Yao and the rationale above disclose that a first switch element (see Yao, figure 7 and its associated depictions; i.e., M7 is the switch) configured to in response to a scan signal (see Yao, figure 7 and its associated depictions; i.e., scan signal Scan1), apply the first mode selection signal to a gate electrode of the first pixel switch element (see Yao, figure 7 and its associated depictions; i.e., mode control module 6); and a second switch element (see Yao, figure 7 and its associated depictions; i.e., M7 is the switch) configured to in response to a scan signal (see Yao, figure 7 and its associated depictions; i.e., scan signal Scan1), apply the first mode selection signal to a gate electrode of the first pixel switch element (see Yao, figure 7 and its associated depictions; i.e., mode control module 6).
RE claim 4, Charisoulis in view of Yao and the rationale above disclose that wherein the first switch element includes a first electrode connected to a first control signal configured to receive the first mode selection signal, a gate electrode configured to receive the scan signal, and a second electrode connected to the gate electrode of the first pixel switch element (see Yao, figure 7 and its associated depictions; i.e., the first switch element M7 including its first electrode, second electrode to receive first and second mode selection signals), and wherein the second switch element includes a first electrode connected to a second control signal configured to receive the second mode selection signal, a gate electrode configured to receive the scan signal, and a second electrode connected to the gate electrode of the second pixel switch element (see Yao, figure 7 and its associated depictions; i.e., the second switch element M7 including its first electrode, second electrode to receive first and second mode selection signals).
RE claim 5, Charisoulis in view of Yao and the rationale above disclose that a first capacitor connected between a power line configured to receive a constant voltage and the second electrode of the first switch electrode (see Yao, figure 7 and its associated depictions; i.e., capacitor Cst); and a second capacitor connected between the power line and the second electrode of the second switch element (see Yao, figure 7 and its associated depictions; i.e., capacitor Cst).
RE claim 6, Charisoulis in view of Yao and the rationale above disclose that wherein each of the plurality of pixels 80 further including a plurality of sub-pixels 82 (see Charisoulis, figure 7 and its associated depictions), wherein each of the sub-pixels includes the first light-emitting element 112A. the second light-emitting element 112B (see Charisoulis, figure 10 and its associated depictions), the compensation part and the switch circuit (see Charisoulis, section [0052]), wherein the switch circuit includes a pixel switch element connected between the compensation part And the second light-emitting element and configured to be turned on/off in response to a second mode selection signal (see Charisoulis, sections [0052], [0053]), wherein the mode control part is further configured to output the second mode selection signal (see Yao, figure 7 and its associated depictions; i.e., the mode control module 6), and wherein, in the first mode, the first light-emitting element is activated to emit light by a current from the compensation part (see Charisoulis, section [0052]), and in the second mode, the first light-emitting element is activated to emit light by the current from the compensation part and the second light-emitting element is activated to emit light by a current supplied through the pixel switch element (see Charisoulis, sections [0052], [0053]).
RE claim 7, Charisoulis in view of Yao and the rationale above disclose that a switch element configured to in response to a scan signal, apply the second mode selection signal to a gate electrode of the pixel switch element (see Yao, figure 7 and its associated depictions; i.e., the switch M7).
RE claim 8, Charisoulis in view of Yao and the rationale above disclose that the switch element includes a first electrode connected to a control signal line configured to receive the second mode selection signal, a gate electrode configured to receive the scan signal, and a second electrode connected to the gate electrode of the pixel switch element (see Yao, figure 7 and its associated depictions; i.e., the switch M7 includes its electrodes connected to control signa line from M4 to receive mode selection signal from mode control module 6).
RE claim 9, Charisoulis in view of Yao and the rationale above disclose that a capacitor Cst connected between a power line PVDD configured to receive a constant voltage and the second electrode of the switch element M6 (see Yao, figure 7 and its associated depictions).
RE claim 10, Charisoulis in view of Yao and the rationale above disclose that an EVDD power line configured to supply a pixel driving voltage to the compensation part, and a VDD power line configured to supply a constant voltage to the mode control part, wherein the EVDD power line includes: a first EVDD power line; and a second EVDD power line connected to the first EVDD power line, and wherein the VDD power line crosses over the second EVDD power line and the VDD power line is separated from both of the first EVDD power line and the second EVDD power line by an insulating layer (see Yao, figure 7 and its associated depictions; i.e., power line PVDD, PVEE, compensation module 74, and so on).
RE claim 12, Charisoulis in view of Yao and the rationale above disclose that a driving element including a first electrode connected to a first node, a gate electrode connected to a second node, and a second electrode connected to a third node (see Yao, figure 7 and its associated depictions; i.e., driving element Mo including its electrodes connected to various nodes); a first compensation switch element connected between the second node and the third node and configured to be turned on in response to a first scan signal (see Yao, figure 7 and its associated depictions; i.e., first compensation switch M4 connected between its nodes and configured to be turned on in response to a first scan signal Scan1); a second compensation switch element connected between a data line configured to receive a data voltage and the first node (see Yao, figure 7 and its associated depictions; i.e., compensation switch M4 connected between data line from driving transistor M0 and a node), and the second compensation switch element being configured to be turned on in response to a second scan signal (see Yao, figure 7 and its associated depictions; i.e., compensation switch M4 configured to be turned on in response to a scan signal Scan2); a third compensation switch element connected between a power line configured to receive a pixel driving voltage and the first node, and the third compensation switch element being configured to be turned on/off in response to an emission signal (see Yao, figure 7 and its associated depiction; i.e., compensation switch M4 configured to be turned on/off in response to an emission signal Emit1/Emit2); a fourth compensation switch element connected between the third node and the fourth node, and the fourth compensation switch element being configured to be turned on/off in response to the emission signal (see Yao, figure 7 and its associated depiction; i.e., compensation switch M4 configured to be turned on/off in response to an emission signal Emit1/Emit2); and a storage capacitor connected between a power node to configured to receive the pixel driving voltage and the second node (see Yao, figure 7 and its associated depictions; i.e., storage capacitor Cst connected between power node 76 configured to receive the pixel driving voltage from M6 and a node), wherein the mode control part includes: one or more switch elements configured to be turned on/off in response to the second scan signal (see Yao, figure 7 and its associated depictions; i.e., mode control module 6 includes switches M7 configured to be turned on/off in response to scan signal Scan1/Scan2).
RE claims 13 and 14, Charisoulis in view of Yao and the rationale above disclose that a fifth compensation switch element connected between the second node and an initialization power line configured to receive an initialization voltage, and the fifth compensation switch element being configured to be turned on/off in response to a fourth scan signal (see Yao, figure 7 and its associated depictions; i.e., compensation switch M4 connected between a node and initialization power line from M0, and the fifth compensation switch element M4 configured to be turned on/off in response to a scan signal Scan1); a sixth compensation switch element connected between a fifth node and a first compensation power line configured to receive a first compensation voltage, the sixth compensation switch element being configured to be turned on/off in response to a third scan signal (see Yao, figure 7 and its associated depictions; i.e., compensation switch M4 connected between a node and a compensation power line from M0 to receive a compensation voltage, the sixth compensation switch M4 configured to be turned on/off in response to a scan signal Scan1/Scan2); a seventh compensation switch element connected between a sixth node and a first compensation power line, and the seventh compensation switch element being configured to be turned on/off in response to the third scan signal (see Yao, figure 7 and its associated depictions; i.e., compensation switch M4 connected between a node and a compensation power line from M0 to receive a compensation voltage, the sixth compensation switch M4 configured to be turned on/off in response to a scan signal Scan1/Scan2); and an eighth compensation switch element connected between the first node and a second compensation power line configured to receive a second compensation voltage, and the eighth compensation switch element being configured to be turned on/off in response to the third scan signal (see Yao, figure 7 and its associated depictions; i.e., compensation switch M4 connected between a node and a compensation power line from M0 to receive a compensation voltage, the eighth compensation switch M4 configured to be turned on/off in response to a scan signal Scan1/Scan2), wherein the switch circuit includes: a first pixel switch element connected between the fourth node and the fifth node, and configured to be turned on to supply a current from the driving element to the first light-emitting element in the first mode (see Yao, figure 7 and its associated depictions; i.e., pixel switch M2 connected between its nodes, and configured to be turned on to supply a current from the driving element Mo to the first light-emitting element 21 in the first mode); and a second pixel switch element connected between the fourth node and the sixth node, and configured to be turned on to supply the current from the driving element to the second light-emitting element in the second node (see Yao, figure 7 and its associated depictions; i.e., pixel switch M7 connected between its nodes, and configured to be turned on to supply the current from the driving element M0 to the second light-emitting element 22 in the second mode), and wherein the first light-emitting element includes an anode electrode connected to the fifth node, and a cathode electrode connected to a cathode power line configured to receive a cathode voltage (see Yao, figure 7 and its associated depictions; i.e., light-emitting element 21 including its anode electrode connected to its node, and a cathode node connected to a cathode power line PVEE configured to receive a cathode voltage), and wherein the second light-emitting element includes an anode electrode connected to the sixth node, and a cathode electrode connected to the cathode power line (see Yao, figure 7 and its associated depictions; i.e., the second light-emitting element 22 including its anode electrode connected to its node, and a cathode node connected to the cathode power line PVEE).
RE claim 16, Charisoulis discloses the invention substantially as claimed.
Charisoulis discloses that a display panel (see figure 7 and section [0038]; i.e., display panel 60) comprising: a subpixel including a first light-emitting element configured to emit a same color light and a second light-emitting element configured to emit the same color light (see figures 7/8/10 and its associated depictions; i.e., subpixel 82 including first light-emitting element 112A and second light-emitting element 112B to emit same color light), a controller configured to: in response to a first mode, activate the first light-emitting element to emit the same color light, and in response to a second mode, activate the second emitting element to emit the same color light (see sections [0052], [0064]; i.e., the first LED 112A and the second LED 112B may be controlled to be turned on/off at different times for blending to provide a smooth transition when one of the LEDs 112 becoming inefficient, e.g., current efficiency below a threshold efficiency, the other LED 112 may compensate).
However, Charisoulis does not specifically disclose that a first light-emitting element configured to emit a same color light with a narrow viewing angle, and a second light-emitting element configured to emit the same color light with a wide viewing angle wider than the narrow viewing angle, and a controller to: in response to a first mode, activate the first light-emitting element to emit the same color light with the narrow viewing angle, and in response to a second mode, activate the second light-emitting element to emit the same color light with the wide viewing angle.
Yao teaches that a display panel can operate in a sharing mode and an anti-peeping mode (see section [0081]), wherein in the sharing mode, both the primary light-emitting element 21 and the auxiliary light-emitting element 22 of the display panel configured to emit light, while in the anti-peeping mode, only the primary light-emitting element 21 emitting light and the auxiliary light-emitting element 22 does not emit light (see section [0081]). Since only primary light-emitting element 21 configured to emit light with narrow viewing angle in anti-peeping mode, thereby protecting the user’s privacy well achieved (see section [0078] and figure 5 and its associated depictions). The auxiliary light-emitting element 22 configured to emit light with wide viewing angle (see figure 5 and its associated depictions). The motivation of Yao is to control the viewing angle range of a display panel, thereby improving the user experience (see section [0013]).
Charisoulis and Yao are combinable because they are from the same field of endeavor. It would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to modify Charisoulis by including the teaching from Yao in order to control the viewing angle range of a display panel, thereby improving the user experience.
Furthermore, Charisoulis in view of Yao do not disclose that a first lens providing the narrow viewing angle disposed over the first light-emitting element; and a second lens providing the wide viewing angle disposed over the second light-emitting element.
From the same field of endeavor, Lee teaches that a display panel 100 comprising of a plurality of sub-pixels 101 (see figure 1 and sections [0046], [0048]), a pixel circuit of each sub-pixel including a first light-emitting element EL1 and a second light-emitting element EL2 (see figure 2 and sections [0066], [0067]), and a first lens LENS1 disposed on the first light-emitting element EL1 may be a semi-cylindrical lens for widen viewing angle or a hemispherical cross section lens for narrow viewing angle (see figure 3 and section [0082]). The motivation of Lee is to provide a capability of switching between a share mode and a privacy mode (see section [0008]).
Charisoulis, Yao and Lee are combinable because they are from the same field of endeavor. It would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to modify Charisoulis in view of Yao by including the teaching from Lee in order to provide a capability of switching between a share mode and a privacy mode.
RE claim 18, Charisoulis in view of Yao and the rationale above disclose that in response to the first mode, activate the first light emitting element to emit the same color light while the second light emitting element is deactivated (see Yao, section [0081]; i.e., the anti-peeping mode), and in response to the second mode, activate both of the first light emitting element and second light-emitting element to emit the same color light (see Yao, section [0081]; i.e., the sharing mode).
RE claim 19, Charisoulis in view of Yao and the rationale above disclose that at least one switching transistor (see Yao, figure 7 and its associated depictions; i.e., switching transistor M1) having a gate electrode configured to receive a scan signal (see Yao, figure 7 and its associated depictions; i.e., scan signal Scan1), a first electrode connected to a capacitor (see Yao, figure 7 and its associated depictions; i.e., capacitor Cst), and a second electrode connected to a mode selection line (see Yao, figure 7 and its associated depictions; i.e., mode control module 6), and wherein the capacitor is connected between a first power line and the at least one switching transistor (see Yao, figure 7 and its associated depictions; i.e., capacitor Cst connected between power line PVDD and switching transistor M4).
RE claim 20, Charisoulis in view of Yao and the rationale above disclose that a second power line connected to the subpixel and configured to provide a pixel driving voltage to the subpixel (see Yao, figure 7 and its associated depictions; i.e., power line PVDD connected to the subpixel 7 to provide a pixel driving voltage to the driving transistor M0), wherein the first power line of the controller is electrically isolated from the second power line of the subpixel (see Yao, figure 7 and its associated depictions; i.e., the power line Vref is electrically isolated from the power line PVDD).
RE claim 21, Charisoulis in view of Yao and the rationale above disclose that a plurality of subpixels including the subpixel having the first and second light emitting elements (see Yao, figures 1&7 and its associated depictions; i.e., subpixel 7 having first LED 21 and second LED 22; wherein the controller is further configured to: selectively activate a group of subpixels from among the plurality of subpixels to operate in the first mode to display first content with the narrow viewing angle, while a reminder of subpixels among the plurality of subpixels operate in the second mode to display second content while the wide viewing angle (see Yao, sections [0081], [0082]; i.e., the sharing mode having wide viewing angle, the anti-peeping mode having narrow viewing angle).
RE claim 22, Charisoulis in view of Yao and the rationale above disclose that a plurality of pixels including a plurality of subpixels including the subpixels having the first and second light emitting elements (see Charisoulis, figures 7&10 and its associated depictions; i.e., pixels 80 including a plurality of subpixels 82, each subpixel 82 having first light emitting element 112A and second light emitting element 112B), wherein the controller is further configured to selectively operate the plurality of subpixels in the first mode having the narrow viewing angle or the second mode having the wide viewing angle on a pixel by pixel basis (see Yao, sections [0081], [0082]; i.e., the sharing mode having wide viewing angle, the anti-peeping mode having narrow viewing angle).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Charisoulis et al (US 2023/0091644), hereinafter as Charisoulis, in view of Yao et al (US 2023/0100284), hereinafter as Yao, and further in viewing Lee et al (US 2024/0221670), hereinafter as Lee.
RE claim 17, Charisoulis in view of Yao disclose the invention substantially as claimed.
However, Charisoulis in view of Yao do not disclose that the first lens is a hemispherical shaped lens; and the second lens is a semi-cylindrical shaped lens.
From the same field of endeavor, Lee teaches that a display panel 100 comprising of a plurality of sub-pixels 101 (see figure 1 and sections [0046], [0048]), a pixel circuit of each sub-pixel including a first light-emitting element EL1 and a second light-emitting element EL2 (see figure 2 and sections [0066], [0067]), and a first lens LENS1 disposed on the first light-emitting element EL1 may be a semi-cylindrical lens for widen viewing angle or a hemispherical cross section lens for narrow viewing angle (see figure 3 and section [0082]). The motivation of Lee is to provide a capability of switching between a share mode and a privacy mode (see section [0008]).
Allowable Subject Matter
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication from the examiner should be directed to FRED TZENG whose telephone number is 571-272-7565. The examiner can normally be reached on weekdays from 2:0 pm to 10:00 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Boddie can be reached on 571-272-0666. The fax phone numbers for the organization where this application or proceeding is assigned are 571-273-8300 for regular communications and 571-273-7565 for After Final communications.
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/FRED TZENG/ Primary Examiner, Art Unit 2625
FFT
March 25, 2026