Prosecution Insights
Last updated: April 19, 2026
Application No. 18/959,323

LAYERED DECODING METHOD AND APPARATUS FOR LOW DENSITY PARITY CHECK CODE IN COMMUNICATION SYSTEM

Non-Final OA §101
Filed
Nov 25, 2024
Examiner
CHASE, SHELLY A
Art Unit
2112
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
98%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
715 granted / 755 resolved
+39.7% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
17 currently pending
Career history
772
Total Applications
across all art units

Statute-Specific Performance

§101
13.2%
-26.8% vs TC avg
§103
38.2%
-1.8% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
15.9%
-24.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 755 resolved cases

Office Action

§101
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1 to 20 are presented for examination. Priority Receipt is acknowledged of papers submitted under 35 U.S.C. 119, which papers have been placed of record in the file. Information Disclosure Statement The references listed in the information disclosure statement submitted on 11-25-2024 and 9-5-2025 have been considered by the examiner (see attached PTO-1449). Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1 to 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 1, recites performing layered decoding based on at least a portion of the parity check matrix and at least a portion of the first layer scheduling sequence. This limitation as drafted is a process that, under the broadest reasonable interpretation, covers mathematical calculations except for the step of “receiving a signal transmitted from a transmitter.” Nothing in the claim prevents the limitation of layered decoding from being part of a mathematical calculation of the mathematical concept grouping. The limitation of receiving a signal transmitted from a transmitter is recited at a high-level of generality and fails to prevent the abstract idea from performing the mathematical calculation. Thus, the claim recites an abstract idea. This judicial exception is not integrated into a practical application because the other limitations of claim 1 are mere components for performing the abstract idea and fails to integrate the abstract idea into a practical application. The other limitations recited in the claim are components for the abstract idea, they are “identifying a parity check matrix for decoding the signal,” “wherein the fist layer scheduling sequence corresponds to a plurality of layers of which each layer is configured with one or more row block of the parity check matrix,” and “wherein the plurality of layers corresponding to the first layer scheduling sequence respectively corresponds to one or more index included in the first layer scheduling sequence.” These limitations are components of the abstract idea and fails to add any meaningful limits to the abstract idea as well as fails to integrate the abstract idea into a practical application. Claim 1 includes one additional limitation that is generic in nature and is not sufficient to amount to significantly more than the judicial exception because the limitation of “receiving a signal transmitted from a transmitter is a generic computer component and fails to add significantly more than the abstract idea. The additional limitation is merely a component for performing the abstract idea and does not impart any meaningful limits to the abstract idea to improve a computer or technology. Therefore, the claim is not patent eligible. Dependent claims 2 to 11 are mere components for processing the abstract idea of the independent claim and fails to add any meaningful limits to the abstract idea. The limitations recited in dependent claims 2 to 11 are directed to a mathematical relationship that are part of the mathematical grouping concept thus they do not include any limitations that are significantly more than the abstract idea. The limitations of the dependent claims fail to integrate the abstract idea into a practical application and fails to improve the computer or the technology. Therefore, dependent claims 2 to 11 are not patent eligible. Claim 12: Independent claim 12, is similar to claim 1 and is rejected for the same rationale applied to claim 1. The claim recites a control unit comprising circuitry to perform layered decoding based on at least a portion of the parity check matrix and at least a portion of the first layer scheduling sequence. This limitation as drafted is a process that, under the broadest reasonable interpretation, covers mathematical calculation except for the step of a transceiver and “receiving a signal transmitted from a transmitter.” Nothing in the claim prevents the limitation of layered decoding from being part of a mathematical calculation of the mathematical concept grouping. The additional limitation of a transceiver and receiving a signal transmitted from a transmitter are recited at a high-level of generality and fail to prevent the abstract idea from performing the mathematical calculation. Thus, the claim recites an abstract idea. This judicial exception is not integrated into a practical application because the other limitations of the claimed are mere components for performing the abstract idea and fails to integrate the abstract idea into a practical application. The other limitations recited in the claim that are components for the abstract idea are “identifying a parity check matrix for decoding the signal,” “wherein the first layer scheduling sequence corresponds to a plurality of layers of which each layer is configured with one or more row block of the parity check matrix,” and “wherein the plurality of layers corresponding to the first layer scheduling sequence respectively corresponds to one or more index included in the first layer scheduling sequence.” These limitations are components of the abstract idea and fails to add any meaningful limits to the abstract idea as well as, fails to integrate the abstract idea into a practical application. The claim includes additional limitations that are generic in nature and are not sufficient to amount to significantly more than the judicial exception because the limitations of “a transceiver” and “receiving a signal transmitted from a transmitter” are generic computer component and fails to add significantly more than the abstract idea. The additional limitations are merely components for performing the abstract idea and do not impart any meaningful limits to the abstract idea to improve the computer or the technology. Therefore, the claim is not patent eligible. Dependent claims 13 to 20 are mere components for processing the abstract idea of the independent claim and fails to add any meaningful limits to the abstract idea. The limitations recited in dependent claims 13 to 20 are directed to a mathematical relationship that are part of the mathematical grouping and fails to include any limitation that are significantly more than the abstract idea. The limitations of the dependent claims fail to integrate the abstract idea into a practical application and fail to improve a computer or technology. Therefore, dependent claims 13 to 20 are not patent eligible. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Micheloni et al. (9,813,080 B1) teaches a method to decode low-density parity (LDPC) encoded data using a parity check matrix having a plurality of layers. Varnica et al. (8,291,285 B1) teaches a system and method for decoding low-density parity check codes. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Albert Decady can be reached at 571-272 3819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Shelly A Chase/Primary Examiner, Art Unit 2112
Read full office action

Prosecution Timeline

Nov 25, 2024
Application Filed
Feb 16, 2026
Non-Final Rejection — §101 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603144
BLOCK HEALTH DETECTOR FOR BLOCK RETIREMENT IN A MEMORY SUB-SYSTEM
2y 5m to grant Granted Apr 14, 2026
Patent 12603753
SIGNAL TRANSMITTING METHOD, ELECTRONIC DEVICE, AND COMMUNICATION SYSTEM
2y 5m to grant Granted Apr 14, 2026
Patent 12596610
PARITY DATA IN DYNAMIC RANDOM ACCESS MEMORY (DRAM)
2y 5m to grant Granted Apr 07, 2026
Patent 12572413
MEMORY CONTROLLERS AND MEMORY SYSTEMS
2y 5m to grant Granted Mar 10, 2026
Patent 12572412
MANAGING ERROR CORRECTIONS FOR DATA STORAGE SYSTEMS
2y 5m to grant Granted Mar 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
98%
With Interview (+3.3%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 755 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month