DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 4/8/26, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kinter (US 20020156996) in view of Burger (US 20170083337) and Scrbak (US 20250245160).
With respect to claim 1, the Kinter reference teaches an instruction cache, comprising:
an instruction cache bank, configured to store instructions for a processor; (e.g. fig. 1, instruction cache 102 with “banks” 140A-D; paragraph 33, where the processor determines that there was a "miss" upon reading instruction cache 102, the processor accesses bus interface 103 to obtain instruction 132 from memory 104 (interconnection of bus interface 103 and memory 104 not shown). The processor supplies the memory address 133 of the instruction that was not identified in the cache memory 102 to memory 104 via bus interface 103)
a buffer, configured to store a portion of the instructions outputted from the instruction cache bank; (e.g. fig. 1, fill buffer 130; and paragraph 33, where fill buffer 130 is present and serves as a staging point for cache memory. Fill buffer 130 comprises a tag component 131 and its associated data component or instruction 132. If the processor determines that there was a "miss" upon reading instruction cache 102, the processor accesses bus interface 103 to obtain instruction 132 from memory 104 (interconnection of bus interface 103 and memory 104 not shown)) and
a selection circuit, coupled to the instruction cache bank and the buffer, (e.g. fig. 1, mux 115) and configured to select a specific instruction from one of the instruction cache bank and the buffer to be output as an output instruction for the processor according to whether a read address is found in the buffer or not. (paragraph 32, where multiplexor 115 receives the indicator signal from tag comparator 125, selects the desired instruction, and then transmits the desired instruction to mapper 120. Mapper 120 maps the desired instruction of the first instruction set to a PIWF configuration and transmits a mapped instruction 150 to a decoder 152. Decoder 152 decodes the mapped instructions and provides control signals to execution core 155 for execution)
However, the Kinter reference does not explicitly teach that the buffer is a circular buffer, wherein access speed of the circular buffer is faster than access speed of the instruction cache bank; and the specific instruction is outputted from the circular buffer when the read address is found in the circular buffer while the specific instruction is outputted from the instruction cache bank when the read address is not found in the circular buffer.
The Burger reference teaches it is conventional to have the buffer be a circular buffer, wherein access speed of the circular buffer is faster than access speed of the instruction cache bank. (Burger, paragraph 126, where a circular buffer may potentially be lower power and faster than a comparable sized cache. The streaming instruction
buffer 823 can be configured to selectively store lines of a predicted instruction block in the SIB memory 834. For example, all of the lines of the predicted instruction block can be stored in sequential order at a tail of the streaming instruction buffer 823)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Kinter reference to have wherein the buffer is a circular buffer, wherein access speed of the circular buffer is faster than access speed of the instruction cache bank, as taught by the Burger reference.
The suggestion/motivation for doing so would have been to have a buffer that is lower power and faster than a comparable sized cache. (Burger, paragraph 126)
However, the combination of the Kinter and Burger references does not explicitly teach that the specific instruction is outputted from the circular buffer when the read address is found in the circular buffer while the specific instruction is outputted from the instruction cache bank when the read address is not found in the circular buffer.
The Scrbak reference teaches it is conventional to have that the specific instruction is outputted from the circular buffer when the read address is found in the circular buffer while the specific instruction is outputted from the instruction cache bank when the read address is not found in the circular buffer. (paragraph 21, where the fine-grained memory aware prefetcher is further configured to: select a load instruction associated with the data to be prefetched, perform a cache lookup in the cache for a physical address associated with the load instruction, perform a side buffer lookup in the side buffer for the physical address associated with the load instruction, and responsive to a hit in the cache lookup or the side buffer lookup, perform a prefetcher training table lookup in a prefetcher training table)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the combination of Kinter and Burger references to have wherein the specific instruction is outputted from the circular buffer when the read address is found in the circular buffer while the specific instruction is outputted from the instruction cache bank when the read address is not found in the circular buffer, as taught by the Scrbak reference.
The suggestion/motivation for doing so would have been to predict and fetch, in advance, the data or instructions to be used by a processor (e.g., a central processing unit or “CPU”) in the near future. (Scrbak, abstract)
Therefore it would have been obvious to combine the Kinter, Burger, and Scrbak references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the Kinter, Burger, and Scrbak references teaches the instruction cache of claim 1, wherein when the read address is found in the circular buffer, the circular buffer is configured to output the specific instruction from the circular buffer according to the read address, and the selection circuit is configured to select the specific instruction to be output as the output instruction. (Kinter, paragraph 34, where just as a cache line is accessed upon the data read operation, fill buffer 130 is accessed. Tag 131 of fill buffer 130 is compared to the tag of the sought address. If there is a hit, tag comparator 125 transmits a signal to multiplexor 125 to select data 132 because its associated tag 131 was the hit. Multiplexor 125 then passes the selected instruction to be processed to mapper 120 and transmits it downstream to the execution core, just as if the selected instruction had been stored in cache memory)
With respect to claim 3, the Kinter, Burger, and Scrbak references teaches the instruction cache of claim 1, wherein when the read address is not found in the circular buffer, the instruction cache bank is configured to output the specific instruction according to the read address, and the selection circuit is configured to select the specific instruction to be output as the output instruction. (Kinter, paragraph 33, where fill buffer 130 is present and serves as a staging point for cache memory. Fill buffer 130 comprises a tag component 131 and its associated data component or instruction 132. If the processor determines that there was a "miss" upon reading instruction cache 102, the processor accesses bus interface 103 to obtain instruction 132 from memory 104 (interconnection of bus interface 103 and memory 104 not shown))
With respect to claim 4, the Kinter, Burger, and Scrbak references teaches the instruction cache of claim 3, wherein the read address and the specific instruction outputted from the instruction cache bank are written into the circular buffer when or after the instruction cache bank outputs the specific instruction according to the read address. (Kinter, paragraph 33, where fill buffer 130 is present and serves as a staging point for cache memory. Fill buffer 130 comprises a tag component 131 and its associated data component or instruction 132. If the processor determines that there was a "miss" upon reading instruction cache 102, the processor accesses bus interface 103 to obtain instruction 132 from memory 104 (interconnection of bus interface 103 and memory 104 not shown))
With respect to claim 5, the Kinter, Burger, and Scrbak references teaches the instruction cache of claim 1, wherein the circular buffer comprises: an address buffer, configured to store multiple addresses; an instruction buffer, configured to store multiple instructions respectively corresponding to the multiple addresses; and a comparing circuit, coupled to the address buffer, and configured to determine whether any of the multiple addresses matches the read address, in order to generate a comparison result; wherein the selection circuit is configured to select the specific instruction from one of the instruction bank and the instruction buffer of the circular buffer to be output as the output instruction according to the comparison result. (Kinter, paragraph 34, where just as a cache line is accessed upon the data read operation, fill buffer 130 is accessed. Tag 131 of fill buffer 130 is compared to the tag of the sought address. If there is a hit, tag comparator 125 transmits a signal to multiplexor 125 to select data 132 because its associated tag 131 was the hit. Multiplexor 125 then passes the selected instruction to be processed to mapper 120 and transmits it downstream to the execution core, just as if the selected instruction had been stored in cache memory) and (Scrbak, paragraph 21, where the fine-grained memory aware prefetcher is further configured to: select a load instruction associated with the data to be prefetched, perform a cache lookup in the cache for a physical address associated with the load instruction, perform a side buffer lookup in the side buffer for the physical address associated with the load instruction, and responsive to a hit in the cache lookup or the side buffer lookup, perform a prefetcher training table lookup in a prefetcher training table)
With respect to claim 6, the Kinter, Burger, and Scrbak references teaches the instruction cache of claim 5, wherein when the comparison result indicates that a specific address of the multiple addresses matches the read address, the instruction buffer is configured to output a specific instruction corresponding to the specific address to be the second instruction, and the selection circuit is configured to select the second instruction to be output as the output instruction. (Kinter, paragraph 34, where just as a cache line is accessed upon the data read operation, fill buffer 130 is accessed. Tag 131 of fill buffer 130 is compared to the tag of the sought address. If there is a hit, tag comparator 125 transmits a signal to multiplexor 125 to select data 132 because its associated tag 131 was the hit. Multiplexor 125 then passes the selected instruction to be processed to mapper 120 and transmits it downstream to the execution core, just as if the selected instruction had been stored in cache memory)
With respect to claim 7, the Kinter, Burger, and Scrbak references teaches the instruction cache of claim 5, wherein when the comparison result indicates that none of the multiple addresses matches the read address, the instruction cache bank is configured to output the first instruction according to the read address, and the selection circuit is configured to select the first instruction to be output as the output instruction. (Kinter, paragraph 33, where fill buffer 130 is present and serves as a staging point for cache memory. Fill buffer 130 comprises a tag component 131 and its associated data component or instruction 132. If the processor determines that there was a "miss" upon reading instruction cache 102, the processor accesses bus interface 103 to obtain instruction 132 from memory 104 (interconnection of bus interface 103 and memory 104 not shown))
With respect to claim 8, the Kinter, Burger, and Scrbak references teaches the instruction cache of claim 7, wherein the read address is written into the address buffer, and the first instruction output from the instruction cache bank is written into the instruction buffer when or after the instruction cache bank outputs the first instruction according to the read address. (Kinter, paragraph 33, where fill buffer 130 is present and serves as a staging point for cache memory. Fill buffer 130 comprises a tag component 131 and its associated data component or instruction 132. If the processor determines that there was a "miss" upon reading instruction cache 102, the processor accesses bus interface 103 to obtain instruction 132 from memory 104 (interconnection of bus interface 103 and memory 104 not shown). The processor supplies the memory address 133 of the instruction that was not identified in the cache memory 102 to memory 104 via bus interface 103)
With respect to claim 9, the Kinter, Burger, and Scrbak teaches the instruction cache of claim 5, wherein the instruction cache bank is further configured to receive and store an instruction in response to a write address, and when the write address is found in the address buffer a specific instruction stored in the instruction buffer corresponding to the write address is marked as an invalid instruction. (Burger, paragraph 96, where a speculative block can complete when it is determined the work of the block will be used, all register writes are buffered, all writes to memory are buffered, and a branch target is calculated, for example. A non-speculative block can execute to completion when all register writes are buffered, all writes to memory are buffered, and a branch target is calculated; and paragraph 154, where when the execution path is incorrectly predicted, the prefetched instruction blocks in the streaming instruction buffer can be either invalidated or marked as mispredicted)
Claims 10-14 are the circular buffer implementation of claims 1-9, and rejected under a similar rationale as shown in the rejections above.
Claims 15-20 are the method implementation of claims 1-9, and rejected under a similar rationale as shown in the rejections above.
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 12-17 of the remarks) and amendments with respect to claims 1-20 have been considered, and are persuasive. Particularly, the Examiner notes the updated citations from the Kinter and Burger references and the inclusion of the Scrbak reference to teach the newly amended claim language as shown in the rejections above.
3. CLOSING COMMENTS
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137
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