DETAILED ACTION
This Office action is in response to the application filed on 26 November 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 13 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Maru et al. (US 2024/0333127; hereinafter “Maru”).
In re claims 1 and 13, Maru discloses a power stage control circuit applied to a buck voltage converter (Fig. 1), wherein the voltage converter comprises a power stage (Fig. 1), the power stage comprises a first switch and a second switch (102 and 104 respectively), the first switch and the second switch are connected in series between an input voltage and a first reference voltage (VBAT and GND respectively), the input voltage is higher than the first reference voltage (i.e., VBAT is positive as GND is understood to be zero), and the power stage control circuit comprises:
a current sensing circuit, arranged to sense a current associated with the first switch, and convert the current into a sensing voltage (current sense circuit 114 senses current through switch 102 and outputs sense voltage to 116, 126);
a control circuit (118, 112, 110, 134, 136, 128, 130, 132), arranged to perform multiple first logical operations according to the sensing voltage (from 114), a second switch driving signal (driving signal to low-side switch 104, which drives discharge current through inductor 106 for zero current detection via 132), a zero crossing detection voltage (output of 132), a compensation voltage (IPK), and a second reference voltage (MAX current limit), in order to generate a modulation signal (output of 128) and a determination signal (112), for controlling turn-on and turn-off of the first switch and the second switch ([0031]) and dynamically setting an inductor peak current of an inductor (see [0042] and Fig. 5B), respectively, wherein the inductor (L 106) has a first terminal coupled between the first switch and the second switch (node Y), and a second terminal coupled to an output pin providing an output voltage (VOUT); and
a driving circuit (120), arranged to perform multiple second logical operations according to the modulation signal and the determination signal in order to generate a first switch driving signal and the second switch driving signal, for driving the first switch and the second switch, respectively (driver 120 produces gate signals to 102, 104 based on signals produced by control circuit; see [0024]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maru.
In re claim 2, Maru discloses the invention according to claim 1 as explained above, and further discloses an error amplifier (108), arranged to receive a feedback voltage (VOUT) and a third reference voltage (Vsetpoint) in order to generate an error amplifier voltage (output of 108); and a slope compensation voltage (SLOPE COMPENSATION at 116).
Maru disclosing adding a slope compensation voltage to the current sensing voltage (at 116), in contrast to the claim, which recites a subtraction circuit, arranged to subtract a slope compensation voltage from the error amplifier voltage in order to generate the compensation voltage. However, it was known and routine in the art that when modifying one of the inputs to a comparator, either of the inputs could be alternatively and inversely modified with the same result achieved. That is, subtracting slope compensation from the error amplifier voltage would be readily seen as equivalent to adding such to the current sensing voltage when generating the inputs to comparator 112 in Maru. Thus, faced with the choice between these two equivalent design choices, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to try the alternative of subtracting the slope compensation voltage from the error amplifier output, for the purpose of preventing subharmonic oscillation of the inductor current due to current mode control.
Allowable Subject Matter
Claims 3-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, the closest prior art in Maru discloses the invention according to claim 1 as explained above, but does not further disclose wherein the inductor peak current of the inductor is dynamically set according to a reference current, the determination signal, and the compensation voltage; and the reference current is a product of a conductance of the current sensing circuit and the second reference voltage. Rather, Maru discloses dynamically controlling the peak inductor current “based on one or more of a duration between trips of output comparator 128, duration of time output comparator 128 is tripped, duration of time output comparator 128 is untripped, a difference between output voltage VOUT and setpoint voltage Vsetpoint, and a fixed-predetermined value” ([0042]).
Furthermore, the additional prior art on record does not disclose the claimed feature, and there is therefore no obvious suggestion to modify Maru in a manner that could have arrived at the claimed solution.
Claims 4-7 each depend from claim 3 and would therefore be allowable for the same reasons as stated above.
With respect to claim 8, the closest prior art in Maru discloses the invention according to claim 1 as explained above, but does not further disclose wherein the control circuit comprises: a discontinuous conduction mode (DCM) detection circuit, comprising: a pulse generator, arranged to receive the second switch driving signal from the driving circuit, and generate a pulse signal according to the second switch driving signal; a first AND gate circuit, arranged to perform an AND operation upon an inverse of the pulse signal and the zero crossing detection voltage in order to generate a first AND gate output; and a set-reset (SR) latch circuit, having a reset input terminal, a set input terminal, and an output terminal, wherein the reset input terminal receives the pulse signal, the set input terminal receives the first AND gate output, and a DCM detection signal is generated at the output terminal for determining whether an inductor current of the voltage converter operates in a DCM. Rather, Maru discloses controlling the converter in DCM via the PFM control circuitry including PFM entry logic and controller 118 in Fig. 1.
Furthermore, the additional prior art on record does not disclose the claimed feature, and there is therefore no obvious suggestion to modify Maru in a manner that could have arrived at the claimed solution.
Claims 9-10 each depend, either directly or indirectly, from claim 8 and would therefore be allowable for the same reasons as stated above.
With respect to claim 11, the closest prior art in Maru discloses the invention according to claim 1 as explained above, but does not further disclose wherein a reference current is a product of a conductance of the current sensing circuit and the second reference voltage; and when an inductor current of the voltage converter operates in a discontinuous conduction mode (DCM), the inductor peak current of the inductor is set to be greater than or equal to the reference current. Rather, Maru discloses dynamically controlling the peak inductor current “based on one or more of a duration between trips of output comparator 128, duration of time output comparator 128 is tripped, duration of time output comparator 128 is untripped, a difference between output voltage VOUT and setpoint voltage Vsetpoint, and a fixed-predetermined value” ([0042]).
With respect to claim 12, the closest prior art in Maru discloses the invention according to claim 1 as explained above, but does not further disclose wherein a reference current is a product of a conductance of the current sensing circuit and the second reference voltage; and when an inductor current of the voltage converter operates in a discontinuous conduction mode (DCM), and the inductor peak current of the inductor is equal to the reference current, a next charging cycle of the power stage is performed only after an inductor current of the inductor is discharged to zero. Rather, Maru discloses dynamically controlling the peak inductor current “based on one or more of a duration between trips of output comparator 128, duration of time output comparator 128 is tripped, duration of time output comparator 128 is untripped, a difference between output voltage VOUT and setpoint voltage Vsetpoint, and a fixed-predetermined value” ([0042]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2011/0309815 discloses a POWER CONVERTER AND METHOD OF POWER CONVERSION in which a driving circuit compensates for an inductor peak current, and performs in a pulse-frequency-modulation (PFM) mode and a pulse-width-modulation (PWM) mode to generate the pull-up driving signal and the pull-down driving signal based on the DC output voltage and the compensated inductor peak current
US 2015/0214827 discloses a VOLTAGE CONVERTER AND POWER MANAGEMENT DEVICE INCLUDING THE SAME, comprising a driving device unit, a current sensing unit and a switching control circuit, the switching control circuit generates the first and second driving control signals by performing a pulse-frequency modulation (PFM) and a pulse-width modulation (PWM) based on a feedback voltage, a reference voltage and the first and second sensing signals.
US 2016/0322900 discloses a SWITCHING CONVERTER WITH ACCURATE ZERO CURRENT DETECTION AND CONTROL METHOD THEREOF including adjusting an offset signal in accordance with the on-time of the body diode in the second switch; comparing the current flowing through the tank element with the offset signal; and turning off the second switch if the current flowing through the tank element is detected to be lower than the offset signal.
US 2026/0142569 discloses a CONTROLLER FOR SWITCHING CONVERTER configured to drive a switching operation of the one or more power switches to provide a magnetization phase where an inductor current flowing through the inductor increases to a peak current value that is dependent on the load current, and a demagnetization phase where the inductor current decreases from the peak current value.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
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