Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 26, 2024 and June 20, 2025 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Claims 5-8 and 10-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on April 24, 2026.
Claim Rejections - 35 USC § 102
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Sharma (US 7710164 B1); hereinafter Sharma.
Regarding Claim 1, Sharma discloses a bootstrapped switch [Fig. 1] comprising: a first transistor [M1], comprising: a first connection terminal [M1-source], arranged to receive an input voltage [VIN] of the bootstrapped switch, wherein the input voltage is a static bias voltage [constant voltage VIN that changes with time per Fig. 3]; a second connection terminal [M1-drain], arranged to generate an output voltage [VOUT] of the bootstrapped switch; and a control terminal [M1-gate]; a capacitor [C1], comprising: a first end [N2], coupled to the control terminal of the first transistor; and a second end [N1]; a first voltage providing circuit [S1/S2], coupled to the second end of the capacitor, wherein the first voltage providing circuit is arranged to provide a first voltage [GND] to the second end of the capacitor during a first period in which the first transistor is turned off [Fig. 2A], and provide a second voltage [VIN] to the second end of the capacitor during a second period in which the first transistor is turned on [Fig. 2B], where the second voltage is different from the first voltage; a second voltage providing circuit [S3/S4], coupled to the control terminal of the first transistor, wherein the second voltage providing circuit is arranged to provide a boost voltage [VIN+VCC; column 4, lines 7-14] to the control terminal of the first transistor during the first period in which the first transistor is turned off, and stop providing the boost voltage to the control terminal of the first transistor during the second period in which the first transistor is turned on [Fig. 2B/3].
Regarding Claim 2, Sharma discloses the bootstrapped switch of claim 1, wherein the first transistor is an N-type transistor [column 5, line 56].
Regarding Claim 3, Sharma discloses the bootstrapped switch of claim 2, wherein the boost voltage is set by the static bias voltage [as shown in claim 1 above, the static bias voltage is the input voltage; and as shown in claim 2, the boost voltage is VIN+VCC; therefore, the input voltage sets the boost voltage].
Claims 1-3 and 9 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Singer et al. (US 6060937 A); hereinafter Singer.
Regarding Claim 1, Singer discloses a bootstrapped switch [Fig. 6] comprising: a first transistor [M1], comprising: a first connection terminal [M1-source], arranged to receive an input voltage [Vin] of the bootstrapped switch, wherein the input voltage is a static bias voltage [column 6, lines 22-39]; a second connection terminal [M1-drain], arranged to generate an output voltage [Vout] of the bootstrapped switch; and a control terminal [M1-gate]; a capacitor [Cboot], comprising: a first end [N1], coupled to the control terminal of the first transistor; and a second end [N2]; a first voltage providing circuit [S2/S3], coupled to the second end of the capacitor, wherein the first voltage providing circuit is arranged to provide a first voltage [V--] to the second end of the capacitor during a first period in which the first transistor is turned off [column 6, lines 1-10], and provide a second voltage [V++] to the second end of the capacitor during a second period in which the first transistor is turned on [column 6, lines 1-10], where the second voltage is different from the first voltage [column 8, lines 48-61]; a second voltage providing circuit [M2/M3/M4], coupled to the control terminal of the first transistor, wherein the second voltage providing circuit is arranged to provide a boost voltage [column 10, lines 20-30] to the control terminal of the first transistor during the first period in which the first transistor is turned off, and stop providing the boost voltage to the control terminal of the first transistor during the second period in which the first transistor is turned on.
Regarding Claim 2, Singer discloses the bootstrapped switch of claim 1, wherein the first transistor is an N-type transistor [column 6, lines 15-16].
Regarding Claim 3, Singer discloses the bootstrapped switch of claim 2, wherein the boost voltage is set by the static bias voltage [column 10, lines 20-30].
Regarding Claim 9, Singer discloses the bootstrapped switch of claim 2, wherein the first voltage providing circuit comprises: an inverter circuit [S3/S2], comprising: a second transistor [S3], comprising: a first connection terminal [S3-source], arranged to receive the second voltage; a second connection terminal [S3-drain], coupled to the second end of the capacitor; and a control terminal [S3-gate], arranged to receive a clock signal [phi-1'B]; and a third transistor [S2], comprising: a first connection terminal [S2-source], arranged to receive the first voltage; a second connection terminal [S2-drain], coupled to the second end of the capacitor; and a control terminal [S2-gate], arranged to receive the clock signal.
Claim Rejections - 35 USC § 103
Applicant is reminded that claim mapping is provided as a courtesy to the applicant, but applicant should consider a reference as a whole, as the entire reference gives context to mapped sections.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Singer, in view of Chou et al. (US 20070052452 A1); hereinafter Singer, in view of Chou.
Regarding Claim 18, Singer discloses the bootstrapped switch of claim 1 [see Claim 1 rejection, above]. Singer does not explicitly disclose a sample-and-hold circuit comprising the bootstrapped switch.
However, Chou discloses a sample-and-hold circuit [Fig. 5A; paragraphs 0019-0020] comprising a bootstrapped switch [Fig. 6, 610; paragraph 0021]. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to use the invention of Chou in the invention of Singer, with the expected benefit of improving linearity and reducing distortion. This method of improving Singer using Chou was within the ordinary ability of one of ordinary skill in the art before the effective filing date of the claimed invention based on the teachings of Chou. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Singer and Chou to obtain the invention: incorporating the bootstrapped switch within the sample-and-hold circuit.
Allowable Subject Matter
Claim 4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding Claim 4, Singer et al. (US 6060937 A) discloses the bootstrapped switch of claim 3, wherein the second voltage providing circuit comprises: an inverter circuit [M3/M4], comprising: a second transistor [M3], comprising: a first connection terminal [M3-source], arranged to receive the second voltage; a second connection terminal [M3-drain]; and a control terminal [M3-gate], arranged to receive a clock signal [phi-2B]; a third transistor [M4], comprising: a first connection terminal [M4-drain]; a second connection terminal [M4-source]; and a control terminal [M4-gate], arranged to receive the clock signal; and a fourth transistor [M2], comprising: a first connection terminal [M2-drain]. The prior art of record does not disclose nor render obvious a first connection terminal of the third transistor [M4-drain], arranged to receive the static bias voltage; a first connection terminal of a fourth transistor [M2-drain], arranged to receive the static bias voltage; a second connection terminal of the fourth transistor, coupled to the control terminal of the first transistor; and a control terminal of the fourth transistor, coupled to the second connection terminal of the second transistor and the second connection terminal of the third transistor.
Conclusion
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/Amit R Bhatia/Examiner, Art Unit 2836
/REGIS J BETSCH/SPE, Art Unit 2836
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