DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/30/2025, 7/17/2025 and 12/23/2024 were filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1: Claim(s) 1-3, 5-7, 9, 10, 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over USPN 10,412,327 B2 Takahashi in view of US 2021/0029321 A1 MA et al.
2: As for Claim 1, Takahashi depicts in Figures 1, 3 and 6 and teaches on Column 12, Lines 21-62 and Column 13, Lines 11-63 An image capturing device comprising: a pixel chip (10) having a plurality of pixel blocks (11) each including one or more pixels (Column 3, Lines 24-31); and a signal processing chip (20) having a first control block including a first converting unit (70 for single pixel) configured to convert a signal from a pixel (12) included in at least a first pixel block among the plurality of pixel blocks into a digital signal (ADC), and a first storage unit (71) configured to store the digital signal converted in the first converting unit (72 and 73), and a second control block arranged next to the first control block in a column direction (MxN signal processing sections 21) (Column 13, Lines 13-18) and including a second converting unit (22) configured to convert a signal from a pixel included in at least a second pixel block (12) among the plurality of pixel blocks into a digital signal (ADC), and a second storage unit (71 in different MxN location) configured to store the digital signal converted in the second converting unit. Takahashi teaches a stacked chip architecture having a pixel chip 10 stocked on a signal processing chip 20. Takahashi teaches in Column 14, Lines 18-30 the chips are connected using vias (24) and that the vias on chips 10 and 20 will be aligned with each other. Furthermore, Takahashi depicts in Figure 6 a layout for the signal processing sections 21 in a matrix array wherein all the signal processing sections 21 are arranged in the same orientation. However, Takahashi further teaches on Column 11, Lines 22-30 that different wiring schemes can be adopted. However, does not explicitly teach a wiring scheme wherein the second converting unit and the second storage unit in the second control block are arranged at positions reversed vertically with respect to arrangement positions of the first converting unit and the first storage unit in the first control block.
MA et al depicts in Figures 1, 7D, 7C and 9D and teaches in Paragraphs [0107- 0109] a stacked pixel structure that uses a quad pixel structure where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other (see Figure 7D) MA et al teaches this arrangement is advantageous because it can simplify the wiring structure and allow for shared readout and control circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the pixels in the pixel array (12) of Takahashi in a quad pixel arrangement as taught in Figure 7D of MA et al where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other and therefore, also orient the corresponding signal processing sections (21) in the same arrangement wherein the second converting unit and the second storage unit in the second control block are arranged at positions reversed vertically with respect to arrangement positions of the first converting unit and the first storage unit in the first control block in order to align the vias (24) to correspond to the new locations of the corresponding terminals of the pixel structure in order to simplify the wiring structure and allow for shared readout and control circuitry.
3: As for Claim 2, Takahashi depicts in Figures 1, 3 and 6 and teaches on Column 12, Lines 21-62 and Column 13, Lines 11-63 wherein the first control block (1X1 location in 21 depicted in Figure 6) has a first exposure control unit for controlling an exposure time of a pixel included in the first pixel block (12), the second control block (MxN array of circuits including 24) has a second exposure control unit for controlling an exposure time of a pixel included in the second pixel block, and the second converting unit. Furthermore, as discussed in Claim 1, the combination with MA et al having a quad pixel arrangement in Figure 7D of MA et al where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other and therefore, also orient the corresponding signal processing sections (21) in the same arrangement this will result in
the second storage unit (71) and the second exposure control unit in the second control block to be arranged at positions reversed vertically with respect to arrangement positions of the first converting unit, the first storage unit and the first exposure control unit in the first control block.
4: As for Claim 3, Takahashi depicts in Figures 1, 3 and 6 and teaches on Column 12, Lines 21-62 and Column 13, Lines 11-63 wherein the first control block (1X1 location in 21 depicted in Figure 6) has a first pixel drive unit for driving a pixel included in the first pixel block, the second control block (MxN array of circuits including 24) has a second pixel drive unit for driving a pixel included in the second pixel block. Furthermore, as discussed in Claim 1, the combination with MA et al having a quad pixel arrangement in Figure 7D of MA et al where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other and therefore, also orient the corresponding signal processing sections (21) in the same arrangement this will result in the second converting unit, the second storage unit (71), the second exposure control unit and the second pixel drive unit in the second control block to be arranged at positions reversed vertically with respect to arrangement positions of the first converting unit, the first storage unit, the first exposure control unit and the first pixel drive unit in the first control block.
5: As for Claim 5, Takahashi depicts in Figures 1, 3 and 6 and teaches on Column 12, Lines 21-62 and Column 13, Lines 11-63 wherein the signal processing chip (20) has a third control block (1x2 circuit including 24) arranged next to the first control block (1X1) in a row direction and including a third converting unit configured to convert a signal from a pixel (12) included in at least a third pixel block among the plurality of pixels into a digital signal (ADC), and a third storage unit (71) configured to store the digital signal converted in the third converting unit. Furthermore, as discussed in Claim 1, the combination with MA et al having a quad pixel arrangement in Figure 7D of MA et al where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other and therefore, also orient the corresponding signal processing sections (21) in the same arrangement this will result in the third converting unit and the third storage unit in the third control block to be arranged at positions reversed horizontally with respect to the arrangement positions of the first converting unit and the first storage unit in the first control block.
6: As for Claim 6, Takahashi depicts in Figures 1, 3 and 6 and teaches on Column 12, Lines 21-62 and Column 13, Lines 11-63 wherein the first control block (1x1) has a first exposure control unit for controlling an exposure time of a pixel included in the first pixel block, the second control block (2x1) has a second exposure control unit for controlling an exposure time of a pixel included in the second pixel block, the third control block (1x2) has a third exposure control unit for controlling an exposure time of a pixel included in the third pixel block. Furthermore, as discussed in Claim 1, the combination with MA et al having a quad pixel arrangement in Figure 7D of MA et al where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other and therefore, also orient the corresponding signal processing sections (21) in the same arrangement this will result in the second converting unit, the second storage unit and the second exposure control unit in the second control block (2x1) are arranged at positions reversed vertically with respect to arrangement positions of the first converting unit, the first storage unit and the first exposure control unit in the first control block (1x1) , and the third converting unit, the third storage unit and the third exposure control unit in the third control block (1x2) are arranged at positions reversed horizontally with respect to arrangement positions of the first converting unit, the first storage unit and the first exposure control unit in the first control block (1x1).
7: As for Claim 7, Takahashi depicts in Figures 1, 3 and 6 and teaches on Column 12, Lines 21-62 and Column 13, Lines 11-63 wherein the first control block (1x1) has a first pixel drive unit for driving a pixel included in the first pixel block, the second control block (2x1) has a second pixel drive unit for driving a pixel included in the second pixel block, the third control block (1x2) has a third pixel drive unit for driving a pixel included in the third pixel block. Furthermore, as discussed in Claim 1, the combination with MA et al having a quad pixel arrangement in Figure 7D of MA et al where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other and therefore, also orient the corresponding signal processing sections (21) in the same arrangement this will result in the second converting unit, the second storage unit, the second exposure control unit and the second pixel drive unit in the second control block (2x1) are arranged at positions reversed vertically with respect to arrangement positions of the first converting unit, the first storage unit, the first exposure control unit and the first pixel drive unit in the first control block (1x1), and the third converting unit, the third storage unit, the third exposure control unit and the third pixel drive unit in the third control block (1x2) are arranged at positions reversed horizontally with respect to arrangement positions of the first converting unit, the first storage unit, the first exposure control unit and the first pixel drive unit in the first control block (1x1).
8: As for Claim 9, Takahashi depicts in Figures 1, 3 and 6 and teaches on Column 12, Lines 21-62 and Column 13, Lines 11-63 An image capturing device comprising: a pixel chip (10) having a plurality of pixel blocks (11) each including one or more pixels; and a signal processing chip (20) having a first control block including a first converting unit (70 for single pixel) configured to convert a signal from a pixel included in at least a first pixel block among the plurality of pixel blocks into a digital signal (ADC), a first storage unit (71) configured to store the digital signal converted in the first converting unit (72 and 73), and a first exposure control unit for controlling an exposure time of a pixel included in the first pixel block (Column 9, Lines 20-23), and a second control block (MxN array of blocks 21) arranged next to the first control block in a row direction and including a second converting unit (70) configured to convert a signal from a pixel included in at least a second pixel block among the plurality of pixel blocks into a digital signal (ADC), a second storage unit (71) configured to store the digital signal converted in the second converting unit, and a second exposure control unit for controlling an exposure time of a pixel included in the second pixel block (MxN array). Furthermore, Takahashi depicts in Figure 6 a layout for the signal processing sections 21 in a matrix array wherein all the signal processing sections 21 are arranged in the same orientation. However, Takahashi further teaches on Column 11, Lines 22-30 that different wiring schemes can be adopted. However, does not explicitly teach a wiring scheme wherein the second converting unit and the second storage unit in the second control block are arranged at positions reversed horizontally with respect to arrangement positions of the first converting unit and the first storage unit in the first control block.
MA et al depicts in Figures 1, 7D, 7C and 9D and teaches in Paragraphs [0107- 0109] a stacked pixel structure that uses a quad pixel structure where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other (see Figure 7D) MA et al teaches this arrangement is advantageous because it can simplify the wiring structure and allow for shared readout and control circuitry.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to arrange the pixels in the pixel array (12) of Takahashi in a quad pixel arrangement as taught in Figure 7D of MA et al where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other and therefore, also orient the corresponding signal processing sections (21) in the same arrangement wherein the second converting unit and the second storage unit in the second control block are arranged at positions reversed vertically with respect to arrangement positions of the first converting unit and the first storage unit in the first control block in order to align the vias (24) to correspond to the new locations of the corresponding terminals of the pixel structure in order to simplify the wiring structure and allow for shared readout and control circuitry.
9: As for Claim 10, Takahashi depicts in Figures 1, 3 and 6 and teaches on Column 12, Lines 21-62 and Column 13, Lines 11-63 wherein the first control block (1x1) has a first pixel drive unit for driving a pixel included in the first pixel block, the second control block (2x1) has a second pixel drive unit for driving a pixel included in the second pixel block. Furthermore, as discussed in Claim 1, the combination with MA et al having a quad pixel arrangement in Figure 7D of MA et al where four pixels are arranged with the same structure but are arranged at position reversed vertically and horizontally with respect to each other and therefore, also orient the corresponding signal processing sections (21) in the same arrangement this will result in the second converting unit, the second storage unit, the second exposure control unit and the second pixel drive unit in the second control block (2x1) are arranged at positions reversed horizontally with respect to arrangement positions of the first converting unit, the first storage unit, the first exposure control unit and the first pixel drive unit in the first control block (1x1).
10: As for Claim 12, Takahashi further teaches In Figure 2 wherein the pixel has a photoelectric converting unit (31) configured to convert light into electric charges, a transfer unit (32) configured to transfer the electric charges of the photoelectric converting unit (31), an accumulating unit (36) configured to accumulate the electric charges transferred by the transfer unit (32), and a reset unit (33) configured to discharge the electric charges of the accumulating unit (36).
11: As for Claim 13, Takahashi further teaches on Column 16, Lines 8-11 An image capturing apparatus comprising the image capture device according to claim 1.
12: Claim(s) 4, 8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over USPN 10,412,327 B2 Takahashi in view of US 2021/0029321 A1 MA et al further in view of USPN 7,128,270 B2 Silverbrook et al.
13: As for Claim 4, Takahashi in view of MA et al teaches as discussed in Claim 1 the second converting unit, the second storage unit, the second exposure control unit, the second pixel drive unit in the second control block (2x1) are arranged at positions reversed vertically with respect to arrangement positions of the first converting unit, the first storage unit, the first exposure control unit, the first pixel drive unit and the first control block (1x1). However, does not teach each control block has a level shifter.
Silverbrook et al teaches on Column 92, Lines 11-29 that it was advantageous when using buffers in imaging circuitry to use level shifter buffers in order to translate the logic levels by using basic feedback circuitry in order to avoid any potential latch-up during fast transitions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use level shift buffers as taught by Silverbrook et al for the buffers of Takahashi in view of MA et al in order to avoid any potential latch-up during fast transitions.
14: As for Claim 8, Takahashi in view of MA et al teaches as discussed in Claim 1 the second converting unit, the second storage unit, the second exposure control unit, the second pixel drive unit in the second control block (2x1) are arranged at positions reversed vertically with respect to arrangement positions of the first converting unit, the first storage unit, the first exposure control unit, the first pixel drive unit in the first control block (1x1), and the third converting unit, the third storage unit, the third exposure control unit, the third pixel drive unit in the third control block (1x2) are arranged at positions reversed horizontally with respect to arrangement positions of the first converting unit, the first storage unit, the first exposure control unit, the first pixel drive unit in the first control block (1x1). However, does not teach each control block has a level shifter.
Silverbrook et al teaches on Column 92, Lines 11-29 that it was advantageous when using buffers in imaging circuitry to use level shifter buffers in order to translate the logic levels by using basic feedback circuitry in order to avoid any potential latch-up during fast transitions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use level shift buffers as taught by Silverbrook et al for the buffers of Takahashi in view of MA et al in order to avoid any potential latch-up during fast transitions.
15: As for Claim 11, Takahashi in view of MA et al teaches as discussed in Claim 9 the second converting unit, the second storage unit, the second exposure control unit, the second pixel drive unit in the second control block (2x1) are arranged at positions reversed vertically with respect to arrangement positions of the first converting unit, the first storage unit, the first exposure control unit, the first pixel drive unit and the first control block (1x1). However, does not teach each control block has a level shifter
Silverbrook et al teaches on Column 92, Lines 11-29 that it was advantageous when using buffers in imaging circuitry to use level shifter buffers in order to translate the logic levels by using basic feedback circuitry in order to avoid any potential latch-up during fast transitions.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use level shift buffers as taught by Silverbrook et al for the buffers of Takahashi in view of MA et al in order to avoid any potential latch-up during fast transitions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES M HANNETT whose telephone number is (571)272-7309. The examiner can normally be reached 8:00 AM-5:00 PM Monday thru Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at 571-272-7406 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES M HANNETT/Primary Examiner, Art Unit 2639
JMH
February 11, 2026