Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Objections
Claims 1-17 are objected to because of the following informalities: in claims 1, 3-4, 7-8, 10-12, 14, and 16-17, “/ resistance” should be changed to “and resistance”.
Other dependent claims are objected for at least the reasons of including the above discussed deficiencies by the way of their claim dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 and 12-13 rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0256493 to Saito (cited in an IDS).
With respect to claim 1, Saito discloses in Fig. 2 a power semiconductor device comprising:
a power semiconductor die forming a power switch and comprising an input pad, an output pad, and a control pad (e.g., 2, 4, and 3, respectively) (e.g., 2-4 and insulated gate bipolar transistor (IGBT) 1 may be formed on a semiconductor die having pads for 2-4 as described below);
a collector power terminal (e.g., 2) coupled to the input pad (e.g., 2) of the power switch;
an auxiliary gate terminal (e.g., 3) coupled to the control pad (e.g., 3) of the power switch;
an emitter power terminal (e.g., 4);
two or more inductance and resistance pairs, wherein each inductance and resistance pair comprises a common stray inductance and a resistance that are arranged in series (e.g., each conductor/wiring of 8 and 9 comprises series connected parasitic inductance and resistance as discussed below) between the output pad (e.g., 4) of the power switch and the emitter power terminal (e.g., the emitter of 1); and
a plurality of auxiliary emitter terminals (e.g., 6 and 7), wherein the auxiliary emitter terminals (e.g., 6 and 7) are coupled to both sides of the inductance and resistance pairs (e.g., each conductor/wiring of 8 and 9 comprises series connected parasitic inductance and resistance as discussed below) so that one auxiliary emitter terminal (e.g., 6) is coupled to one side of one inductance/resistance pair (e.g., 9 and the respective resistance). In Saito, the wiring/conductor section for each of parasitic inductance 8 and 9 also includes series connected parasitic impedance. For example, US 2017/0248646 to Mauder et al. (“Mauder”) (cited in an IDS) discloses in Fig. 6 and Para. 60 an electric connection/wiring has series connected parasitic inductance and parasitic resistance. Saito fails to disclose that terminals 2-4 and insulated gate bipolar transistor (IGBT) 1 in Fig. 2 are formed on a semiconductor die and the die has pads for terminals 2-4. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that (1) a transistor including terminals may be formed on a semiconductor die and (2) terminals of a circuit may be formed of pads; an official notice of the foregoing fact is hereby taken. For example, US 8,890,596 to Chen discloses in Fig. 1 that a pad may be used for a terminal of an integrated circuit. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to (1) form terminals 2-4 and insulated gate bipolar transistor (IGBT) 1 in Fig. 2 of Saito on a semiconductor die in light of the notoriously well-known teaching of forming a transistor and terminals on a die because such a modification saves space/costs and (2) form terminals 2-4 in Fig. 2 of Saito as pads in light of the notoriously well-known teaching of forming terminals as pads because the formation of terminals 2-4 in Fig. 2 of Saito requires a specific implementation in fabrication and the notoriously well-known teaching of forming terminals as pads provides such a specific implementation.
With respect to claim 2, Saito fails to explicitly disclose that the wirings/conductors for 8 and 9 (including the common stray inductance and the resistance as discussed for claim 1) are formed by wire bonds and/or substrate copper tracks. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that wirings/conductors may be formed of wire bonds and/or substrate copper tracks; an official notice of the foregoing fact is hereby taken. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form the wirings/conductors for 8 and 9 in Fig. 2 of Saito using the notoriously well-known method because the formation of the wirings/conductors for 8 and 9 in Fig. 2 of Saito requires a specific implementation in fabrication and the notoriously well-known teaching provides such a specific implementation.
With respect to claims 3-4, as to the feature that the common stray inductance has a first inductance value that is the same or different in different inductance/resistance pairs, such specific parameters will not support the patentability of the subject matter encompassed by the prior art unless there is evidence indicating the parameters are critical. Absent any evidence demonstrating a patentable difference between the compositions and the criticality of the claimed amounts, the determination of the optimum or workable range(s) given the guidance of the prior art would have been generally prima facie obvious to the skilled artisan. Please see MPEP §2144.05 [R-2](II)(A) and In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) ("[W]here the general conditions of claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation."). It is noted that the specification contains no disclosure of either the critical nature of the instant parameters or any unexpected results arising thereof. Since applicant has not established the criticality of the specific parameters, it would have been obvious to one of ordinary skill in the art before the filing of the claimed invention to use these values in the Fig. 2 circuit of Saito.
With respect to claim 5, Saito discloses a plurality of power semiconductor dies forming a plurality of power switches (“The present application is applicable to a module such as an IPM (intelligent power module) on which a plurality of elements is placed”, wherein the said plurality of elements correspond to the claimed plurality of power switches).
With respect to claim 6, Saito fails to explicitly disclose a device package, wherein the collector power terminal, the auxiliary gate terminal, the emitter power terminal, and the plurality of auxiliary emitter terminals (e.g., 2-7 in Fig. 2) extend through the device package. However, it was notoriously well known to a person of ordinary skill in the art before the effective filing date of the claimed invention that (1) a package may be used to enclose a circuit with package in order to protect the circuit and provide an output and (2) terminals of the circuit may extend through the package; an official notice of the foregoing fact is hereby taken. For example, US 2017/0187372 to Perruchoud et al. discloses in Fig. 6 that (1) a packaging may be used to enclose an integrated circuit with the package in order to protect the integrated circuit and provide an output, and (2) input/output/supply terminals of the integrated circuit may be formed of package terminals. Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to (1) package IGBT 1 in Fig. 2 of Saito including terminals 2-7 and (2) provide input/output supply terminals 2-7 to extend through the package because (1) packaging of a circuit is notoriously well-known and provides protection to the circuit and (2) forming of input/output/supply terminals of the integrated circuit through the package is notoriously well-known and enables the packaged circuit to receive/output signals/voltages.
With respect to claims 7 and 12, the above discussion for claim 1 similarly applies.
With respect to claim 8, electronic switches 11-12 are shown.
With respect to claim 13, the control circuit 10 also includes a drive circuit for driving the gate of 1 as 1 needs a gate drive input.
Allowable Subject Matter
Claims 9-11 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jung KIM whose telephone number is (571)270-7964. The examiner can normally be reached on M-F from 9AM to 5:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Lincoln Donovan, can be reached at (571)272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUNG KIM/
Primary Examiner, Art Unit 2842