Prosecution Insights
Last updated: May 29, 2026
Application No. 18/960,101

MEMORY DEVICE, OPERATING METHOD OF MEMORY DEVICE, AND OPERATING METHOD OF HOST DEVICE FOR MEMORY DEVICE

Final Rejection §101§112
Filed
Nov 26, 2024
Priority
Nov 29, 2023 — RE 10-2023-0169556
Examiner
PETRANEK, JACOB ANDREW
Art Unit
2183
Tech Center
2100 — Computer Architecture & Software
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
Est. Remaining
88%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
609 granted / 765 resolved
+24.6% vs TC avg
Moderate +8% lift
Without
With
+8.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 9m
Avg Prosecution
23 currently pending
Career history
799
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
80.5%
+40.5% vs TC avg
§102
6.0%
-34.0% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 765 resolved cases

Office Action

§101 §112
DETAILED ACTION Claims 1-23 are pending. The office acknowledges the following papers: Claims, specification, and remarks filed on 2/25/2026. Allowable Subject Matter Claims 1-13, 19, and 21-23 are allowed. Withdrawn objections and rejections The specification objections have been withdrawn due to amendment. The 35 U.S.C. 112(b) rejection for claim 16 has been withdrawn due to amendment. New Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 14-18 and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without either reciting additional elements that integrate the judicial exception into a practical application or reciting additional elements that amount to significantly more than the judicial exception. Independent claims 14 and 20 recite a mental process of determining an operation of a target accelerator is for a different neural network layer than an operation for a previous accelerator and adjusting the operation. All of the claims are directed towards a process, machine manufacture, or a composition of matter. The determining an operation of a target accelerator is for a different neural network layer than an operation for a previous accelerator and adjusting the operation step is a process that, under its broadest reasonable interpretation, covers a mental process of the mind with the aid of pen and paper but for the recitation of generic computer components. This judicial exception is not integrated into a practical application. In particular, the claim only recites “a memory device” to perform the determining, adjusting, and performing steps. The “memory device” is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Therefore, this additional element doesn’t integrate the abstract idea into a practical application because it doesn’t impose any meaningful limits on practicing the abstract idea. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception, including the performing step. Thus, the claims are directed towards an abstract idea and aren’t patent eligible. Maintained Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 14-18 and 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. Claim 14 recites “adjusting the operation instruction for the different layer based on the determination.” Claim 20 recites a similar limitation. The state of the prior art shows that operations in different neural network layers is well-known. Additionally, it’s well-known that neural network operations can be processed on heterogeneous or homogeneous accelerators. However, the state of the prior art is non-existent regarding adjusting instruction operations when operations for a target accelerator are at a different layer than a previous accelerator for a previous operation. The broadest reasonable interpretation of the limitation is performing an adjustment of the operation instruction when the determining step is true. The level of one of ordinary skill in the art is well-aware of general types of neural network operations. However, one of ordinary skill in the art is not generally aware of the claimed adjusting step based on the determining step being true. The amount of direction provided by the applicant and inventors for implementing the adjusting step is non-existent. There are no working examples provided by the applicant and inventors for how adjusting the instruction is performing. Making the adjustment would require substantial work and experimentation to correctly use and make work. Such substantial work and experimentation at the very least includes: Determining what adjustment(s) is(are) actually needed when the determination step is true Selecting between potential adjustments is different use cases Testing out the adjustments while performing the layer operations. For all of these above reasons, the specification at the time of filing failed to teach one skilled in the art how to make and/or use adjusting the layer instruction without undue experimentation Claims 15-18 are rejected due to their dependency. Response to Arguments The arguments presented by Applicant in the response, received on 2/25/2026 are partially considered persuasive. Applicant argues regarding the 35 U.S.C. 112(a) rejections: “The Office Action, pages 4-6, rejected claims 14-18 and 20 under 35 U.S.C. § 112(a) as failing to comply with the enablement requirement. Particularly, the Office Action recites a limitation of claim 14 that teaches 'adjusting the operation instruction for the different layer based on the determination'. The Applicant has amended claim 14 and further submits the CXL is an open industry standard for controlling communication between CPUs, memories, and accelerator devices. Therefore, one skilled in the art would be aware of the implementation using the example of the CXL industry standard. See paragraph [0139]-[0144] of the present Application.” This argument is not found to be persuasive for the following reason. The examiner doesn’t disagree that CXL is an open industry standard or well-known. However, it’s unclear to the examiner how CXL provides enablement support for the claimed limitations that involve adjusting operations at different neural network layers. Thus, the enablement rejection is maintained. Applicant argues regarding the 35 U.S.C. 112(b) rejection: “Additionally, the Office Action rejected claim 16 under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Particularly, the Office Action recites limitation of claim 16 as being unclear regarding what adjusting the bit value is between. Applicant has amended claim 16 to provide clarity to the limitation.” This argument is found to be persuasive for the following reason. The examiner agrees that the indefiniteness issue has been addressed. Thus, the rejection has been withdrawn. Applicant argues regarding the 35 U.S.C. 101 rejection: “Steps of amended independent claim 14 cannot be performed in the human mind, or by a human using a pen and paper. Rather, the steps in claim 1 are directed at performing, using the memory device, an operation based on the adjusted operation instruction. For example, claim 1 involves a sophisticated process of adjusting an operation instruction for different layers of the neural network model using a memory device, that goes beyond being performed in the human mind. Additionally, performing an operation based on the adjusted operation instruction is a tangible result (i.e., significantly more than abstract idea). Further, the above steps do not fall under mental process grouping of abstract ideas because these steps rely on performing, using the memory device, an operation based on the adjusted operation instruction. The operation is performed on a layer of the neural network model and the results thereof are presented to the user. Applicant respectfully submits these steps recited in amended independent claim 14 are not a mental process that can be performed in the human mind. Therefore, these steps of amended claim 14 do not fall under the mental process grouping of abstract ideas.” This argument is not found to be persuasive for the following reason. The addition of the performing operations using the memory device isn’t sufficient to integrate the judicial exception into a practical application nor are sufficient to amount to significantly more than the judicial exception. In this instance, the memory device is generic circuitry recited at a high-level of generality that fails to integrate the abstract idea into a practical application. Thus, the 101 rejections still apply. Applicant argues regarding claims 1, 11, and 21: “The Office Action relies on Aga, page 7, to teach offloading PIM operations to the PIM component within the memory module. However, the Applicant respectfully submits that the present invention teaches that the first accelerator comprises a control unit that selects one of the second accelerators to perform an operation. Accordingly, the Office Action has not shown the prior art can be relied on to teach or suggest at least the cited portion of the amended independent claims. Aga merely teaches a near-memory processing unit 112 in the memory module 104, as shown in FIG. 1 and described in paragraph [0043], "processing-in-memory component 112 is an example of an accelerator or other near-memory compute unit utilized by the host 102 to offload performance of computations (e.g., computations that would otherwise be performed by the core 108 in a conventional computing device architecture)". Thus, as shown in FIG. 1, Aga teaches PIM 112 as an accelerator that performs a downcast and an upcast operation. See paragraph [0054]-[0056] of Aga. That is, Aga only teaches PIM 112 to perform said operations, but Aga does not teach or suggest that the accelerator includes a control unit that selects one of a second accelerator (i.e., different from the PIM component 112) from a set of second accelerators to perform a second operation. Moreover, the Office Action relies on Gladding, page 7, to teach a processor that offloads matrix multiplication instructions to a hardware accelerator. As shown in FIG. lA of Gladding, and described in paragraphs [0019]-[0022], "the memory 14 may be communicatively coupled to the processor 12 and the hardware accelerator 16 such that the processor 12 and the hardware accelerator 16 may store data in the memory 14 and retrieve data from the memory 14". Thus, Gladding also does not teach the two accelerators. FIG. lA of Gladding also shows that the hardware accelerator in Gladding is located outside the memory 14. That is, the Office Action has not shown that any of the prior art teaches the two accelerators in the memory device (i.e., corresponding to a first accelerator and a second accelerator in the present Application), much less the first accelerator that includes a control unit to select one of a second accelerator to perform an operation.” This argument is found to be persuasive for the following reason. The previous combination used two separate accelerators to receive offloaded operations from a host computer for processing. The combination failed to teach a control unit of the first accelerator to select a second accelerator. Additionally, the combination failed to teach selecting, at the first accelerator outside of memory, a target accelerator disposed within the memory. Thus, the combinations based on Aga and Gladding have been withdrawn. A hypothetical modification to the previous combination of Aga and Gladding could be made in such a way that reads upon the newly claimed limitations. This would require the host of Aga offloading all accelerator operations to the added accelerator of Gladding. The accelerator of Gladding would then be required to further offload PIM operations to the PIM accelerator of Aga. However, there is insufficient motivation to one of ordinary skill in the art to make such a modification in a way that reads upon the newly claimed limitations. Thus, such a combination against the amended independent claims hasn’t been made. An updated prior art search has been performed that hasn’t resulted in any additional prior art references being found that read upon the newly claimed limitations. Thus, these independent claim sets are in condition for allowance. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACOB PETRANEK/Primary Examiner, Art Unit 2183
Read full office action

Prosecution Timeline

Nov 26, 2024
Application Filed
Dec 09, 2025
Non-Final Rejection mailed — §101, §112
Dec 11, 2025
Interview Requested
Dec 19, 2025
Applicant Interview (Telephonic)
Dec 19, 2025
Examiner Interview Summary
Feb 25, 2026
Response Filed
May 15, 2026
Final Rejection mailed — §101, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
88%
With Interview (+8.5%)
3y 9m (~2y 3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 765 resolved cases by this examiner. Grant probability derived from career allowance rate.

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