DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103, which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-35 are rejected under 35 U.S.C. 103 as being unpatentable over US 20100099363 A1 (Faust), in view of US 20220050174 A1 (Goumballa) and in further view of US20050093729A1 (Lin)
Regarding Claims 16 and 34:
A device for self-calibrating a radiofrequency transmitter, comprising: first circuitry for receiving a reference phase value and configured to output a first analog signal based on the reference phase value (Faust: Fig. 1 and [0049]-[0050], "The transmitter, generally referenced 10, comprises a digital baseband (DBB) 12, an I path including: digital to analog converter (DAC) 18, low pass filter (LPF) 20, variable gain amplifier (VGA) 22, mixer 24 and LO.sub.I 26."; "the output (both I and Q signal outputs) of the digital IQ modulator (i.e. the digital baseband) is converted to an analog signal by the high rate DAC." The digital baseband generates calibration signals S₁–S₄ based on phase relationships between I and Q (Table 2, [0077]-[0078]), which constitute the reference phase value. The I-path DAC 18 receives these digital signals and outputs the first analog signal);
second circuitry for receiving the reference phase value and configured to output a second analog signal based on the reference phase value (Faust: Fig. 1 and [0049]-[0050], "a Q path including: DAC 28, LPF 30, VGA 32, mixer 34 and LOQ 36." ; "the output (both I and Q signal outputs) of the digital IQ modulator (i.e. the digital baseband) is converted to an analog signal by the high rate DAC." The Q-path DAC 28 receives the same calibration signal phase codes (reference phase value) and outputs the second analog signal);
an IQ modulator coupled to receive an input signal, the first analog signal and the second analog signal, and configured to provide an IQ modulator output signal based on the input signal, the first analog signal and the second analog signal (Faust: Fig. 1 and [0049]-[0050], "The transmitter, generally referenced 10, comprises a digital baseband (DBB) 12, an I path including: digital to analog converter (DAC) 18, low pass filter (LPF) 20, variable gain amplifier (VGA) 22, mixer 24 and LO.sub.I 26; a Q path including: DAC 28, LPF 30, VGA 32, mixer 34 and LOQ 36; a power amplifier (PA) 38 and power detector 39."; "The output of the VGA is upconverted to an RF frequency by a mixer… Once in the RF domain, the signal is amplified by the power amplifier (PA). A power detector (i.e. coupler) at the output of the power amplifier 'samples' part of the PA output to provide a power indication." Mixers 24 and 34 with LO inputs constitute the IQ modulator; LO_I/LO_Q is the input signal; the first and second analog signals are the I and Q baseband signals; the output of the mixers summed and amplified by the PA is the IQ modulator output signal); and
compensation control circuitry coupled to receive the IQ modulator output signal and configured, during calibration, to output at least one compensation signal indicative of a compensation value based on the IQ modulator output signal (Faust: Fig. 1 and [0049]-[0053], "a power amplifier (PA) 38 and power detector 39"; "A power detector (i.e. coupler) at the output of the power amplifier 'samples' part of the PA output to provide a power indication."; "The power detector functions to sample part of the output of the power amplifier and provides an indication of what the output power is. The power detector provides an analog signal which is filtered and sampled with an ADC to obtain a digital word that corresponds to the power level."; [0082]–[0083]: The gain mismatch estimate is updated according to the following expression, eq. (12); the power detector is equivalent to compensation control circuitry; it receives the IQ modulator output signal (the PA output); it outputs compensation signals (P₁–P₄ power detection signals and the resulting gain/phase mismatch estimate updates) that are indicative of the compensation values (gain mismatch α, phase mismatch φ));
wherein the first circuitry comprises: a digital signal generating portion for generating a digital signal based on the reference phase value and at least one the compensation value (Faust: [0049]: "The digital baseband 12 comprises a TX data predistortion block 14 and IQ calibration block 16." [0055]: "During the correction phase, the data to be transmitted is pre-distorted with the inverse of matrix {circumflex over (M)} (Equation 3) before being output of the digital baseband." [0085]: "The new IQ correction matrix M is then applied to the new signal to be transmitted (as shown in Equation 11 above) and the whole process repeats itself in iterative fashion until a stopping criterion is reached." The predistorted digital I signal is generated based on both the phase-coded calibration signal (i.e., reference phase value) and the updated correction matrix M (i.e., compensation value)),
a sigma-delta modulator portion coupled to receive the digital signal and configured, during calibration, for applying sigma-delta modulation to the digital signal (Faust does not teach explicitly on sigma-delta modulation, However, Goumballa explicitly discloses this limitation, e.g., [0043]: "The signal from the DDS 118 may be provided at the output of the digital controller 116 via a sigma-delta modulator 120."; [0047]: "In the voltage mode of operation, the output of the DDS 118 may be provided to the input of the phase shifter DAC via the sigma-delta modulator 120. The output of the phase shifter DAC 122 in the voltage mode is provided to the phase shifter 124 via a low pass filter 140 to remove out-of-band signals. The use of a sigma-delta (SD) modulator to drive the PSDAC 122 may increase the phase accuracy of the transmitted signals by increasing the effective number of bits of the PSDAC 122."; Fig. 3 and [0052]: "The digital controller 116 comprises the DDS 118 and a delta-sigma converter 120I, 120Q for the in-phase and quadrature components of the DDS outputs I, Q." The sigma-delta modulator 120 (120I for in-phase) is coupled to receive the DDS digital signal and applies sigma-delta modulation during calibration/BIST mode (voltage mode). The combination of Faust and Goumballa teaches this limitation, with Goumballa supplying the sigma-delta modulator portion);
It would have been obvious for one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify Faust with sigma-delta modulation as further taught by Goumballa. The advantage of doing so is to provide a mechanism for inserting a sigma-delta modulator before the I/Q DAC "may increase the phase accuracy of the transmitted signals by increasing the effective number of bits of the PSDAC" and that "the complexity of the PSDAC that is required can be reduced while still providing acceptable performance" (Goumballa [0047]).
and a digital-to-analog converter, coupled, during calibration, to receive the modulated digital signal provided by the sigma-delta modulator portion and configured to output the first analog signal (Goumballa: Fig. 3 and [0052]: "Outputs of the delta-sigma converters 120I, 120Q are provided to the PSDAC 122, having first and second paths comprising DACs 122I and 122Q."; [0047]: "The output of the phase shifter DAC 122 in the voltage mode is provided to the phase shifter 124 via a low pass filter 140 to remove out-of-band signals."; PSDAC 122I (i.e., DAC) receives the sigma-delta-modulated digital signal from delta-sigma converter 120I and outputs the first analog signal to the phase shifter (IQ modulator). This operates during voltage mode (i.e., calibration mode); Faust: [0050]: "the output (both I and Q signal outputs) of the digital IQ modulator (i.e. the digital baseband) is converted to an analog signal by the high rate DAC." DAC 18 in Faust converts the digital I signal to the first analog signal. The combination teaches a DAC receiving the sigma-delta-modulated signal during calibration and outputting the first analog signal).
Faust as modified does not teach explicitly on applying signal-delta modulator to both a 1st and a 2nd part, and summing the modulated the 1st and 2nd parts. However, Lin teaches (Lin: [0008]–[0009]: "the bits are divided into m most significant bits (MSB)… and (n-m) least significant bits (LSB)… The m most significant bits… are converted to thermometer code by a thermometer decoder… The value represented by the (n-m) LSB is always smaller than the value represented by the last bit of the MSB… the value represented by the (n-m) least significant bits can be calculated as a fraction of the 'whole' value of an element."; [0036]: "The present embodiment uses sigma delta (SD) dithering to solve this problem. SD dithering removes the frequency spurs associated with periodical dithering." The MSB drives the thermometer array (first part, unmodulated) and the LSB is sigma-delta-dithered (second part, modulated); their outputs are combined — a summing node — into the final analog output; claim 4: "… wherein dithering the unexercised element comprises performing sigma delta dithering."; claim 12: "A hybrid digital to analog converter (DAC) …a digital input node having an MSB output node and an LSB output node; a thermometer decoder coupled to the MSB output node… a thermometer element array coupled to the thermometer decoder; and a dithering circuit coupled to the LSB output node and at least one element in the thermometer element array." A POSITA would implement Goumballa's sigma-delta DAC using Lin's established MSB/LSB hybrid architecture, yielding a sigma-delta modulator on the second (LSB) part summed with the first (MSB) part).
Regarding Claim 17, Faust as modified further teaches:
The device according to claim 16, wherein the sigma-delta modulator portion comprises: a sigma-delta modulator configured to apply sigma-delta modulation to a second part of the digital signal; and a summing node for summing the modulated second part with a first part of the digital signal (Lin: [0008]-[0010], "the bits are divided into m most significant bits (MSB) named 4.sub.n-m through 4.sub.n and (n-m) least significant bits (LSB)"; Fig.2 and [0027], "Combining the value converted from the MSB and the value dithered from the fractional value of the LSB, the analog signal can be obtained.").
Regarding Claim 18, Faust as modified further teaches:
The device according to claim 17, wherein the first part is an integer part and the second part is a fractional part of the digital signal (Lin: Fig.2 and [0027], "the fraction value of the LSB is the value of LSB divided by 16. Digital input 0010,0011 has a fraction value of 3/16.").
Regarding Claim 19, Faust as modified further teaches:
The device according to claim 16, wherein the device is selectively configurable between: a calibration mode, in which the sigma delta modulator portion is enabled; and a transmission mode, in which the sigma delta modulator portion is disabled or bypassed (Goumballa: [0047]-[0048], "In the voltage mode of operation, the output of the DDS 118 may be provided to the input of the phase shifter DAC via the sigma-delta modulator 120,"; "During the normal mode of operation... the output of the DDS 118 is provided directly to the input of the phase shifter DAC 122").
Regarding Claim 20, Faust as modified further teaches:
The device according to claim 19, wherein, when the device is operating in the transmission mode, the digital signal generating portion is configured to generate the digital signal based on the reference phase value and the compensation value output by the compensation control circuitry during calibration (Faust: [0087], "the correction matrix M is applied to predistort transmit data in the digital baseband section 12 (FIG. 1) (step 160).")
Regarding Claim 21, Faust as modified further teaches:
The device according to claim 19, further comprising a power amplifier coupled to receive the IQ modulator output signal, the power amplifier being configured to amplify the IQ modulator output signal for output to an antenna (Faust: [0050], "the signal is amplified by the power amplifier (PA).").
Regarding Claim 22, Faust as modified further teaches:
The device according to claim 21, wherein, during the calibration mode, the power amplifier is disabled (Goumballa: 0049], "according to the selected mode (voltage or current), parts of the circuit are activated or deactivated"; [0057], "controller module 339 first enables the dummy load 240", which inherently bypasses normal RF amplification to the antenna during test mode).
Regarding Claim 23, Faust as modified further teaches:
The device according to claim 16, wherein the compensation control circuitry comprises a power meter coupled to receive the IQ modulator output signal and configured to output a power measurement signal indicative of the power of the IQ modulator output signal, and wherein the compensation value is determined by the compensation control circuitry based on the power measurement signal (Faust: [0053]-[0054], "The resulting analog signal is sampled by an ADC to generate a digital power word which is read and used by the calibration manager").
Regarding Claim 24, Faust as modified further teaches:
The device according to claim 23, wherein the compensation control circuitry comprises a low pass filter for removing high frequency noise from the power measurement signal (Faust: [0052], "The power detector block, generally referenced 50, comprises a squarer block 52, low pass filter block 54").
Regarding Claim 25, Faust as modified further teaches:
The device according to claim 16, wherein the compensation value corresponds to at least one of an amplitude adjustment, a phase offset and a DC offset of the digital signal (Faust: [0082]-[0083], "The gain mismatch estimate is updated according to the following expression: ... The phase mismatch estimate is updated according to the following expression:").
Regarding Claim 26, Faust as modified further teaches:
The device according to claim 16, wherein the compensation control circuitry is further configured to determine from the IQ modulator output signal a signal component path of the IQ modulator having the highest gain, and wherein the compensation value includes an amplitude adjustment of the digital signal corresponding to the signal component path having the highest gain (Faust: [0055], "estimate the gain and phase mismatch or imbalance between the I and Q paths". Balancing gain dictates applying amplitude adjustments to the path exhibiting the higher gain relative to the other).
Regarding Claim 27, Faust as modified further teaches:
The device according to claim 26, wherein the amplitude adjustment decreases the amplitude of the digital signal with respect to a predetermined initial amplitude (Faust: [0082], "The gain mismatch estimate is updated according to the following expression: a.sub.TX(n)=a.sub.TX(n-1)+.alpha.sign(P.sub.1-P.sub.2)". Iterative feedback inherently decreases mismatch errors relative to predetermined initial states).
Regarding Claim 28, Faust as modified further teaches:
The device according to claim 16, wherein the compensation value is stored by the first circuitry (Goumballa: [0022], "output and store a first digital code representing the measure of linearity").
Regarding Claim 29, Faust as modified further teaches:
The device according to claim 16, wherein the compensation control circuitry is configured to determine the compensation value based on the IQ modulator output signal by iteratively updating the respective compensation value (Faust: [0075], "The differences are used to update the mismatch estimates in an iterative process, i.e. a closed loop process or feedback scheme.").
Regarding Claim 30, Faust as modified further teaches:
The device according to claim 16, wherein the compensation control circuitry is configured to determine the compensation value based on the IQ modulator output signal by performing at least one respective binary search (Faust: [0083], "gear shifting wherein larger values of .alpha. and .beta. are used initially to quickly achieve convergence followed by use of smaller values". Modulating step sizes is a known equivalent to a binary search for resolving digital values).
Regarding Claim 31, Faust as modified further teaches:
A radiofrequency transmitter, comprising: the device according to claim 16; and a radiofrequency transmission antenna coupled to the output of the IQ modulator (Faust: [0050], "the signal is amplified by the power amplifier (PA)"; [0104], "The mobile device may comprise a plurality of RF transceivers 94 and associated antennas 98.").
Regarding Claim 32, Faust as modified further teaches:
The radiofrequency transmitter according to claim 31, wherein the radiofrequency transmitter is a radar transmitter (Goumballa: [0042], "radar device 100 comprises a radar transceiver with a receiver module 102 and a transmitter module 104.").
Regarding Claim 33, all limitations are taught by Claims 16 and 19-20. Therefore, Claim 31 is rejected for the same reasons as Claims 16 and 19-20.
Regarding Claim 35, Faust as modified further teaches:
A method according to claim 34, wherein the at least one compensation value comprises at least one of an amplitude adjustment, a phase offset and a dc offset of at least one of the first and second digital signals (Faust: [0082]-[0083], "The gain mismatch estimate is updated according to the following expression: ... The phase mismatch estimate is updated according to the following expression").
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHITONG CHEN whose telephone number is (571) 270-1936. The examiner can normally be reached on M-F 9:30am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yuwen Pan can be reached on 571-272-7855. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ZHITONG CHEN/
Primary Examiner, Art Unit 2649
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