Prosecution Insights
Last updated: April 18, 2026
Application No. 18/960,246

PROGRAMMABLE GATE DRIVER CIRCUIT FOR AN INTEGRATED POWER SWITCH

Non-Final OA §102
Filed
Nov 26, 2024
Examiner
COX, CASSANDRA F
Art Unit
2849
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies Austria AG
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
1y 11m
To Grant
97%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
784 granted / 831 resolved
+26.3% vs TC avg
Minimal +3% lift
Without
With
+3.0%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
8 currently pending
Career history
839
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
22.1%
-17.9% vs TC avg
§102
44.2%
+4.2% vs TC avg
§112
22.2%
-17.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 831 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1-2, 4, and 6-9 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Wang et al. (US 11,070,197). In reference to claim 1 Wang discloses in Figure 5 a gate driver circuit (502, 504) configured to drive a gallium nitride (GaN) transistor (508; column 9, lines 56-59), the gate driver circuit comprising a communication interface (560) configured to receive a gate driver parameter (see column 10, lines 31-52 where Wang discloses that the interface 560 queries the driver control logic 518 for measurements associated with the transistor 508), wherein the communication interface is n asynchronous serial communication interface (see column 10, lines 33-36). In reference to claim 2 Wang discloses in column 10, line 66 through column 12, line 25 that the communication interface 560 (as a part of controller 502) is configured to forward the received gate driver parameter to an external control circuit (as an alert signal indicating a need for repair/replacement of the transistor 508). In reference to claim 4 Wang discloses in column 2, line 61 through column 3, line 3 and column 10, line 39-44 that the gate driver parameter is a gate voltage parameter (VGS), and wherein the gate driver circuit is configured to generate a gate voltage for driving the GaN transistor (508) based on the gate voltage parameter (see column 12, line 58 through column 13, line 30). In reference to claim 6 Wang discloses in column 2, line 61 through column 3, line 3 and column 10, line 39-44 wherein the gate driver circuit is configured to determine a current value (IDS) indicative of a current flowing through the GaN transistor (508), and wherein the communication interface (560) is configured to transmit the current value to an external control circuit (see column 10, line 66 through column 12, line 25 wherein the communication interface 560 (as a part of controller 502) is configured to forward the received gate driver parameter (IDS) to an external control circuit (as an alert signal indicating a need for repair/replacement of the transistor 508). In reference to claim 7 Wang discloses in column 10, line 66 through column 12, line 25 wherein the gate driver circuit is configured to determine a fault condition (the alert signal indicating repair/replacement of the transistor (508) is needed) related to the GaN transistor (508) or to the gate driver circuit, and wherein the communication interface 560 (as a part of controller 502) is configured to transmit a signal indicative of the fault condition to an external control circuit (as an alert signal indicating a need for repair/replacement of the transistor 508). In reference to claim 8 Wang discloses in column 10, lines 33-36 that the communication interface (560) is a universal asynchronous receiver-transmitter UART interface. In reference to claim 9 Wang discloses in Figure 5 an integrated power switch comprising: the GaN transistor (508) as in claim 1, and the gate driver circuit (502, 504) according to claim 1, wherein the gate driver circuit is coupled to the gate of the GaN transistor (508). Allowable Subject Matter Claims 16-18 are allowed. Claims 3, 5, and 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CASSANDRA F COX whose telephone number is (571)272-1741. The examiner can normally be reached M-F 7:00-4:30; off alt Fridays. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at 571-270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CASSANDRA F COX/Primary Examiner, Art Unit 2849
Read full office action

Prosecution Timeline

Nov 26, 2024
Application Filed
Jan 28, 2026
Examiner Interview (Telephonic)
Apr 04, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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2y 5m to grant Granted Feb 10, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
97%
With Interview (+3.0%)
1y 11m
Median Time to Grant
Low
PTA Risk
Based on 831 resolved cases by this examiner. Grant probability derived from career allow rate.

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