DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-18 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. USPN 12,190,792 B2 in view of Ka et al. (USPN 2017/0294502 A1) in view of Choi et al. (USPN 2019/0115415 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because it is clear that most of the elements of the application claims 1-18 are found in patent claims 1-20 (see chart below). The difference between the application claims 1-18 and the patent claims 1-20 is underlined below. Thus the invention of claims 1-20 of the patent is in effect a "species" of the "generic" invention of the application claims 1-18. It has been held that the generic invention is "anticipated" by the "species". Further, the underlined differences are taught by Choi (see the 103 rejection below). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to further modify the display device of USPN 12,190,792 B2 to include the details taught by Choi (see 103 rejection below).
USPN 12,190,792 B2
Instant Application 18/960268
1. A display device, comprising:
a display panel including a substrate on which an active area where a plurality of subpixels are disposed is defined;
at least one hole area surrounded by the active area;
a boundary area disposed between the at least one hole area and the active area;
at least one gate line to supply a scan signal or an emission signal to a first group of subpixels among the plurality of subpixels;
a first data line disposed on the active area and the boundary area, the first data line being configured to supply first data voltages to a second group of subpixels including at least one first color subpixel and at least one second color subpixel among the plurality of subpixels, the second group not including any green subpixels; and
a second data line disposed on the active area and the boundary area, the second data line being configured to supply a second data voltage to a third group of subpixels including at least one green subpixel different from the first and second color subpixels among the plurality of subpixels,
wherein in the boundary area, a vertical distance of the second data line from the substrate is different from a vertical distance of the first data line from the substrate, to reduce a load of the second data line to prevent a decrease of luminance in an area located around the at least one hole area.
4. The display device of claim 1, wherein the second group of subpixels includes a red subpixel and a blue subpixel, and does not include a green subpixel.
5. The display device of claim 4, wherein the third group of subpixels includes the green subpixel, and does not include the red subpixel and the blue subpixel.
6. The display device of claim 5, further comprising:
an insulating layer disposed between the at least one gate line and the first data line; and a passivation layer disposed between the first data line and the second data line, wherein a thickness of the insulating layer is greater than a thickness of the passivation layer.
+ Choi (see rejection below)
1. A display device, comprising:
a display panel having an active area where a plurality of subpixels are disposed over a substrate;
at least one hole area surrounded by the active area;
a boundary area disposed between the at least one hole area and the active area;
a first data line disposed on the active area and the boundary area, and configured to supply a first data voltage to each of a first group of subpixels representing at least one first color among the plurality of subpixels; and
a second data line disposed on the active area and the boundary area, and configured to supply a second data voltage to each of a second group of subpixels representing a second color among the plurality of subpixels; and
an insulating layer disposed between the first and second data lines,
wherein a vertical distance between the second data line and the substrate is different from a vertical distance between the first data line and the substrate,
wherein in a cross-sectional view, a first vertical distance from a portion of an upper surface of the insulating layer contacting a lower surface of the second data line to a lower surface of the insulating layer is different from a second vertical distance from a portion of the lower surface of the insulating layer contacting an upper surface of the first data line to the upper surface of the insulating layer,
wherein in the cross-sectional view and in the boundary area, the upper surface of the insulating layer extends with a same vertical distance from an upper surface of the substrate along the upper surface of the substrate, and wherein each of the plurality of subpixels includes a driving transistor configured to drive a light-emitting device and including a gate electrode, a first electrode and a second electrode.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-18 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (USPN 2020/0273941 A1 – see also KR Application No: KR 20190023263 A filed 2019-02-27) in view of Choi et al. (USPN 2019/0115415 A1).
As to claim 1, Cha teaches a display device, comprising:
a display panel having an active area where a plurality of subpixels are disposed over a substrate (see at least Figs. 3-6, 8A, 10: display panel 110 including display area DA in which pixels PX are disposed over first substrate SUB1; [0043], [0049]-[0051], [0067]-[0068] “The main area MA may include the display area DA in which pixels are formed to display images”, [0080]-[0085] “The display unit DU includes a first substrate SUB1 and a thin-film transistor (TFT) layer TFTL, a light-emitting element layer EML…”, [0093]-[0098]; [0163]-[0164] “Each of the pixels PX may include a red subpixel emitting red light, a green subpixel emitting green light, and a blue subpixel emitting blue light.”);
at least one hole area surrounded by the active area (see at least Figs. 5, 6, and 20: through hole TH, dead-space area DSA, wiring area LA, and pixel area PXA, display area DA; [0050], [0068], [0095]-[0096] “The through hole TH, which penetrates the display panel 110, is formed in the display area DA.”, [0103]-[0105]);
a boundary area disposed between the at least one hole area and the active area (see at least Fig. 6; [0103]-[0109]). [0104] “The dead space area DSA may be arranged to surround the through hole TH”; [0105] “The wiring area LA may be arranged to surround the dead space area DSA.”; [0109] “The pixel area PXA refers to an area in which the pixels PX are located. In the pixel area PXA, the scan lines SL may be arranged to extend in parallel in the first direction (or the X-axis direction), and the data lines DL may be arranged to extend in parallel in the second direction (or the Y-axis direction).” – note wiring area LA, alone or together with DSA corresponds to a boundary area between through hole TH and the surrounding active pixel area);
a first data line disposed on the active area and the boundary area (see at least Figs. 6-9 and Figs. 16-17; [0094]-[0096], [0107]-[0109], [0179]-[0184] “The (s+5)-th data line DLs+5 includes only the 1A-th data line DLA1 in both the pixel area PXA and the wiring area LA. The (s+6)-th data line DLs+6 includes only the 2B-th data line DLB2 in both the pixel area PXA and the wiring area LA.” – note each of the two adjacent data lines extends through both the pixel/active area and the wiring/boundary area), and
configured to supply a first data voltage to each of a first group of subpixels representing at least one first color among the plurality of subpixels (see at least [0074] “the first driving circuit unit 200 may supply data voltages to the data lines”, [0097]-[0100] “The first driving circuit unit 200 converts the digital video data into positive/negative analog data voltages and provides the positive/negative analog data voltages to the data lines DL”, [0132]-[0133] “the first pixel may be a red pixel … the second pixel may be a green pixel …, and the third pixel may be a blue pixel … the (s+5)-th data line DLs+5 may be connected to the first and third pixels, and the (s+6)-th data line DLs+6 may be connected to the second pixel.” – note DLs+5 can supply data to a first color group, such as red and/or blue subpixels, while DLs+6 supplies data to a different color group, such as green subpixels);
a second data line disposed on the active area and the boundary area (see at least Figs. 6-9 and Figs. 16-17; [0094]-[0096], [0107]-[0109], [0179]-[0184] “The (s+5)-th data line DLs+5 includes only the 1A-th data line DLA1 in both the pixel area PXA and the wiring area LA. The (s+6)-th data line DLs+6 includes only the 2B-th data line DLB2 in both the pixel area PXA and the wiring area LA.” – note each of the two adjacent data lines extends through both the pixel/active area and the wiring/boundary area), and
configured to supply a second data voltage to each of a second group of subpixels representing a second color among the plurality of subpixels (see at least [0074] “the first driving circuit unit 200 may supply data voltages to the data lines”, [0097]-[0100] “The first driving circuit unit 200 converts the digital video data into positive/negative analog data voltages and provides the positive/negative analog data voltages to the data lines DL”, [0132]-[0133] “the first pixel may be a red pixel … the second pixel may be a green pixel …, and the third pixel may be a blue pixel … the (s+5)-th data line DLs+5 may be connected to the first and third pixels, and the (s+6)-th data line DLs+6 may be connected to the second pixel.” – note DLs+5 can supply data to a first color group, such as red and/or blue subpixels, while DLs+6 supplies data to a different color group, such as green subpixels); and
an insulating layer disposed between the first and second data lines, wherein a vertical distance between the second data line and the substrate is different from a vertical distance between the first data line and the substrate (see at least Figs. 10-11: DLA1 of first data line DLs+5 and DLB2 of second data line DLs+6 are vertically separated from substrate SUB1 by different distances, with insulating material 143 between DLA1 and DLB2; and Figs. 16-17; [0138], [0147] “The first data metal layer DTL1 may include the 1A-th data line DLA1”; [0151] “A third interlayer insulating film 143 may be formed on the first data metal layer DTL1.”; [0152] “The second data metal layer DTL2 may be formed on the third interlayer insulating film 143. The second data metal layer DTL2 may include the 2B-th data line DLB2”; [0180] “The 1A-th data line DLA1 … may be formed as a first data layer. On the other hand, the 2B-th data line DLB2 … may be formed as a second data layer, which is located in a different layer from the first data layer.”), and
wherein each of the plurality of subpixels includes a driving transistor configured to drive a light-emitting device and including a gate electrode, a first electrode and a second electrode. (see at least Figs. 8A and 10; [0098] “Each of the pixels PX may include TFTs (including a driving transistor and one or more switching transistors), an OLED, and a capacitor.”, [0117]-[0125] “The driving transistor DT may include a driving active layer DT_ACT, a driving gate electrode DT_G, a driving source electrode DT_S, and a driving drain electrode DT_D.”, [0158]-[0165] – note the driving source and drain electrodes correspond to the first and second electrodes).
Cha does not directly teach wherein in a cross-sectional view, a first vertical distance from a portion of an upper surface of the insulating layer contacting a lower surface of the second data line to a lower surface of the insulating layer is different from a second vertical distance from a portion of the lower surface of the insulating layer contacting an upper surface of the first data line to the upper surface of the insulating layer, wherein in the cross-sectional view and in the boundary area, the upper surface of the insulating layer extends with a same vertical distance from an upper surface of the substrate along the upper surface of the substrate.
Choi teaches wherein in a cross-sectional view, a first vertical distance from a portion of an upper surface of the insulating layer contacting a lower surface of the second data line to a lower surface of the insulating layer is different from a second vertical distance from a portion of the lower surface of the insulating layer contacting an upper surface of the first data line to the upper surface of the insulating layer, wherein in the cross-sectional view and in the boundary area, the upper surface of the insulating layer extends with a same vertical distance from an upper surface of the substrate along the upper surface of the substrate (see at least Figs. 6, 8, 13, 16, 17, 18: a first vertical distance from a portion of an upper surface of the insulating layer 220 contacting a lower surface of the second data line 231 to a lower surface of the insulating layer 220 is different from a second vertical distance from a portion of the lower surface of the insulating layer 220 contacting an upper surface of the first data line 191 to the upper surface of the insulating layer 220, and the upper surface of the insulating layer 220 extends with a same vertical distance from an upper surface of the substrate 110 along the upper surface of the substrate; [0091] “the planarization layer 220 is disposed on … the data line DL”; [0092] “The planarization layer 220 can planarize the substrate 110 by eliminating height differences of the substrate 110…”; [0111] “The sensor area 330 is located in the display area 310. The sensor area 330 is surrounded by the display area 310”; [0113] “An open hole, referred to hereinafter as a penetrating sensor area, is provided which physically penetrates through the display panel 101 or the substrate 110 at the sensor area 330”; [0116] “a wiring connection area 340 is located between the sensor area 330 and the display area 310.” – note wiring connection area 340 is the boundary area surrounding a hole; [0175] “A planarization layer 220 is disposed on the data lines 191 and 193 … and contact holes 233 and 234 are formed in planarization layer 220 … in wiring connection area 340.”; [0176] “the data lines 231 and 232 are disposed on the planarization layer 220 in the sensor area 330 and the wiring connection area 340.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Cha’s vertically separated data lines in the wiring area using Choi’s planarization-layer arrangement in order to electrically isolate the vertically separated data lines while planarizing the wiring area.
As to claim 2, the combination of Cha and Choi teach the display device of claim 1 (see above rejection), wherein each of the plurality of subpixels further includes: a first transistor (see Cha at least fig. 8A: ST1) connected between the gate electrode and the second electrode of the driving transistor (see Cha at least fig. 8A and [0119] “The first switching transistor ST1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first gate electrode G1 may be a part of the (p+1)-th scan line SLp+1 that overlaps with the first active layer ACT1. The first source electrode S1 may be connected to the drain electrode DT_D of the driving transistor DT.”; a second transistor (see Cha at least fig. 8A: ST2) connected between the gate electrode of the driving transistor and an initialization voltage line (see Cha at least fig. 8A and [0120] “The second switching transistor ST2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second gate electrode G2 may be a part of the p-th scan line SLp that overlaps with the second active layer ACT2. The second source electrode S2 may be connected to the gate electrode DT-G of the driving transistor DT and the first drain electrode D1 of the first switching transistor ST1. The second drain electrode D2 may be connected to an initialization voltage line VIL.”); a third transistor (see Cha at least fig. 8A: ST6) connected between the first electrode of the driving transistor and one of the first and second data lines (see Cha at least fig. 8A and [0124] “The sixth switching transistor ST6 may include a sixth active layer ACT6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth gate electrode G6 may be a part of the (p+1)-th scan line SLp+1 that overlaps with the sixth active layer ACT6. The sixth source electrode S6 may be connected to a data line through a third contact hole CNT3. The sixth drain electrode D6 may be connected to the driving source electrode DT_S of the driving transistor DT.”); a fourth transistor (see Cha at least fig. 8A: ST5) connected between a power voltage line and the first electrode of the driving transistor (see Cha at least fig. 8A and [0123] “The fifth switching transistor ST5 may include a fifth active layer ACT5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. ... The fifth drain electrode D5 may be connected to the source electrode DT_S of the driving transistor DT ... The fifth source electrode S5 may be connected to a first power supply voltage line VDL”); a fifth transistor (see Cha at least fig. 8A: ST4) connected between the second electrode of the driving transistor and an anode electrode of the light-emitting device (see Cha at least fig. 8A and [0122] “The fourth switching transistor ST4 may include a fourth active layer ACT4, a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode D4. ... The fourth source electrode S4 may be connected to the drain electrode DT_D of the driving transistor DT ... The fourth drain electrode D4 may be connected to the anode electrode AND of the OLED.”); and a sixth transistor (see Cha at least fig. 8A: ST3) connected between an initialization voltage line and the anode electrode (see Cha at least fig. 8A and [0121] “The third switching transistor ST3 may include a third active layer ACT3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3. ... The third source electrode S3 may be connected to an anode electrode AND of an OLED. The third drain electrode D3 may be connected to the initialization voltage line VIL”).
As to claim 3, the combination of Cha and Choi teach the display device of claim 2 (see above rejection), further comprising: a first gate line disposed on the active area and extending to the boundary area, and supplying a first scan signal to a third group of the plurality of subpixels; and a second gate line disposed on the active area and extending to the boundary area, and supplying a second scan signal to the third group of the plurality of subpixels (see Cha at least fig. 8A: first gate line SLp, second gate line SLp+1, third group is pixels/subpixels connected to both scan lines; and [0097] “Each of the pixels PX may be connected to at least one of the scan lines SL…”; [0119]-[0124]: ST2 and ST3 are controlled by SLp and ST1 and ST6 are controlled by SLp+1).
As to claim 4, the combination of Cha and Choi teach the display device of claim 3 (see above rejection), wherein the fifth transistor is turned on in response to the first scan signal or the second scan signal from the first gate line or the second gate line (see Cha at least fig. 8A: ST4 and [0122] “The fourth switching transistor ST4 may include a fourth active layer ACT4, a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode D4. The fourth gate electrode G4 may be a part of a (p+1)-th emission control line ELp+1 that overlaps with the fourth active layer ACT4. The fourth source electrode S4 may be connected to the drain electrode DT_D of the driving transistor DT and the first source electrode S1 of the first switching transistor ST1. The fourth drain electrode D4 may be connected to the anode electrode AND of the OLED.”).
As to claim 5, the combination of Cha and Choi teach the display device of claim 1 (see above rejection), wherein the first group of the plurality of subpixels includes at least one first color subpixel and at least one second color subpixel, and wherein the second group of the plurality of subpixels includes at least one third color subpixel different from the first and second color subpixels (see Cha at least [0132] “the first pixel may be a red pixel .., the second pixel may be a green pixel .., and the third pixel may be a blue pixel …, the (s+5)-th data line DLs+5 may be connected to the first and third pixels, and the (s+6)-th data line DLs+6 may be connected to the second pixel.” – note first group is red and blue and second group is green).
As to claim 6, the combination of Cha and Choi teach the display device of claim 5 (see above rejection), wherein a peak wavelength of light emitted by the third color subpixel is smaller than a peak wavelength of light emitted by the first color subpixel and greater than a peak wavelength of light emitted by the second color subpixels (see Cha at least [0132] “the first pixel may be a red pixel .., the second pixel may be a green pixel .., and the third pixel may be a blue pixel …, the (s+5)-th data line DLs+5 may be connected to the first and third pixels, and the (s+6)-th data line DLs+6 may be connected to the second pixel.” – note first color is red, second color is blue and third color is green and the known spectral ordering is blue < green < red).
As to claim 7, the combination of Cha and Choi teach the display device of claim 1 (see above rejection), wherein the first data line and the second data line are alternately arranged (see Cha at least [0134], [0174], [0183] “each odd-numbered data line may include the 1A-th data line DLA1, and each even-numbered data line may include the 2B-th data line DLB2.”).
As to claim 8, the combination of Cha and Choi teach the display device of claim 7 (see above rejection), wherein the first group of the plurality of subpixels and the second group of the plurality of subpixels are alternately arranged (see Cha at least [0132] “the first pixel may be a red pixel .., the second pixel may be a green pixel .., and the third pixel may be a blue pixel …, the (s+5)-th data line DLs+5 may be connected to the first and third pixels, and the (s+6)-th data line DLs+6 may be connected to the second pixel.”; [0134], [0174], [0183] “each odd-numbered data line may include the 1A-th data line DLA1, and each even-numbered data line may include the 2B-th data line DLB2.” – note odd lines are first-group pixels and even lines are second-group pixels, and the pixels are associated with those respective lines, then the groups alternate in the data-line direction).
As to claim 9, Cha teaches a display device, comprising:
a display panel including a substrate on which an active area where a plurality of subpixels are disposed is defined (see Cha at least figs. 5-6: substrate SUB1, display area DA/pixel area PXA);
at least one hole area surrounded by the active area (see at least figs. 5-6: through hole TH within the display area);
a boundary area disposed between the at least one hole area and the active area (see at figs. 5-6: least dead space area DSA and wiring area LA between TH and the surrounding pixel region; and [0095] “The through hole TH, which penetrates the display panel 110, is formed in the display area DA.”; [0105] “The wiring area LA may be arranged to surround the dead space area DSA.”);
at least one gate line supplying a scan signal or an emission signal to a first group of subpixels among the plurality of subpixels (see at least [0099] “The scan driver 111 may generate scan signals in accordance with the scan control signals and may provide the scan signals to the scan lines SL.”; [0122] “The fourth gate electrode G4 may be a part of a (p+1)-th emission control line ELp+1…”);
a first data line disposed on the active area and the boundary area, the first data line being configured to supply first data voltages to a second group of subpixels including at least one first color subpixel and at least one second color subpixel among the plurality of subpixels (see at least Figs. 6-9 and Figs. 16-17; [0074] “the first driving circuit unit 200 may supply data voltages to the data lines”, [0094]-[0096], [0097]-[0100] “The first driving circuit unit 200 converts the digital video data into positive/negative analog data voltages and provides the positive/negative analog data voltages to the data lines DL”; [0107]-[0109], [0132] “the first pixel may be a red pixel .., the second pixel may be a green pixel .., and the third pixel may be a blue pixel …, the (s+5)-th data line DLs+5 may be connected to the first and third pixels, and the (s+6)-th data line DLs+6 may be connected to the second pixel.” – note first data line DLs+5 (red/blue); [0179]-[0184] “The (s+5)-th data line DLs+5 includes only the 1A-th data line DLA1 in both the pixel area PXA and the wiring area LA. The (s+6)-th data line DLs+6 includes only the 2B-th data line DLB2 in both the pixel area PXA and the wiring area LA.” – note each of the two adjacent data lines extends through both the pixel/active area and the wiring/boundary area); and
a second data line disposed on the active area and the boundary area, the second data line being configured to supply a second data voltage to a third group of subpixels including at least one third color subpixel different from the first and second color subpixels among the plurality of subpixels (see at least at least Figs. 6-9 and Figs. 16-17; [0074] “the first driving circuit unit 200 may supply data voltages to the data lines”, [0094]-[0096], [0097]-[0100] “The first driving circuit unit 200 converts the digital video data into positive/negative analog data voltages and provides the positive/negative analog data voltages to the data lines DL”; [0107]-[0109], [0132] “the first pixel may be a red pixel .., the second pixel may be a green pixel ..s– note second data line DLs+6 (green); [0179]-[0184] “The (s+5)-th data line DLs+5 includes only the 1A-th data line DLA1 in both the pixel area PXA and the wiring area LA. The (s+6)-th data line DLs+6 includes only the 2B-th data line DLB2 in both the pixel area PXA and the wiring area LA.” – note each of the two adjacent data lines extends through both the pixel/active area and the wiring/boundary area); and
an insulating layer disposed between the first and second data lines, wherein in the boundary area, a vertical distance of the second data line from the substrate is different from a vertical distance of the first data line from the substrate (see at least Figs. 10-11: DLA1 of first data line DLs+5 and DLB2 of second data line DLs+6 are vertically separated from substrate SUB1 by different distances, withe insulating material 143 between DLA1 and DLB2; and Figs. 16-17; [0138], [0147] “The first data metal layer DTL1 may include the 1A-th data line DLA1”; [0151] “A third interlayer insulating film 143 may be formed on the first data metal layer DTL1.”; [0152] “The second data metal layer DTL2 may be formed on the third interlayer insulating film 143. The second data metal layer DTL2 may include the 2B-th data line DLB2”; [0180] “The 1A-th data line DLA1 … may be formed as a first data layer. On the other hand, the 2B-th data line DLB2 … may be formed as a second data layer, which is located in a different layer from the first data layer.”)
wherein each of data lines running through the boundary area is any one of the first data line for supplying the first data voltages to the second group of subpixels and the second data line for supplying the second data voltage to the third group of subpixels (see at least at least Figs. 6-9 and Figs. 16-17; [0074] “the first driving circuit unit 200 may supply data voltages to the data lines”, [0094]-[0096], [0097]-[0100] “The first driving circuit unit 200 converts the digital video data into positive/negative analog data voltages and provides the positive/negative analog data voltages to the data lines DL”; [0107]-[0109], [0132] “the first pixel may be a red pixel .., the second pixel may be a green pixel ..s– note second data line DLs+6 (green); [0179] “The (s+5)-th data line DLs+5 includes only the 1A-th data line DLA1 in both the pixel area PXA and the wiring area LA. The (s+6)-th data line DLs+6 includes only the 2B-th data line DLB2 in both the pixel area PXA and the wiring area LA.” – note each of the two adjacent data lines extends through both the pixel/active area and the wiring/boundary area; [0183] “each odd-numbered data line may include the 1A-th data line DLA1, and each even-numbered data line may include the 2B-th data line DLB2.” – note odd lines and even lines are different group pixels), and
wherein each of the plurality of subpixels includes a driving transistor configured to drive a light-emitting device and including a gate electrode, a first electrode and a second electrode. (see at least Figs. 8A and 10; [0098] “Each of the pixels PX may include TFTs (including a driving transistor and one or more switching transistors), an OLED, and a capacitor.”, [0117]-[0125] “The driving transistor DT may include a driving active layer DT_ACT, a driving gate electrode DT_G, a driving source electrode DT_S, and a driving drain electrode DT_D.”, [0158]-[0165] – note the driving source and drain electrodes correspond to the first and second electrodes).
Cha does not directly teach wherein in a cross-sectional view, a first vertical distance from a portion of an upper surface of the insulating layer contacting a lower surface of the second data line to a lower surface of the insulating layer is different from a second vertical distance from a portion of the lower surface of the insulating layer contacting an upper surface of the first data line to the upper surface of the insulating layer, wherein in the cross-sectional view and in the boundary area, the upper surface of the insulating layer extends with a same vertical distance from an upper surface of the substrate along the upper surface of the substrate.
Choi teaches wherein in a cross-sectional view, a first vertical distance from a portion of an upper surface of the insulating layer contacting a lower surface of the second data line to a lower surface of the insulating layer is different from a second vertical distance from a portion of the lower surface of the insulating layer contacting an upper surface of the first data line to the upper surface of the insulating layer, wherein in the cross-sectional view and in the boundary area, the upper surface of the insulating layer extends with a same vertical distance from an upper surface of the substrate along the upper surface of the substrate (see at least Figs. 6, 8, 13, 16, 17, 18: a first vertical distance from a portion of an upper surface of the insulating layer 220 contacting a lower surface of the second data line 231 to a lower surface of the insulating layer 220 is different from a second vertical distance from a portion of the lower surface of the insulating layer 220 contacting an upper surface of the first data line 191 to the upper surface of the insulating layer 220, and the upper surface of the insulating layer 220 extends with a same vertical distance from an upper surface of the substrate 110 along the upper surface of the substrate; [0091] “the planarization layer 220 is disposed on … the data line DL”; [0092] “The planarization layer 220 can planarize the substrate 110 by eliminating height differences of the substrate 110…”; [0111] “The sensor area 330 is located in the display area 310. The sensor area 330 is surrounded by the display area 310”; [0113] “An open hole, referred to hereinafter as a penetrating sensor area, is provided which physically penetrates through the display panel 101 or the substrate 110 at the sensor area 330”; [0116] “a wiring connection area 340 is located between the sensor area 330 and the display area 310.” – note wiring connection area 340 is the boundary area surrounding a hole; [0175] “A planarization layer 220 is disposed on the data lines 191 and 193 … and contact holes 233 and 234 are formed in planarization layer 220 … in wiring connection area 340.”; [0176] “the data lines 231 and 232 are disposed on the planarization layer 220 in the sensor area 330 and the wiring connection area 340.”).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to implement Cha’s vertically separated data lines in the wiring area using Choi’s planarization-layer arrangement in order to electrically isolate the vertically separated data lines while planarizing the wiring area.
As to claim 10, the combination of Cha and Choi teach the display device of claim 9 (see above rejection), wherein a peak wavelength of light emitted by the third color subpixel is smaller than a peak wavelength of light emitted by the first color subpixel and greater than a peak wavelength of light emitted by the second color subpixels (see Cha at least [0132] “the first pixel may be a red pixel .., the second pixel may be a green pixel .., and the third pixel may be a blue pixel …, the (s+5)-th data line DLs+5 may be connected to the first and third pixels, and the (s+6)-th data line DLs+6 may be connected to the second pixel.” – note first color is red, second color is blue and third color is green and the known spectral ordering is blue < green < red).
As to claim 11, the combination of Cha and Choi teach the display device of claim 9 (see above rejection), wherein the first data line and the second data line are alternately arranged (see Cha at least [0134], [0174], [0183] “each odd-numbered data line may include the 1A-th data line DLA1, and each even-numbered data line may include the 2B-th data line DLB2.”).
As to claim 12, the combination of Cha and Choi teach the display device of claim 9 (see above rejection), wherein the second group of the plurality of subpixels and the third group of the plurality of subpixels are alternately arranged in an extending direction of the at least one gate line (see Cha at least [0132] “the first pixel may be a red pixel .., the second pixel may be a green pixel .., and the third pixel may be a blue pixel …, the (s+5)-th data line DLs+5 may be connected to the first and third pixels, and the (s+6)-th data line DLs+6 may be connected to the second pixel.”; [0134], [0174], [0183] “each odd-numbered data line may include the 1A-th data line DLA1, and each even-numbered data line may include the 2B-th data line DLB2.” – note odd lines are third-group pixels and even lines are second-group pixels, and the pixels are associated with those respective lines, then the groups alternate in the data-line direction).
As to claim 13, the combination of Cha and Choi teach the display device of claim 12 (see above rejection), wherein the at least one first color subpixel and the at least one second color subpixel are alternately arranged in an extending direction of a first gate line (see Cha at least [0132] “the first pixel may be a red pixel .., the second pixel may be a green pixel .., and the third pixel may be a blue pixel …, the (s+5)-th data line DLs+5 may be connected to the first and third pixels, and the (s+6)-th data line DLs+6 may be connected to the second pixel.”; [0134], [0174], [0183] “each odd-numbered data line may include the 1A-th data line DLA1, and each even-numbered data line may include the 2B-th data line DLB2.”)
As to claim 14, the combination of Cha and Choi teach the display device of claim 12 (see above rejection), wherein the at least one third color subpixel are arranged in a same column in an extending direction of a second gate line. (see Cha at least [0132] and note examiner is taking official notice that this is a known PenTile/subpixel-layout that would be obvious to incorporate).
As to claim 15, the combination of Cha and Choi teach the display device of claim 9 (see above rejection), wherein each of the plurality of subpixels further includes: a first transistor (see Cha at least fig. 8A: ST1) connected between the gate electrode and the second electrode of the driving transistor (see Cha at least fig. 8A and [0119] “The first switching transistor ST1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first gate electrode G1 may be a part of the (p+1)-th scan line SLp+1 that overlaps with the first active layer ACT1. The first source electrode S1 may be connected to the drain electrode DT_D of the driving transistor DT.”; a second transistor (see Cha at least fig. 8A: ST2) connected between the gate electrode of the driving transistor and an initialization voltage line (see Cha at least fig. 8A and [0120] “The second switching transistor ST2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second gate electrode G2 may be a part of the p-th scan line SLp that overlaps with the second active layer ACT2. The second source electrode S2 may be connected to the gate electrode DT-G of the driving transistor DT and the first drain electrode D1 of the first switching transistor ST1. The second drain electrode D2 may be connected to an initialization voltage line VIL.”); a third transistor (see Cha at least fig. 8A: ST6) connected between the first electrode of the driving transistor and one of the first and second data lines (see Cha at least fig. 8A and [0124] “The sixth switching transistor ST6 may include a sixth active layer ACT6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth gate electrode G6 may be a part of the (p+1)-th scan line SLp+1 that overlaps with the sixth active layer ACT6. The sixth source electrode S6 may be connected to a data line through a third contact hole CNT3. The sixth drain electrode D6 may be connected to the driving source electrode DT_S of the driving transistor DT.”); a fourth transistor (see Cha at least fig. 8A: ST5) connected between a power voltage line and the first electrode of the driving transistor (see Cha at least fig. 8A and [0123] “The fifth switching transistor ST5 may include a fifth active layer ACT5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. ... The fifth drain electrode D5 may be connected to the source electrode DT_S of the driving transistor DT ... The fifth source electrode S5 may be connected to a first power supply voltage line VDL”); a fifth transistor (see Cha at least fig. 8A: ST4) connected between the second electrode of the driving transistor and an anode electrode of the light-emitting device (see Cha at least fig. 8A and [0122] “The fourth switching transistor ST4 may include a fourth active layer ACT4, a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode D4. ... The fourth source electrode S4 may be connected to the drain electrode DT_D of the driving transistor DT ... The fourth drain electrode D4 may be connected to the anode electrode AND of the OLED.”); and a sixth transistor (see Cha at least fig. 8A: ST3) connected between an initialization voltage line and the anode electrode (see Cha at least fig. 8A and [0121] “The third switching transistor ST3 may include a third active layer ACT3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3. ... The third source electrode S3 may be connected to an anode electrode AND of an OLED. The third drain electrode D3 may be connected to the initialization voltage line VIL”).
As to claim 16, the combination of Cha and Choi teach the display device of claim 15 (see above rejection), wherein the fifth transistor is turned on in response to the emission signal from the at least one gate line (see Cha at least fig. 8A: fifth transistor ST4, gate line ELp+1, and [0122] “The fourth switching transistor ST4 may include a fourth active layer ACT4, a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode D4. The fourth gate electrode G4 may be a part of a (p+1)-th emission control line ELp+1 that overlaps with the fourth active layer ACT4. The fourth source electrode S4 may be connected to the drain electrode DT_D of the driving transistor DT and the first source electrode S1 of the first switching transistor ST1. The fourth drain electrode D4 may be connected to the anode electrode AND of the OLED.”).
As to claim 17, the combination of Cha and Choi teach the display device of claim 1 (see above rejection), wherein the first group of subpixels does not include green subpixels, and the second group of subpixels includes green subpixels, and wherein in the boundary area, the first and second data lines are disposed adjacent to each other, and the second data line supplying the second data voltage to each of the green subpixels is disposed closer to the at least one hole area than the first data line supplying the first data voltage to the first group of subpixels not including green subpixels (see Cha at least figs. 5-6 and [0129]: DLs+6 adjacent to DLs+5; [0132]: DLs+5 is first and third pixels (red/blue), DLs+6 is second pixel (green); [0179] “the (s+6)-th data line DLs+6, which is adjacent to the (s+5)-th data line DLs+5…” and Choi at least figs. 6, 19-20 – note it would have been obvious, as a matter of routine layout optimization within the boundary/detour area of Cha/Choi, to select the relative positioning of those adjacent data lines such that the data line supplying green subpixels is disposed closer to the hole area than the data line supplying non- green subpixels because of the known importance of green subpixels in OLED/PenTile arrangements for luminance and resolution, and the known desire to optimize routing, signal integrity, and layout efficiency in constrained boundary regions surrounding hole areas).
As to claim 18, the combination of Cha and Choi teach the display device of claim 9 (see above rejection), wherein the second group of subpixels does not include green subpixels, and the third group of subpixels includes green subpixels, and wherein in the boundary area, the first and second data lines are disposed adjacent to each other, and the second data line supplying the second data voltage to each of the green subpixels is disposed closer to the at least one hole area than the first data line supplying the first data voltages to the second group of subpixels not including green subpixels (see Cha at least figs. 5-6 and [0129]: DLs+6 adjacent to DLs+5; [0132]: DLs+5 is first and third pixels (red/blue), DLs+6 is second pixel (green); [0179] “the (s+6)-th data line DLs+6, which is adjacent to the (s+5)-th data line DLs+5…” and Choi at least figs. 6, 19-20 – note it would have been obvious, as a matter of routine layout optimization within the boundary/detour area of Cha/Choi, to select the relative positioning of those adjacent data lines such that the data line supplying green subpixels is disposed closer to the hole area than the data line supplying non- green subpixels because of the known importance of green subpixels in OLED/PenTile arrangements for luminance and resolution, and the known desire to optimize routing, signal integrity, and layout efficiency in constrained boundary regions surrounding hole areas).
Response to Arguments
Applicant’s arguments filed 7/1/2026 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JENNIFER L ZUBAJLO/Examiner, Art Unit 2627 9/11/2026
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627
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