DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim(s) 1, 9 and 15 is/are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 11 and 20 of U.S. Patent No. US-12182318-B2 (hereinafter “Pat ‘318”). Although the claims at issue are not identical, they are not patentably distinct from each other.
Per claim 1 (independent):
Claim 11 of Pat ‘318 anticipates all of the limitations in claim 1 of the instant application.
Claims / App Language
Pat ‘318 Language
1
A system, comprising:
a memory sub-system operable to couple with a nonvolatile memory device that is separate from the memory sub-system via a firmware component of the memory subsystem, the memory sub-system configured to:
receive, by the firmware component and from the nonvolatile memory device, an encrypted first cryptographic key for encrypting or decrypting data stored on a memory of the memory sub-system;
decrypt, by the memory sub-system, the encrypted first cryptographic key; and
store the first cryptographic key in a volatile memory of the memory sub-system based at least in part on decrypting the encrypted first cryptographic key
11
A system, comprising:
a memory sub-system operable to couple with a nonvolatile memory device that is separate from the memory sub-system via a firmware component of the memory sub-system, the memory sub-system configured to:
receive, by the firmware component and from the nonvolatile memory device, an encrypted first cryptographic key and a second cryptographic key, wherein the encrypted first cryptographic key is for encrypting or decrypting data stored on a memory device of the memory sub-system and different from the nonvolatile memory device;
generate, by a hardware component of the memory sub-system, an initialization vector based at least in part on the first cryptographic key;
decrypt, by the hardware component, the encrypted first cryptographic key using the second cryptographic key and the initialization vector; and
store the first cryptographic key in a volatile memory device on the hardware component based at least in part on decrypting the encrypted first cryptographic key.
Per claim 9 (independent):
Claim 1 of Pat ‘318 anticipates all of the limitations in claim 9 of the instant application.
Claims / App Language
Pat ‘318 Language
9
A method at a memory sub-system, comprising:
receiving, by a firmware component of the memory sub-system and from a nonvolatile memory device separate from the memory sub-system, an encrypted first cryptographic key, wherein the encrypted first cryptographic key is for encrypting or decrypting data stored on a memory of the memory sub-system;
decrypting, by the memory sub-system, the encrypted first cryptographic key; and
storing the first cryptographic key in a volatile memory of the memory sub
system based at least in part on decrypting the encrypted first cryptographic key.
1
A method at a memory sub-system, comprising:
receiving, by a firmware component of the memory sub-system and from a nonvolatile memory device separate from the memory sub-system, an encrypted first cryptographic key and a second cryptographic key, wherein the encrypted first cryptographic key is for encrypting or decrypting data stored on a memory device of the memory sub-system and different from the nonvolatile memory device;
generating, by a hardware component of the memory sub-system, an initialization vector based at least in part on the first cryptographic key, the data, or both;
decrypting, by the hardware component, the encrypted first cryptographic key using the second cryptographic key and the initialization vector; and
storing the first cryptographic key in a volatile memory device on the hardware component based at least in part on decrypting the encrypted first cryptographic key.
Per claim 15 (independent):
Claim 20 of Pat ‘318 anticipates all of the limitations in claim 15 of the instant application.
Claims / App Language
Pat ‘318 Language
15
A non-transitory computer-readable medium storing code comprising instructions which, when executed by one or more processors of a memory sub-system, cause the memory sub-system to:
receive, by a firmware component of the memory sub-system and from a nonvolatile memory device separate from the memory sub-system, an encrypted first cryptographic key, wherein the encrypted first cryptographic key is for encrypting or decrypting data stored on a memory of the memory sub-system;
decrypt, by the memory sub-system, the encrypted first cryptographic key; and
store the first cryptographic key in a volatile memory of the memory sub
system based at least in part on decrypting the encrypted first cryptographic key.
20
A non-transitory computer-readable medium storing code, the code comprising instructions executable by processing logic to:
receive, by a firmware component of a memory sub-system and from a nonvolatile memory device separate from the memory sub-system, an encrypted first cryptographic key and a second cryptographic key, wherein the encrypted first cryptographic key is for encrypting or decrypting data stored on a memory device of the memory sub-system and different from the nonvolatile memory device;
generate, by a hardware component of the memory sub-system, an initialization vector based at least in part on the first cryptographic key;
decrypt, by the hardware component, the encrypted first cryptographic key using the second cryptographic key and the initialization vector; and
store the first cryptographic key in a volatile memory device on the hardware component based at least in part on decrypting the encrypted first cryptographic key
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 7-9 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Von Der Lippe et al., US-20180278415-A1 (hereinafter “Von ‘415”).
Per claim 1 (independent):
Von ‘415 discloses: A system, comprising:
a memory sub-system operable to couple with a nonvolatile memory device that is separate from the memory sub-system via a firmware component of the memory subsystem (FIG. 1, [0097], The apparatus 10 (a system) has a control unit 12 (a memory sub-system) to which both a hard disk 14 (a nonvolatile memory device, that is separate from the control unit 12) and a plurality of further peripheral devices (via a firmware component) are connected), the memory sub-system configured to:
receive, by the firmware component and from the nonvolatile memory device, an encrypted first cryptographic key for encrypting or decrypting data stored on a memory of the memory sub-system
(FIG. 1 and 2, [0103], for initializing and operating the apparatus 10, particularly methods for automatic secure encryption of the hard disk 14; [0107], On the basis of the five read identification information W_1, W_2, ..., W_5 (which corresponds to a peripheral device among the number of peripheral devices 16, 18, 20, 22, 24 of FIG. 1, that is, by the firmware component), five key encryption keys KEK_1, KEK_2, ..., KEK_5 are generated in step S48; [0108] the next step S50 involves the five encrypted data encryption keys VDEK_1, VDEK_2, . . . , VDEK_5 (receive an encrypted first cryptographic key), stored in a memory area of the hard disk 14 (the nonvolatile memory from which an encrypted first cryptographic key is received), which have been generated by encrypting a data encryption key DEK (a first cryptographic key), generated in an initialization step for the apparatus 10, using the five key encryption keys KEK_1, KEK_2, ... , KEK_5 and have been written to the hard disk, being read; [0112], If it has been established in step S54 that the data encryption key DEK can be ascertained from at least three of the encrypted data encryption keys VDEK_1, VDEK_2, ... , VDEK_5, the method continues with step S56 and permits the access to the useful data (data to be encrypted or decrypted) stored on the hard disk 14 in encrypted form; FIG. 3, [0114], the hard disk controller performs the encryption. For this approach, the hard disk controller receives the key to encrypt the information, which is sent to and received from the hard disk; reading cryptographic keys and data from a hard disk and loading them into volatile memory (e.g., a RAM; a memory of the memory sub-system), for processing, that is, encrypting or decrypting data stored on a memory of the memory sub-system, is a routine implementation detail in contemporary operating system by the control unit 12, i.e., the memory sub-system);
decrypt, by the memory sub-system, the encrypted first cryptographic key; and
store the first cryptographic key in a volatile memory of the memory sub-system based at least in part on decrypting the encrypted first cryptographic key
(FIG. 1 and 2, [0109], Next, step S52 involves the data encryption key DEK being ascertained by decrypting the encrypted data encryption keys VDEK_1, VDEK_2, ..., VDEK_5 (decrypt the encrypted first cryptographic key) using the respective key encryption key KEK_1, KEK_2, ..., KEK_5 (via the control unit 12, i.e., the memory sub-system); [0112], If it has been established in step S54 that the data encryption key DEK (the first cryptographic key) can be ascertained from at least three of the encrypted data encryption keys VDEK_1, VDEK_2, ... , VDEK_5, the method continues with step S56 and permits the access to the useful data stored on the hard disk 14 in encrypted form; it is reasonable that the control unit 12 includes a volatile memory such as a RAM storing the DEKs (the first cryptographic key) decrypted from the VDEKs (based at least in part on decrypting the encrypted first cryptographic key)).
Per claim 7 (dependent on claim 1):
Von ‘415 discloses the elements detailed in the rejection of claim 1 above, incorporated herein by reference.
Von ‘415 discloses: The system of claim 1, wherein, to decrypt the encrypted first cryptographic key, the memory sub-system is configured to:
decrypt the encrypted first cryptographic key by a hardware component of the memory sub-system that is coupled with the firmware component
(FIG. 1 and 2, [0109], Next, step S52 involves the data encryption key DEK being ascertained by decrypting the encrypted data encryption keys VDEK_1, VDEK_2, ..., VDEK_5 (decrypt the encrypted first cryptographic key) using the respective key encryption key KEK_1, KEK_2, ..., KEK_5 (via the control unit 12, i.e., the memory sub-system that is coupled with the firmware component, such as a plurality of further peripheral devices as recited in [0097]); [0112], If it has been established in step S54 that the data encryption key DEK (the first cryptographic key) can be ascertained from at least three of the encrypted data encryption keys VDEK_1, VDEK_2, ... , VDEK_5, the method continues with step S56 and permits the access to the useful data stored on the hard disk 14 in encrypted form; it is reasonable that the control unit 12 includes a volatile memory (a hardware component) such as a RAM storing the DEKs (the first cryptographic key) decrypted from the VDEKs).
Per claim 8 (dependent on claim 7):
Von ‘415 discloses the elements detailed in the rejection of claim 7 above, incorporated herein by reference.
Von ‘415 discloses: The system of claim 7, wherein the hardware component comprises the volatile memory (FIG. 1 and 2, [0112], If it has been established in step S54 that the data encryption key DEK can be ascertained from at least three of the encrypted data encryption keys VDEK_1, VDEK_2, ... , VDEK_5, the method continues with step S56 and permits the access to the useful data stored on the hard disk 14 in encrypted form; it is reasonable that the control unit 12 includes the volatile memory (the hardware component) such as a RAM storing the DEKs (the first cryptographic key) decrypted from the VDEKs).
Per claim 9 (independent):
The limitations of the claim(s) correspond(s) to features of claim 1 and the claim(s) is/are rejected for the reasons detailed with respect to claim 1.
Per claim 15 (independent):
The limitations of the claim(s) correspond(s) to features of claim 1 and the claim(s) is/are rejected for the reasons detailed with respect to claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 10 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Von ‘415 as applied to claims 1, 9 and 15 above, and further in view of Hartley et al., US-20150100792-A1 (hereinafter “Hartley ‘792”).
Per claim 2 (dependent on claim 1):
Von ‘415 discloses the elements detailed in the rejection of claim 1 above, incorporated herein by reference.
Von ‘415 discloses: The system of claim 1, wherein, to store the first cryptographic key in the volatile memory, the memory sub-system is configured to:
store the cryptographic key in a volatile memory, configured to store cryptographic keys that encrypt data, based at least in part on the first cryptographic key being for encrypting the data stored on the memory; or
store the first cryptographic key in a volatile memory, configured to store cryptographic keys that decrypt data, based at least in part on the first cryptographic key being for decrypting the data stored on the memory
(FIG. 1 and 2, [0109], Next, step S52 involves the data encryption key DEK being ascertained by decrypting the encrypted data encryption keys VDEK_1, VDEK_2, ..., VDEK_5 (in subsequent to decrypting, the first cryptographic key is to be stored in a volatile memory of the control unit 12, where cryptographic keys can be stored) using the respective key encryption key KEK_1, KEK_2, ..., KEK_5 (via the control unit 12, i.e., the memory sub-system); [0112], If it has been established in step S54 that the data encryption key DEK (the first cryptographic key) can be ascertained from at least three of the encrypted data encryption keys VDEK_1, VDEK_2, ... , VDEK_5, the method continues with step S56 and permits the access to the useful data stored on the hard disk 14 in encrypted form – based at least in part on the first cryptographic key being for decrypting the data stored on the memory or for encrypting the data stored on the data stored on the memory; as recited in paragraph [0026], “The control unit is connected to a hard disk storing the digital data, which is to be encrypted and decrypted,” the system is capable of performing both encryption and decryption).
Von ‘415 does not disclose but Hartley ‘792 discloses: store the first cryptographic key in a first volatile memory; or store the first cryptographic key in a second volatile memory
(FIG. 2, [0020], The semiconductor device 10 further has a first key RAM 110 (a first volatile memory) associated with the first multimedia interface 100 for storing the first device key (the first cryptographic key) during run-time and a first key RAM controller 120 for restricting access to the first key RAM to exclusive access by the first multimedia interface 100. The semiconductor device 10 further has a second key RAM 111 (a second volatile memory) associated with second first multimedia interface 101 for storing the second device key (the first cryptographic key) during run-time and a second key RAM controller 121 for restricting access to the second key RAM to exclusive access by the second multimedia interface 101).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Von ‘415 with the storing each different device key to each respective RAM during run-time as taught by Hartley ‘792 because it would provide the flexibility by scaling a number of RAMs storing device keys used for different purposes and enabling individual security measures [0017][0020]. Additionally, Hartley ‘792 is analogous to the claimed invention because it teaches a semiconductor device having a plurality of on-chip processors capable to perform device key protected processing [0017].
Per claim 10 (dependent on claim 9):
Von ‘415 discloses the elements detailed in the rejection of claim 9 above, incorporated herein by reference.
The limitations of the claim(s) correspond(s) to features of claim 2 and the claim(s) is/are rejected for the reasons detailed with respect to claim 2.
Per claim 16 (dependent on claim 15):
Von ‘415 discloses the elements detailed in the rejection of claim 15 above, incorporated herein by reference.
The limitations of the claim(s) correspond(s) to features of claim 2 and the claim(s) is/are rejected for the reasons detailed with respect to claim 2.
Claim(s) 3, 11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Von ‘415 as applied to claims 1, 9 and 15 above, and further in view of Farhan et al., US-10185509-B1 (hereinafter “Farhan ‘509”) and Halcrow et al., US-10164955-B1 (hereinafter “Halcrow ‘955”).
Per claim 3 (dependent on claim 1):
Von ‘415 discloses the elements detailed in the rejection of claim 1 above, incorporated herein by reference.
Von ‘415 does not disclose but Farhan ‘509 discloses: The system of claim 1, wherein the memory sub-system is further configured to:
receive a command to erase the first cryptographic key and to generate a second cryptographic key;
generate the second cryptographic key based at least in part on receiving the command
(FIG. 4, [Col. 10], ll. 22-25, an example method 400 for initializing a storage device in an operational mode or a sanitization mode; [Col. 11], ll. 27-34, If the storage device is in the cryptographic erase mode, then at 416 the cryptographic erase command is processed (receive a command). Processing the cryptographic erase command can comprise deleting the cryptographic key (to erase the first cryptographic key) used to encrypt the data stored on the storage device. In at least one embodiment, processing the cryptographic erase command can comprise generating a new cryptographic key (to generate a second cryptographic key) and replacing the deleted cryptographic key with the new cryptographic key – generate the second cryptographic key based at least in part on receiving the command).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Von ‘415 with the replacement of the deleted cryptographic key with the new cryptographic key in reply to the cryptographic erase command as taught by Farhan ‘509 because the system would prevent unauthorized access to data by malicious users via restricting access to a cryptographic erase operation [Col. 1], ll.62 – [Col. 2], ll.3. Additionally, Farhan ‘509 is analogous to the claimed invention because it teaches initializing a storage device in an operational mode or a sanitization mode [Col. 10], ll. 22-25.
Von ‘415 in view of Farhan ‘509 does not disclose but Halcrow ‘955 discloses: store the second cryptographic key in the volatile memory based at least in part on generating the second cryptographic key ([Col. 10], ll. 14-39, The customer-supplied encryption key 122 (the second cryptographic key) may be thought of as a master key that opens a key map 230 that includes data resources 214 (stored on the memory resources 214) and their associated resource persistent keys 240. The key map 230 may be stored on non-volatile memory 224a associated with the cryptographic manager 220, while the customer-supplied encryption key 122 is temporarily stored on the volatile memory 224b (store the second cryptographic key in the volatile memory) associated with the cryptographic manager 220, for example, until the operation associated with the client request 120 is complete – based at least in part on generating the second cryptographic key).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Von ‘415 in view of Farhan ‘509 with the temporary store of the customer-supplied encryption key on the volatile memory until the operation of an access request is complete as taught by Halcrow ‘955 because a distributed system is impenetrable by unauthorized users ( e.g., hackers) preventing the client data from being accessed by the unauthorized users [Col. 7], ll.25-35. Additionally, Halcrow ‘955 is analogous to the claimed invention because it teaches receiving, at data processing hardware of the distributed storage system, a customer-supplied encryption key from a customer device (i.e., a client) [ABSTRACT].
Per claim 11 (dependent on claim 9):
Von ‘415 discloses the elements detailed in the rejection of claim 9 above, incorporated herein by reference.
The limitations of the claim(s) correspond(s) to features of claim 3 and the claim(s) is/are rejected for the reasons detailed with respect to claim 3.
Per claim 17 (dependent on claim 15):
Von ‘415 discloses the elements detailed in the rejection of claim 15 above, incorporated herein by reference.
The limitations of the claim(s) correspond(s) to features of claim 3 and the claim(s) is/are rejected for the reasons detailed with respect to claim 3.
Claim(s) 5, 13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Von ‘415 as applied to claims 1, 9 and 15 above, and further in view of Bshara et al., US-10740466-B1 (hereinafter “Bshara ‘466”).
Per claim 5 (dependent on claim 1):
Von ‘415 discloses the elements detailed in the rejection of claim 1 above, incorporated herein by reference.
Von ‘415 discloses: The system of claim 1, wherein the memory sub-system is further configured to:
receive, from the memory sub-system, a second cryptographic key; and
encrypt the first cryptographic key using the second cryptographic key
(FIG. 1 and 2, [0108] the next step S50 involves the five encrypted data encryption keys VDEK_1, VDEK_2, . . . , VDEK_5 (by encrypting the first cryptographic key), stored in a memory area of the hard disk 14, which have been generated by encrypting a data encryption key DEK, generated in an initialization step for the apparatus 10, using the five key encryption keys KEK_1, KEK_2, ... , KEK_5 (the second cryptographic key) – encrypt the first cryptographic key using the second cryptographic key – and have been written to the hard disk (thorough the memory sub-system, i.e., the control unit 12), being read).
Von ‘415 does not disclose but Bshara ‘466 discloses: receive, from one or more registers of the memory sub-system, a second cryptographic key (FIG. 2, [Col. 8], ll.64 – [Col. 9], ll.21, the cryptographic logic 104d may be configured to determine a cryptographic key … the cryptographic key (a second cryptographic key) may be stored in the on-chip memory 104b or in a register (a register of the integrated circuit 104 in FIG. 2, that is, one or more registers of the memory sub-system)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Von ‘415 with the storing of the cryptographic key in a register as taught by Bshara ‘466 because register values can usually be accessed much faster than RAM or NVM. Additionally, Bshara ‘466 is analogous to the claimed invention because it teaches the integrated circuit 104 configured to communicate with a data storage device and a data processing device using encrypted interfaces [FIG. 2].
Per claim 13 (dependent on claim 9):
Von ‘415 discloses the elements detailed in the rejection of claim 9 above, incorporated herein by reference.
The limitations of the claim(s) correspond(s) to features of claim 5 and the claim(s) is/are rejected for the reasons detailed with respect to claim 5.
Per claim 19 (dependent on claim 15):
Von ‘415 discloses the elements detailed in the rejection of claim 15 above, incorporated herein by reference.
The limitations of the claim(s) correspond(s) to features of claim 5 and the claim(s) is/are rejected for the reasons detailed with respect to claim 5.
Allowable Subject Matter
Claim(s) 4, 6, 12, 14, 18 and 20 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGSEOK PARK whose telephone number is (571)272-4332. The examiner can normally be reached Monday-Friday 7:30-5:30 and Alternate Fridays 9:00 am-5:00 pm.
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/SANGSEOK PARK/Primary Examiner, Art Unit 2499