DETAILED ACTION
INFORMATION CONCERNING RESPONSES
Response to Amendment
This Office Action is in response to applicant’s communication filed on June 3, 2026, in response to PTO Office Action mailed on March 6, 2026. The Applicant’s remarks and amendments to the claims and/or the specification were considered with the results that follow.
In response to the last Office Action, claims 1-5, 9-13, 17-21, and 24-25 have been amended. As a result, claims 1-25 are now pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on June 3, 2026, in response to PTO Office Action mailed on March 6, 2026, have been fully considered and are persuasive. Hence, the rejection has been withdrawn. However, upon further review a new ground of rejection has been made in view of Young (Publication Number US 2003/0014580 A1).
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 1, 5-9, 13-17, and 21-25 are rejected under 35 U.S.C. 103(a) as being unpatentable over Maturana et al. (Patent Number US 11,582,127 B2) in view of Young (Publication Number US 2003/0014580 A1).
As per claim 1, Maturana et al. discloses “A computer-implemented method of optimizing input/output (I/O) packet batch sizes, the method comprising: based on receiving a first I/O request, issuing, by processing circuitry via a data link layer, a data available notification to an I/O adapter (notification applications that generate and send notifications to specified client devices if any of the data satisfies a defined notification criterion, data transformation applications that transform or reformat the data to suit the needs of a target application (e.g., filtering, data reduction, anomaly detection, aggregation, compression, truncation, contextualization), or other such applications; Column 5, lines 25-32) to initiate communication of a data payload of the first I/O request between the I/O adapter and at least one data queue (queued data; Column 1, lines 23-36).” Maturana et al. discloses “determining by the processing circuitry via the data link layer based on the status indication, whether an adapter initiation command was utilized to transition an adapter state of the I/O adapter from a quiescent state to a busy state to process the data payload of the first I/O request (as it pertains to queued data and batch size; Column 1, lines 37-47).” Maturana et al. discloses “and based on a determination that the adapter initiation command was utilized, the processing circuitry increasing a current packet batch size applicable to a subsequent second I/O request (Column 1, lines 48-61).”
However, Maturana et al. does not disclose “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter.”
Young discloses “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter (where there exists a SCSI bus phase status register in a parallel SCSI host adapter integrated circuit; Paragraphs 0012-0013, 0027, and 0048).”
Young also discloses “by processing circuitry via a data link layer (through a SCSI bus phase status register read instruction in response to an active request signal; Paragraph 0012, 0027, and 0048).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Maturana et al. with elements of Young in order to generate an active acknowledge signal as soon as possible after an active request signal that minimizes delays [Paragraph 0008].
As per claims 5, 13, and 21, Young discloses “The method of Claim 1 (as disclosed by Maturana et al. and Young above), wherein the obtaining the status indication (Paragraphs 0012-0013, 0027, and 0048) includes executing an adapter abstraction layer firmware instruction to obtain the status indication (Paragraph 0007).”
As per claims 6, 14, and 22, Maturana et al. discloses “The method of Claim 1 (as disclosed by Maturana et al. and Young above), wherein: the at least one data queue includes a plurality of data queues for buffering data payloads of I/O requests (queued data; Column 1, lines 23-369).” Maturana et al. discloses “and the determining includes determining the adapter state of the I/O adapter is busy based on the I/O adapter communicating I/O data with any of the plurality of data queues (notification applications that generate and send notifications to specified client devices if any of the data satisfies a defined notification criterion, data transformation applications that transform or reformat the data to suit the needs of a target application (e.g., filtering, data reduction, anomaly detection, aggregation, compression, truncation, contextualization), or other such applications; Column 5, lines 25-32).”
As per claims 7 and 15, Maturana et al. discloses “The method of Claim 1 (as disclosed by Maturana et al. and Young above), further comprising: resetting the current packet batch size to an initial value based on the I/O adapter resuming an idle state (see initial or default batch size; Column 13, lines 21-44).”
As per claims 8, 16, and 23, Maturana et al. discloses “The method of Claim 1 (as disclosed by Maturana et al. and Young above), further comprising the processing circuitry iteratively optimizing the current packet batch size based on utilization of adapter initiation commands (FIG. 10).”
As per claim 9, Maturana et al. discloses “A computer program product, comprising: a storage device (external storage 2016 and HDD 2014; FIG. 20).” Maturana et al. discloses “and program code stored within the storage device and executable by processing circuitry of a data processing system to perform operations including: based on receiving a first I/O request, issuing, by the processing circuitry via a data link layer, a data available notification to an I/O adapter (notification applications that generate and send notifications to specified client devices if any of the data satisfies a defined notification criterion, data transformation applications that transform or reformat the data to suit the needs of a target application (e.g., filtering, data reduction, anomaly detection, aggregation, compression, truncation, contextualization), or other such applications; Column 5, lines 25-32) to initiate communication of a data payload of the first I/O request between an I/O adapter and at least one data queue (queued data; Column 1, lines 23-36).” Maturana et al. discloses “determining, by the processing circuitry via the data link layer based on the status indication, whether an adapter initiation command was utilized to transition the adapter state of the I/O adapter from a quiescent state to a busy state to process the data payload of the first I/O request (as it pertains to queued data and batch size; Column 1, lines 37-47).” Maturana et al. discloses “and based on a determination that the adapter initiation command was utilized, increasing a current packet batch size applicable to a subsequent second I/O write request (Column 1, lines 48-61).”
However, Maturana et al. does not disclose “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter.”
Young discloses “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter (where there exists a SCSI bus phase status register in a parallel SCSI host adapter integrated circuit; Paragraphs 0012-0013, 0027, and 0048).”
Young also discloses “by the processing circuitry via a data link layer (through a SCSI bus phase status register read instruction in response to an active request signal; Paragraph 0012, 0027, and 0048).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Maturana et al. with elements of Young in order to generate an active acknowledge signal as soon as possible after an active request signal that minimizes delays [Paragraph 0008].
As per claim 17, Maturana et al. discloses “A data processing system, comprising: processing circuitry (processing unit 2004; FIG. 20).” Maturana et al. discloses “and a storage device coupled to the processing circuitry (external storage 2016 and HDD 2014; FIG. 20), wherein the storage device includes program code executable by the processing circuitry to perform operations: based on receiving a first I/O request, issuing, by the processing circuitry via a data link layer, a data available notification to the I/O adapter (notification applications that generate and send notifications to specified client devices if any of the data satisfies a defined notification criterion, data transformation applications that transform or reformat the data to suit the needs of a target application (e.g., filtering, data reduction, anomaly detection, aggregation, compression, truncation, contextualization), or other such applications; Column 5, lines 25-32) to initiate communication of a data payload of the first I/O request between an I/O adapter and at least one data queue (queued data; Column 1, lines 23-36).” Maturana et al. discloses “determining, by the processing circuitry via the data link layer based on the status indication, whether an adapter initiation command was utilized to transition the adapter state of the I/O adapter from a quiescent state to a busy state to process the data payload of the first I/O request (as it pertains to queued data and batch size; Column 1, lines 37-47).” Maturana et al. discloses “and based on a determination that an adapter initiation command was utilized, increasing a current packet batch size applicable to a subsequent second I/O write request (Column 1, lines 48-61).”
However, Maturana et al. does not disclose “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter.”
Young discloses “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter (where there exists a SCSI bus phase status register in a parallel SCSI host adapter integrated circuit; Paragraphs 0012-0013, 0027, and 0048).”
Young also discloses “by processing circuitry via a data link layer (through a SCSI bus phase status register read instruction in response to an active request signal; Paragraph 0012, 0027, and 0048).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Maturana et al. with elements of Young in order to generate an active acknowledge signal as soon as possible after an active request signal that minimizes delays [Paragraph 0008].
As per claim 24, Maturana et al. discloses “A computer-implemented method of optimizing input/output (I/O) packet batch sizes, the method comprising: based on receiving a first I/O write request, issuing, by processing circuitry of a computer via a data link layer, a data available notification to an I/O adapter (notification applications that generate and send notifications to specified client devices if any of the data satisfies a defined notification criterion, data transformation applications that transform or reformat the data to suit the needs of a target application (e.g., filtering, data reduction, anomaly detection, aggregation, compression, truncation, contextualization), or other such applications; Column 5, lines 25-32) to initiate communication of a data payload of the first I/O write request from at least one data queue to the I/O adapter (queued data; Column 1, lines 23-36).” Maturana et al. discloses “determining, by the processing circuitry via the data link layer based on the status indication, whether an adapter initiation command was utilized to transition the adapter state of the I/O adapter from a quiescent state to a busy state to process the data payload of the first I/O write request (as it pertains to queued data and batch size; Column 1, lines 37-47).” Maturana et al. discloses “based on a determination that the adapter initiation command was utilized, the processing circuitry increasing a current packet batch size applicable to a subsequent second I/O write request (Column 1, lines 48-61).” Maturana et al. discloses “and the processing circuitry thereafter iteratively optimizing the current packet batch size based on utilization of adapter initiation commands (FIG. 10).”
However, Maturana et al. does not disclose “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter.”
Young discloses “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter (where there exists a SCSI bus phase status register in a parallel SCSI host adapter integrated circuit; Paragraphs 0012-0013, 0027, and 0048).”
Young also discloses “by processing circuitry via a data link layer (through a SCSI bus phase status register read instruction in response to an active request signal; Paragraph 0012, 0027, and 0048).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Maturana et al. with elements of Young in order to generate an active acknowledge signal as soon as possible after an active request signal that minimizes delays [Paragraph 0008].
As per claim 25, Maturana et al. discloses “A computer program product, comprising: a storage device (external storage 2016 and HDD 2014; FIG. 20).” Maturana et al. discloses “and program code stored within the storage device and executable by processing circuitry of a data processing system to perform operations including: based on receiving a first I/O write request, issuing, by the processing circuitry via a data link layer, a data available notification to an I/O adapter (notification applications that generate and send notifications to specified client devices if any of the data satisfies a defined notification criterion, data transformation applications that transform or reformat the data to suit the needs of a target application (e.g., filtering, data reduction, anomaly detection, aggregation, compression, truncation, contextualization), or other such applications; Column 5, lines 25-32) to initiate communication of a data payload of the first I/O write request from at least one data queue to the I/O adapter (queued data; Column 1, lines 23-36).” Maturana et al. discloses “determining, by the processing circuitry via the data link layer based on the status indication, whether an adapter initiation command was utilized to transition the adapter state of the I/O adapter from a quiescent state to a busy state to process the data payload of the first I/O write request (as it pertains to queued data and batch size; Column 1, lines 37-47).” Maturana et al. discloses “based on a determination that the adapter initiation command was utilized, increasing a current packet batch size applicable to a subsequent second I/O write request (Column 1, lines 48-61).” Maturana et al. discloses “and thereafter iteratively optimizing the current packet batch size based on utilization of adapter initiation commands (FIG. 10).”
However, Maturana et al. does not disclose “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter.”
Young discloses “obtaining, by the processing circuitry via the data link layer, from the I/O adapter, a status indication indicative of an adapter state of the I/O adapter (where there exists a SCSI bus phase status register in a parallel SCSI host adapter integrated circuit; Paragraphs 0012-0013, 0027, and 0048).”
Young also discloses “by processing circuitry via a data link layer (through a SCSI bus phase status register read instruction in response to an active request signal; Paragraph 0012, 0027, and 0048).”
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Maturana et al. with elements of Young in order to generate an active acknowledge signal as soon as possible after an active request signal that minimizes delays [Paragraph 0008].
Claims 2-4, 10-12, and 18-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Maturana et al. (Patent Number US 11,582,127 B2) and Young (Publication Number US 2003/0014580 A1) in view of Xu et al. (Publication Number US 2024/0111755 A1).
As per claims 2, 10, and 18, Maturana et al. and Young disclose “The method of Claim 1 (as disclosed by Maturana et al. and Young above).” However, while Maturana et al. disclose variable batch sizing [Column 1, lines 23-36], Maturana et al. and Young do not disclose “and further comprising: based on a determination that the adapter initiation command was not utilized, the processing circuitry retaining the current packet batch size.”
Xu et al. discloses “and further comprising: based on a determination that the adapter initiation command was not utilized, the processing circuitry retaining the current packet batch size (the batch size of reserved LSNs may be decreased by a certain amount or percentage when too many reserved LSNs for one or more resync write requests are not utilized [Paragraph 0048]. This is in view of the batch size changes if the one or more resync write requests in the 2PC queue have been exhausted; Paragraph 0048).”
Maturana et al. and Xu et al. are analogous art in that they in the field of batch size configuration.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Maturana et al. and Young with elements of Xu et al. to resolve unfairness in I/O performance of delayed storage I/O requests [Paragraph 0002].
As per claims 3, 11, and 19, Maturana et al. and Young disclose “The method of Claim 1 (as disclosed by Maturana et al. and Young above). However, while Maturana et al. disclose variable batch sizing [Column 1, lines 23-36], Maturana et al. and Young do not disclose “and further comprising: based on a determination that the adapter initiation command was not utilized, the processing circuitry decreasing the current packet batch size.”
Xu et al. discloses “and further comprising: based on a determination that the adapter initiation command was not utilized, the processing circuitry decreasing the current packet batch size (the batch size of reserved LSNs may be decreased by a certain amount or percentage when too many reserved LSNs for one or more resync write requests are not utilized; Paragraph 0048).”
Maturana et al. and Xu et al. are analogous art in that they in the field of batch size configuration.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements Maturana et al. and Young with elements of Xu et al. to resolve unfairness in I/O performance of delayed storage I/O requests [Paragraph 0002].
As per claims 4, 12, and 20, Maturana et al. and Young disclose “The method of Claim 1 (as disclosed by Maturana et al. and Young above). However, while Maturana et al. disclose variable batch sizing [Column 1, lines 23-36], Maturana et al. and Young do not disclose “wherein increasing the current packet batch size includes increasing the current packet batch size an amount based on a then-current CPU cost for processing the adapter initiation command.”
Xu et al. discloses “wherein increasing the current packet batch size includes increasing the current packet batch size an amount based on a then-current CPU cost for processing the adapter initiation command (the batch size of reserved LSNs may be increased by ten percent (10%) for subsequent resync write requests if the reserved LSNs for one or more resync write requests in the 2PC queue 310 have been exhausted; Paragraph 0048).”
Maturana et al. and Xu et al. are analogous art in that they in the field of batch size configuration.
Before the effective filing date of the claimed invention it would have been obvious to a person of ordinary skill in the art to combine the elements of Maturana et al. and Young with elements of Xu et al. to resolve unfairness in I/O performance of delayed storage I/O requests [Paragraph 0002].
RELEVENT ART CITED BY THE EXAMINER
The following prior art made of record and relied upon is citied to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
The following references teach data transfer as they pertain to status determination of a device/component:
U.S. PATENT NUMBERS:
2003/0079075 A1 – [Paragraph 0014]
2003/0167347 A1 – [Paragraph 0041 and 0049]
CONCLUDING REMARKS
Conclusions
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Yu whose telephone number is (571)272-9779. The examiner can normally be reached Monday - Friday.
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/H.W.Y/Examiner, Art Unit 2181 July 21, 2026
/IDRISS N ALROBAYE/Supervisory Patent Examiner, Art Unit 2181
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