DETAILED ACTION
Claim Objections
Claims 6 and 15 are objected to because of the phrase “at lease” (line 2) is mistyped. It should be amended to read as “at least”. Correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Huang et al. (US 2023/0336184) (cited by the applicant).
Regarding claim 1, Huang et al. (Figs. 1, 2, 4, 5) discloses an analog-to-digital conversion (ADC) apparatus having a data storage mechanism (Fig. 1), comprising:
at least one ADC conversion circuit (Abstract), comprising:
a conversion circuit (SAR ADC; para. [0002]), comprising:
a capacitor array circuit (capacitor array 2) configured to receive a pair of analog input voltages (Vin and Vip; Fig. 2) corresponding to a sampling stage (1 of Fig. 1) of a conversion process and perform a capacitor-switching operation corresponding to a conversion stage in the conversion process to generate a pair of analog output voltages (para. [0047]);
a comparison circuit (comparator 3) configured to in turn generate a plurality of comparison results according to the pair of analog output voltages in the conversion stage; and a capacitor control circuit configured to in turn control the capacitor array circuit to perform the capacitor-switching operation according to the comparison results by using a successive-approximation register (SAR) mechanism in the conversion stage (para. [0032]-[0034]);
a comparison results storage circuit (“comparison results” are known [e.g., see USP 10,177,779; col. 2, lines 36-40] to be stored in register of the SAR 4; para. [0034]) configured to store the comparison results; and
a calibration circuit (Digital error correction circuit 5) configured to retrieve the comparison results (bits B0 – B12) from the comparison results storage circuit to perform a digital error correction (DEC) according a plurality of weighting values to generate a digital output signal having a plurality of bits (bits D0 – D11) (see, Fig. 4 and para. [0060]).
Regarding claim 2, Huang et al. (Figs. 1, 2, 4, 5) discloses the analog-to-digital conversion apparatus of claim 1, wherein the conversion circuit (Fig. 1) operates according to a plurality of clock periods of a first clock signal (“clock”; para. [0047]), in which each of the plurality of clock periods comprises a sampling time (sampling phase) and a conversion time (conversion phase) after the sampling time; and
the conversion circuit performs the sampling stage of the conversion process in the sampling time (sampling phase) of a current clock period of the plurality of clock periods and performs the conversion stage of the conversion process in the conversion time (“After the sampling is completed, a comparison starts…”) of the current clock period (para. [0047][0048]).
Regarding claim 3, Huang et al. (Figs. 1, 2, 4, 5) discloses the analog-to-digital conversion apparatus of claim 2, wherein the calibration circuit (Digital error correction circuit 5) performs the digital error correction in a correction time (Step 3) after the current clock period corresponding to the conversion process (Step 2) performed in the current clock period (Fig. 4 and para. [0059]).
Regarding claim 10, Huang et al. (Figs. 1, 2, 4, 5) discloses an analog-to-digital conversion method having a data storage mechanism used in an analog-to-digital conversion apparatus (Abstract), comprising:
receiving a pair of analog input voltages (Vin and Vip; Fig. 2) corresponding to a sampling stage (sampling stage 1 of Fig. 1) of a conversion process and performing a capacitor-switching operation corresponding to a conversion stage in the conversion process to generate a pair of analog output voltages by a capacitor array circuit of a conversion circuit of at least one ADC conversion circuit (para. [004]);
in turn generating (by comparator 3) a plurality of comparison results according to the pair of analog output voltages in the conversion stage by a comparison circuit of the conversion circuit (para. [0048]);
in turn controlling (by the SAR 4 of Fig. 1) the capacitor array circuit (2) to perform the capacitor-switching operation according to the comparison results by using a successive-approximation register mechanism in the conversion stage by a capacitor control circuit of the conversion circuit (Abstract);
storing the comparison results (bits B0 – B12; Fig. 4) by a comparison results storage circuit (SAR 4) comprised by the at least one ADC conversion circuit (“comparison results” are known [e.g., see USP 10,177,779; col. 2, lines 36-40] to be stored in register of the SAR 4; para. [0034]); and
retrieving the comparison results (bits B0 – B12; Fig. 4) from the comparison results storage circuit (SAR 4) to perform a digital error correction (Digital correction circuit 5 of Fig. 1) according a plurality of weighting values to generate a digital output signal having a plurality of bits by a calibration circuit comprised by the at least one ADC conversion circuit (see, Fig. 4 and para. [0060]).
Regarding claim 11, Huang et al. (Figs. 1, 2, 4, 5) discloses the analog-to-digital conversion method of claim 10, further comprising: operating the conversion circuit (Fig. 1) according to a plurality of clock periods of a first clock signal (“clock”; para. [0047]), in which each of the plurality of clock periods comprises a sampling time (sampling phase) and a conversion time (conversion phase) after the sampling time; and performing the sampling stage of the conversion process in the sampling time (sampling phase) of a current clock period of the plurality of clock periods and performing the conversion stage of the conversion process in the conversion time (“After the sampling is completed, a comparison starts…”) of the current clock period by the conversion circuit (para. [0047][0048]).
Regarding claim 12, Huang et al. (Figs. 1, 2, 4, 5) discloses the analog-to-digital conversion method of claim 11, further comprising: performing the digital error correction in a correction time (Step 3) after the current clock period corresponding to the conversion process (Step 2) performed in the current clock period by the calibration circuit (Fig. 4 and para. [0059]).
Allowable Subject Matter
Claims 4-9 and 13-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, Huang et al. is not seen to disclose “the comparison results storage circuit operates according to a second clock signal having a second frequency the same as a first frequency of the first clock signal and a second phase different from a first phase of the first clock signal such that for each of the plurality of clock periods, the comparison results storage circuit stores the plurality of comparison results according to the second clock signal before the conversion time finishes”.
Regarding claim 5, Huang et al. is not seen to disclose “the comparison results storage circuit operates according to a plurality of second clock signals each having a second frequency the same as a first frequency of the first clock signal and a second phase different from a first phase of the first clock signal, and the second phase of each of the plurality of second clock signal is different from each other; and the plurality of comparison results are categorized into a plurality of comparison results groups, and a number of the plurality of second clock signals corresponds to a number of the plurality of comparison results groups such that for each of the plurality of clock periods, the comparison results storage circuit in turn stores the plurality of comparison results groups respectively according to the second phase of the plurality of second clock signals before the conversion time finishes”.
Regarding claim 6, Huang et al. is not seen to disclose “the comparison results storage circuit comprises a plurality of storage units each comprising at least [lease] one flip-flop, in which a number of the at least one flip-flop comprised by each of the plurality of storage units is the same, and the plurality of storage units respectively store the plurality of comparison results”.
Regarding claims 7-9, Huang et al. is not seen to disclose “a number of the analog-to-digital conversion circuit is an integer N larger than 1 to be configured as a time-interleaved analog-to-digital conversion circuit, the analog-to-digital conversion apparatus further comprises: an output storage circuit configured to store the N digital output signals generated by the N analog-to-digital conversion circuits; and a post-processing circuit configured to retrieve and process the N digital output signals from the output storage circuit to generate a final digital output signal”.
Regarding claim 13, Huang et al. is not seen to disclose “operating the comparison results storage circuit according to a second clock signal having a second frequency the same as a first frequency of the first clock signal and a second phase different from a first phase of the first clock signal such that for each of the plurality of clock periods, the comparison results storage circuit stores the plurality of comparison results according to the second clock signal before the conversion time finishes”.
Regarding claim 14, Huang et al. is not seen to disclose “operating the comparison results storage circuit according to a plurality of second clock signals each having a second frequency the same as a first frequency of the first clock signal and a second phase different from a first phase of the first clock signal, and the second phase of each of the plurality of second clock signal is different from each other; and the plurality of comparison results are categorized into a plurality of comparison results groups, and a number of the plurality of second clock signals corresponds to a number of the plurality of comparison results groups such that for each of the plurality of clock periods, the comparison results storage circuit in turn stores the plurality of comparison results groups respectively according to the second phase of the plurality of second clock signals before the conversion time finishes”.
Regarding claim 15, Huang et al. is not seen to disclose “the comparison results storage circuit comprises a plurality of storage units each comprising at least [lease] one flip-flop, in which a number of the at least one flip-flop comprised by each of the plurality of storage units is the same, the analog-to-digital conversion method further comprises: respectively storing the plurality of comparison results by the plurality of storage units”.
Regarding claims 16-18, Huang et al. is not seen to disclose “a number of the analog-to-digital conversion circuit is an integer N larger than 1 to be configured as a time-interleaved analog-to-digital conversion circuit, the analog-to-digital conversion method further comprises: storing the N digital output signals generated by the N analog-to-digital conversion circuits by an output storage circuit comprised by the analog-to-digital conversion apparatus; and retrieving and processing the N digital output signals from the output storage circuit to generate a final digital output signal by a post-processing circuit comprised by the analog-to-digital conversion apparatus”.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAI M NGUYEN whose telephone number is (571)272-1809. The examiner can normally be reached Mon-Fri: 8:00 am - 4:30pm.
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/KHAI M NGUYEN/Primary Examiner, Art Unit 2845
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