DETAILED ACTION
This FINAL action is in response to Application No. 18/960,989 originally filed 11/26/2024. The amendment presented on 06/24/2026 which provides amendments to claims 1 and 4-5 is hereby acknowledged.
Currently Claim(s) 1-12, 14-15, and 17 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 14 and 17 is objected to because of the following informalities: Claims 14 and 17 appears to have been amended however not indicated as amended. In addition, claim 14 states “The display device of claim 13, 4,” and claim 17 states “The level shifter of claim 16, 1,”. For purposes of this action, this appears to have been an accidental typographical mistake and the claim will be treated as a dependent of claim 4 and 1 respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5, 9-10, 12, 14-15, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohara et al. U.S. Patent Application Publication No. 2016/0210892 A1 hereinafter Ohara in view of Xu et al. U.S. Patent Application Publication No. 2017/0199403 A1 hereinafter Xu.
Consider Claim 1:
Ohara discloses a level shifter comprising: (Ohara, See Abstract.)
a first logic circuit configured to directly receive a mode selection signal of a first voltage level for selectively driving first and second light-emitting elements that emit light at … a pixel circuit from a timing controller and transmit the mode selection signal of the first voltage level, (Ohara, [0170-0175], [0207], “FIG. 28 is a block diagram showing a detailed configuration of a demultiplexer DM in the present embodiment. Note that the demultiplexer DM is composed of a CMOS circuit. As shown in FIG. 28, the demultiplexer DM is composed of two NOT circuits 811 and 812 and eight AND circuits 821 to 824 and 831 to 834. The NOT circuit 811 outputs a logically inverted signal of the selection signal CTL1. The NOT circuit 812 outputs a logically inverted signal of the selection signal CTL2. The AND circuit 821 outputs a signal indicating an AND of the output signal from the NOT circuit 811 and the output signal from the NOT circuit 812. The AND circuit 822 outputs a signal indicating an AND of the selection signal CTL1 and the output signal from the NOT circuit 812. The AND circuit 823 outputs a signal indicating an AND of the output signal from the NOT circuit 811 and the selection signal CTL2. The AND circuit 824 outputs a signal indicating an AND of the selection signal CTL1 and the selection signal CTL2. The AND circuit 831 outputs a signal indicating an AND of the output signal from the AND circuit 821 and the light-emission enable signal GGem. The AND circuit 832 outputs a signal indicating an AND of the output signal from the AND circuit 822 and the light-emission enable signal GGem. The AND circuit 833 outputs a signal indicating an AND of the output signal from the AND circuit 823 and the light-emission enable signal GGem. The AND circuit 834 outputs a signal indicating an AND of the output signal from the AND circuit 824 and the light-emission enable signal GGem.”)
wherein the first mode selection signal is different from the second mode selection signal; and a second logic circuit configured to convert the mode selection signal of the first voltage level into a converted mode selection signal of a second voltage level higher than the first voltage level and directly output the converted mode selection signal of the second voltage level to the pixel circuit through mode lines, (Ohara, [0207], “FIG. 28 is a block diagram showing a detailed configuration of a demultiplexer DM in the present embodiment. Note that the demultiplexer DM is composed of a CMOS circuit. As shown in FIG. 28, the demultiplexer DM is composed of two NOT circuits 811 and 812 and eight AND circuits 821 to 824 and 831 to 834. The NOT circuit 811 outputs a logically inverted signal of the selection signal CTL1. The NOT circuit 812 outputs a logically inverted signal of the selection signal CTL2. The AND circuit 821 outputs a signal indicating an AND of the output signal from the NOT circuit 811 and the output signal from the NOT circuit 812. The AND circuit 822 outputs a signal indicating an AND of the selection signal CTL1 and the output signal from the NOT circuit 812. The AND circuit 823 outputs a signal indicating an AND of the output signal from the NOT circuit 811 and the selection signal CTL2. The AND circuit 824 outputs a signal indicating an AND of the selection signal CTL1 and the selection signal CTL2. The AND circuit 831 outputs a signal indicating an AND of the output signal from the AND circuit 821 and the light-emission enable signal GGem. The AND circuit 832 outputs a signal indicating an AND of the output signal from the AND circuit 822 and the light-emission enable signal GGem. The AND circuit 833 outputs a signal indicating an AND of the output signal from the AND circuit 823 and the light-emission enable signal GGem. The AND circuit 834 outputs a signal indicating an AND of the output signal from the AND circuit 824 and the light-emission enable signal GGem.”)
wherein the first mode selection signal and the second mode selection signal have different values except during a switching process between the first mode and the second mode while the first mode selection signal and the second mode selection signal have a same value. (Ohara, [0211], “Next, a drive method of the present embodiment will be described on the basis of the above-described operation of the demultiplexers DM. FIG. 31 is a timing chart showing the waveforms of scanning signals provided to scanning signal lines SL, light-emission enable signals provided to the emission lines EM, and selection signals CTL1 and CTL2. As with the above-described first embodiment, a flyback period between two consecutive subframes is a black display period. During the black display period, the value of the selection signal CTL1 is set to 1 and the value of the selection signal CTL2 is set to 1. By this, during the black display period, all the emission lines EM go into a non-selected state and all organic EL elements OLED in a display unit 500 go into a light-off state. Note that at the end time point of each subframe, the value of a light-emission enable signal GGem outputted from the emission driver 400 is set to 0 based on a subframe reset signal SUBF_RST. Therefore, it is not necessarily required to set both the value of the selection signal CTL1 and the value of the selection signal CTL2 to 1 during the black display period. However, by setting both the value of the selection signal CTL1 and the value of the selection signal CTL2 to 1, all the emission lines EM can be securely brought into a non-selected state during the black display period.”)
Ohara, while providing multiple LEDs per pixel and dedicated selection lines provided directly from the timing controller, does not additionally appear to teach providing the pixels for different viewing angles. Thus, Ohara does not appear to expressly teach wherein the different viewing angles of the pixel circuit include a first viewing angle and a second viewing angle different from the first viewing angle, wherein the mode selection signal includes a first mode selection signal for a first mode corresponding to the first viewing angle and a second mode selection signal for a second mode corresponding to the second viewing angle.
Xu however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide multiple subpixels within a pixel for use in providing different viewing angels. Xu therefore teaches wherein the different viewing angles of the pixel circuit include a first viewing angle and a second viewing angle different from the first viewing angle, wherein the mode selection signal includes a first mode selection signal for a first mode corresponding to the first viewing angle and a second mode selection signal for a second mode corresponding to the second viewing angle. (Xu, [0017], “The two grating lines 1 are across upper and lower sides of the pixel components 3 to act as positive and negative electrodes of the conductive pixel films, and the signal line 2 is connected between the two grating lines. The two grating lines 1 are used for driving two display drivers 3 on the upper and lower sides of the pixel, respectively. When in narrow angle of view, the two grating lines 1 are shorted, and the two display drivers 30 are turned on; and when in a wide angle of view, the upper grating is disconnected from the lower grating line, the lower grating line is shorted to a potential Vgh, and the signal line is used for charging the pixel. The signal line 2 includes a connecting line 20 and a TFT source 22, wherein the TFT source 22 is perpendicular to the connecting line 20, and the TFT source 22 extends into the grating lines 1 and is imported into the display drivers 30 to connect the signal line 20 with the display drivers 30. Each of the display drivers 30 includes an active layer 301, an TFT drain 302 and a pixel through hole 303, wherein one end of the TFT drain 302 extends into the active layer 301 while the other end thereof extends into the conductive pixel films 32, and the pixel through hole 303 is formed at an extension end of the TFT drain 302. The two electrodes are embedded into the conductive pixel films 32 to apply a voltage for charging. An electric field is formed between the two electrodes, to control the orientation and tilt angle of the liquid crystal molecules in the conductive pixel films 32. The conductive pixel films 32 are electrically connected to the TFT drains 302 through the pixel through holes 303. When the TFT drains 302 are in a high potential, the conductive pixel films 32 are charged. The active layers are semiconductor layers (for example, a-Si, LTPS, IGZO, etc.).”)
It therefore would have been obvious to those having ordinary skill in the art in view of Xu to provide a functionality for multiple subpixels within a pixel to have different viewing angles as this was a know technique and would have been used for the art recognized purpose providing a richer view experience to audiences. In an existing pixel region, as a plurality of conductive pixel films are additionally provided and interspersed with each other, without increasing the accommodation space, the limited space of the pixel region is effectively utilized. (Xu, [0010])
Consider Claim 2:
Ohara in view of Xu discloses the level shifter of claim 1, wherein the second voltage level of the converted mode selection signal swings between a gate high voltage and a gate low voltage. (Xu, [0018], [0019], “In a preferred embodiment of the present invention, referring to FIG. 1, there are two display drivers 30 and two conductive pixel films 32, respectively. The display drivers 30 are an upper display driver 30a and a lower display driver 30b. When the upper display driver 30a and the lower display driver 30b are turned on simultaneously, the LCD display device is switched to a narrow-angle mode; and, when the upper display driver 30a or the lower display driver 30b is turned on separately, the LCD display device is switched to a wide-angle mode. The upper display driver 30a and the lower display driver 30b are controlled by different control signals, so that the drive states of the upper display driver 30a and the lower display driver 30b are controlled separately to realize a switchover between the wide-angle and narrow-angle display modes. With reference to FIG. 2 and FIG. 3, in panel control signal diagrams at different angles of view, when ctl1 is in a high potential and ctl2 is in a low potential, the upper display driver 30a and the lower display driver 30b are activated simultaneously, the two conductive pixel films 32 connected thereto are both turned on, and the LCD display device is in a narrow-angle state. When ctl1 is in a low potential and ctl2 is in a high potential, the upper display driver 30a or the lower display driver 30b is activated separately, the conductive pixel film 32 connected thereto is turned on separately, and the LCD display device is in a wide-angle state. By switching and controlling the voltage applied to the upper display driver and the voltage applied to the lower display driver, the direction of the electric field is changed, the angle of the orientation of liquid crystal molecules in the electric field is further changed, and the purpose of switching between the wide-angle mode and the narrow-angle mode is achieved. When ctl1 is in a high potential and ctl2 is in a low potential, both the upper display driver 30a and the lower display driver 30b are turned on, and the LCD display device enters a narrow-angle mode. When ctl1 is in a low potential and ctl2 is in a high potential, the upper display driver 30a is turned on, the lower display driver 30b is turned off, and the LCD display device enters a wide-angle mode.”)
Consider Claim 3:
Ohara in view of Xu discloses the level shifter of claim 2, wherein the second logic circuit receives the gate high voltage and the gate low voltage from a power supply. (Xu, [0018], [0019], “In a preferred embodiment of the present invention, referring to FIG. 1, there are two display drivers 30 and two conductive pixel films 32, respectively. The display drivers 30 are an upper display driver 30a and a lower display driver 30b. When the upper display driver 30a and the lower display driver 30b are turned on simultaneously, the LCD display device is switched to a narrow-angle mode; and, when the upper display driver 30a or the lower display driver 30b is turned on separately, the LCD display device is switched to a wide-angle mode. The upper display driver 30a and the lower display driver 30b are controlled by different control signals, so that the drive states of the upper display driver 30a and the lower display driver 30b are controlled separately to realize a switchover between the wide-angle and narrow-angle display modes. With reference to FIG. 2 and FIG. 3, in panel control signal diagrams at different angles of view, when ctl1 is in a high potential and ctl2 is in a low potential, the upper display driver 30a and the lower display driver 30b are activated simultaneously, the two conductive pixel films 32 connected thereto are both turned on, and the LCD display device is in a narrow-angle state. When ctl1 is in a low potential and ctl2 is in a high potential, the upper display driver 30a or the lower display driver 30b is activated separately, the conductive pixel film 32 connected thereto is turned on separately, and the LCD display device is in a wide-angle state. By switching and controlling the voltage applied to the upper display driver and the voltage applied to the lower display driver, the direction of the electric field is changed, the angle of the orientation of liquid crystal molecules in the electric field is further changed, and the purpose of switching between the wide-angle mode and the narrow-angle mode is achieved. When ctl1 is in a high potential and ctl2 is in a low potential, both the upper display driver 30a and the lower display driver 30b are turned on, and the LCD display device enters a narrow-angle mode. When ctl1 is in a low potential and ctl2 is in a high potential, the upper display driver 30a is turned on, the lower display driver 30b is turned off, and the LCD display device enters a wide-angle mode.”)
Consider Claim 15:
Ohara in view of Xu discloses the level shifter of claim 1, wherein the second viewing angle is smaller than the first viewing angle. (Xu, [0004], “The present invention provides an LCD display device with a switchable angle of view, including two grating lines, a signal line and pixel components, the signal line running between the two grating lines, wherein each group of the pixel components includes at least two display drivers and at least two conductive pixel films, the display drivers and the conductive pixel films being electrically connected to each other correspondingly; the display drivers are embedded into the grating lines, respectively, and are electrically connected to the grating lines; when the display drivers respectively disposed on different sides are turned on simultaneously, the LCD display device is switched to a narrow-angle mode; and, when one of the display drivers is turned on separately or the display drivers disposed on a same side are turned on simultaneously, the LCD display device is switched to a wide-angle mode.”)
Consider Claim 17:
Ohara in view of Xu discloses the level shifter of claim 1, wherein the first mode selection signal and the second mode selection signal have the same value for a predetermined time interval between a rising time point of the first mode selection signal and a falling time point of the second mode selection signal. (Ohara, [0211], “Next, a drive method of the present embodiment will be described on the basis of the above-described operation of the demultiplexers DM. FIG. 31 is a timing chart showing the waveforms of scanning signals provided to scanning signal lines SL, light-emission enable signals provided to the emission lines EM, and selection signals CTL1 and CTL2. As with the above-described first embodiment, a flyback period between two consecutive subframes is a black display period. During the black display period, the value of the selection signal CTL1 is set to 1 and the value of the selection signal CTL2 is set to 1. By this, during the black display period, all the emission lines EM go into a non-selected state and all organic EL elements OLED in a display unit 500 go into a light-off state. Note that at the end time point of each subframe, the value of a light-emission enable signal GGem outputted from the emission driver 400 is set to 0 based on a subframe reset signal SUBF_RST. Therefore, it is not necessarily required to set both the value of the selection signal CTL1 and the value of the selection signal CTL2 to 1 during the black display period. However, by setting both the value of the selection signal CTL1 and the value of the selection signal CTL2 to 1, all the emission lines EM can be securely brought into a non-selected state during the black display period.”)
Consider Claim 4:
Ohara discloses a display device comprising: (Ohara, See Abstract.)
a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits each including first and second light-emitting elements that emit light … are disposed, a data driver configured to supply a data voltage of pixel data to the data lines; (Ohara, [0130], “FIG. 2 is a block diagram showing an overall configuration of an active matrix-type organic EL display device 1 according to a first embodiment of the present invention. The organic EL display device 1 includes a display control circuit 100, a source driver (data line drive circuit) 200, a gate driver (scanning signal line drive circuit) 300, an emission driver 400, a display unit 500, and an emission signal input switching circuit 600. Note that the gate driver 300 and the emission driver 400 are formed in an organic EL panel 7 including the display unit 500 in the present embodiment. That is, the gate driver 300 and the emission driver 400 are monolithic. In addition, the organic EL display device 1 is provided with a logic power supply 390, a logic power supply 490, an organic EL high-level power supply 580, and an organic EL low-level power supply 590, as components for supplying various types of power supply voltages to the organic EL panel 7.”)
a level shifter configured to output a gate timing control signal and a mode selection signal, wherein the first mode selection signal is different from the second mode selection signal; (Ohara, [0141], “The emission signal input switching circuit 600 outputs selection signals SEL1, SEL2, and SEL3, based on the emission switching instruction signal Sem which is transmitted from the display control circuit 100. In the present embodiment, one of the three selection signals SEL1, SEL2, and SEL3 is brought to “active” (“high level” in the present embodiment) every subframe, based on the emission switching instruction signal Sem. Note that in the present embodiment a first control signal generating unit is implemented by the emission signal input switching circuit 600, and a first control signal is implemented by the selection signals SEL1, SEL2, and SEL3.”)
a gate driver configured to generate a gate signal based on the gate timing control signal and supply the gate signal to the gate lines; and (Ohara, [0173], “When the gate driver 300 brings the scanning signal line SL(1) in the first row into anon-selected state, the transistor T2 goes into an off state in each pixel circuit 50 in the first row. By this, a gate-source voltage Vgs held in the capacitor Cst is fixed. In each pixel circuit 50 in the first row, a drive current according to the magnitude of the gate-source voltage Vgs flows between the drain and source of the transistor T1. Since the transistor T3 is in an on state in the first subframe SF1 as described above, the drive current is supplied to the organic EL element OLED(R) through the transistor T3 in each pixel circuit 50 in the first row.”)
a timing controller configured to control the data driver, the level shifter and the gate driver, wherein the timing controller generates a mode selection signal of a first voltage level for selectively driving the first and second light-emitting elements of the pixel circuits and directly transmits the generated mode selection signal of the first voltage level to the level shifter, and (Ohara, [0170-0175], [0207], “FIG. 28 is a block diagram showing a detailed configuration of a demultiplexer DM in the present embodiment. Note that the demultiplexer DM is composed of a CMOS circuit. As shown in FIG. 28, the demultiplexer DM is composed of two NOT circuits 811 and 812 and eight AND circuits 821 to 824 and 831 to 834. The NOT circuit 811 outputs a logically inverted signal of the selection signal CTL1. The NOT circuit 812 outputs a logically inverted signal of the selection signal CTL2. The AND circuit 821 outputs a signal indicating an AND of the output signal from the NOT circuit 811 and the output signal from the NOT circuit 812. The AND circuit 822 outputs a signal indicating an AND of the selection signal CTL1 and the output signal from the NOT circuit 812. The AND circuit 823 outputs a signal indicating an AND of the output signal from the NOT circuit 811 and the selection signal CTL2. The AND circuit 824 outputs a signal indicating an AND of the selection signal CTL1 and the selection signal CTL2. The AND circuit 831 outputs a signal indicating an AND of the output signal from the AND circuit 821 and the light-emission enable signal GGem. The AND circuit 832 outputs a signal indicating an AND of the output signal from the AND circuit 822 and the light-emission enable signal GGem. The AND circuit 833 outputs a signal indicating an AND of the output signal from the AND circuit 823 and the light-emission enable signal GGem. The AND circuit 834 outputs a signal indicating an AND of the output signal from the AND circuit 824 and the light-emission enable signal GGem.”)
wherein the level shifter includes: a first logic circuit configured to receive the mode selection signal of the first voltage level from the timing controller and transmit the mode selection signal; and (Ohara, [0207], “FIG. 28 is a block diagram showing a detailed configuration of a demultiplexer DM in the present embodiment. Note that the demultiplexer DM is composed of a CMOS circuit. As shown in FIG. 28, the demultiplexer DM is composed of two NOT circuits 811 and 812 and eight AND circuits 821 to 824 and 831 to 834. The NOT circuit 811 outputs a logically inverted signal of the selection signal CTL1. The NOT circuit 812 outputs a logically inverted signal of the selection signal CTL2. The AND circuit 821 outputs a signal indicating an AND of the output signal from the NOT circuit 811 and the output signal from the NOT circuit 812. The AND circuit 822 outputs a signal indicating an AND of the selection signal CTL1 and the output signal from the NOT circuit 812. The AND circuit 823 outputs a signal indicating an AND of the output signal from the NOT circuit 811 and the selection signal CTL2. The AND circuit 824 outputs a signal indicating an AND of the selection signal CTL1 and the selection signal CTL2. The AND circuit 831 outputs a signal indicating an AND of the output signal from the AND circuit 821 and the light-emission enable signal GGem. The AND circuit 832 outputs a signal indicating an AND of the output signal from the AND circuit 822 and the light-emission enable signal GGem. The AND circuit 833 outputs a signal indicating an AND of the output signal from the AND circuit 823 and the light-emission enable signal GGem. The AND circuit 834 outputs a signal indicating an AND of the output signal from the AND circuit 824 and the light-emission enable signal GGem.”)
a second logic circuit configured to convert the mode selection signal of the first voltage level into a converted mode selection signal of a second voltage level higher than the first voltage level and directly output the converted mode selection signal of the second voltage level to the pixel circuits through mode lines. (Ohara, [0211], “Next, a drive method of the present embodiment will be described on the basis of the above-described operation of the demultiplexers DM. FIG. 31 is a timing chart showing the waveforms of scanning signals provided to scanning signal lines SL, light-emission enable signals provided to the emission lines EM, and selection signals CTL1 and CTL2. As with the above-described first embodiment, a flyback period between two consecutive subframes is a black display period. During the black display period, the value of the selection signal CTL1 is set to 1 and the value of the selection signal CTL2 is set to 1. By this, during the black display period, all the emission lines EM go into a non-selected state and all organic EL elements OLED in a display unit 500 go into a light-off state. Note that at the end time point of each subframe, the value of a light-emission enable signal GGem outputted from the emission driver 400 is set to 0 based on a subframe reset signal SUBF_RST. Therefore, it is not necessarily required to set both the value of the selection signal CTL1 and the value of the selection signal CTL2 to 1 during the black display period. However, by setting both the value of the selection signal CTL1 and the value of the selection signal CTL2 to 1, all the emission lines EM can be securely brought into a non-selected state during the black display period.”)
Ohara, while providing multiple LEDs per pixel and dedicated selection lines provided directly from the timing controller, does not additionally appear to teach providing the pixels for different viewing angles. Thus, Ohara does not appear to expressly teach a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits each including first and second light-emitting elements that emit light at different viewing angles are disposed, wherein the different viewing angles of the pixel circuits include a first viewing angle and a second viewing angle different from the first viewing angle; wherein the mode selection signal includes a first mode selection signal for a first mode corresponding to the first viewing angle and a second mode selection signal for a second mode corresponding to the second viewing angle.
Xu however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide multiple subpixels within a pixel for use in providing different viewing angels. Xu therefore teaches a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits each including first and second light-emitting elements that emit light at different viewing angles are disposed, wherein the different viewing angles of the pixel circuits include a first viewing angle and a second viewing angle different from the first viewing angle; wherein the mode selection signal includes a first mode selection signal for a first mode corresponding to the first viewing angle and a second mode selection signal for a second mode corresponding to the second viewing angle. (Xu, [0017], “The two grating lines 1 are across upper and lower sides of the pixel components 3 to act as positive and negative electrodes of the conductive pixel films, and the signal line 2 is connected between the two grating lines. The two grating lines 1 are used for driving two display drivers 3 on the upper and lower sides of the pixel, respectively. When in narrow angle of view, the two grating lines 1 are shorted, and the two display drivers 30 are turned on; and when in a wide angle of view, the upper grating is disconnected from the lower grating line, the lower grating line is shorted to a potential Vgh, and the signal line is used for charging the pixel. The signal line 2 includes a connecting line 20 and a TFT source 22, wherein the TFT source 22 is perpendicular to the connecting line 20, and the TFT source 22 extends into the grating lines 1 and is imported into the display drivers 30 to connect the signal line 20 with the display drivers 30. Each of the display drivers 30 includes an active layer 301, an TFT drain 302 and a pixel through hole 303, wherein one end of the TFT drain 302 extends into the active layer 301 while the other end thereof extends into the conductive pixel films 32, and the pixel through hole 303 is formed at an extension end of the TFT drain 302. The two electrodes are embedded into the conductive pixel films 32 to apply a voltage for charging. An electric field is formed between the two electrodes, to control the orientation and tilt angle of the liquid crystal molecules in the conductive pixel films 32. The conductive pixel films 32 are electrically connected to the TFT drains 302 through the pixel through holes 303. When the TFT drains 302 are in a high potential, the conductive pixel films 32 are charged. The active layers are semiconductor layers (for example, a-Si, LTPS, IGZO, etc.).”)
It therefore would have been obvious to those having ordinary skill in the art in view of Xu to provide a functionality for multiple subpixels within a pixel to have different viewing angles as this was a know technique and would have been used for the art recognized purpose providing a richer view experience to audiences. In an existing pixel region, as a plurality of conductive pixel films are additionally provided and interspersed with each other, without increasing the accommodation space, the limited space of the pixel region is effectively utilized. (Xu, [0010])
Consider Claim 5:
Ohara in view of Xu discloses the level shifter and the pixel circuits of the display device of claim 4, wherein the level shifter and the pixel circuits are electrically connected through the mode lines, and wherein the mode selection signal of the second voltage level outputted from the level shifter is applied to the pixel circuits through the mode lines. (Ohara, [0150], “FIG. 1 is a circuit diagram showing a configuration of a main part (a configuration of a portion between a pixel circuit 50 and the emission driver 400) in the present embodiment. As can be grasped from FIGS. 1 and 2, in the present embodiment, three emission lines EM (a first emission line EM1, a second emission line EM2, and a third emission line EM3) are provided for each row. As shown in FIG. 1, transistors Tem1 to Tem3 whose on/off states are controlled by selection signals SEL1 to SEL3, respectively, are provided between the emission driver 400 and the first to third emission lines EM1 to EM3. Light-emission enable signal supply control transistors are implemented by the transistors Tem1 to Tem3. The transistor Tem1 has a gate terminal to which the selection signal SEL1 is provided, a drain terminal connected to the emission driver 400, and a source terminal connected to the first emission line EM1. The transistor Tem2 has a gate terminal to which the selection signal SEL2 is provided, a drain terminal connected to the emission driver 400, and a source terminal connected to the second emission line EM2. The transistor Tem3 has a gate terminal to which the selection signal SEL3 is provided, a drain terminal connected to the emission driver 400, and a source terminal connected to the third emission line EM3.”)
Consider Claim 9:
Ohara in view of Xu discloses the display device of claim 4, wherein the second voltage level of the converted mode selection signal swings between a gate high voltage and a gate low voltage. (Xu, [0018], [0019], “In a preferred embodiment of the present invention, referring to FIG. 1, there are two display drivers 30 and two conductive pixel films 32, respectively. The display drivers 30 are an upper display driver 30a and a lower display driver 30b. When the upper display driver 30a and the lower display driver 30b are turned on simultaneously, the LCD display device is switched to a narrow-angle mode; and, when the upper display driver 30a or the lower display driver 30b is turned on separately, the LCD display device is switched to a wide-angle mode. The upper display driver 30a and the lower display driver 30b are controlled by different control signals, so that the drive states of the upper display driver 30a and the lower display driver 30b are controlled separately to realize a switchover between the wide-angle and narrow-angle display modes. With reference to FIG. 2 and FIG. 3, in panel control signal diagrams at different angles of view, when ctl1 is in a high potential and ctl2 is in a low potential, the upper display driver 30a and the lower display driver 30b are activated simultaneously, the two conductive pixel films 32 connected thereto are both turned on, and the LCD display device is in a narrow-angle state. When ctl1 is in a low potential and ctl2 is in a high potential, the upper display driver 30a or the lower display driver 30b is activated separately, the conductive pixel film 32 connected thereto is turned on separately, and the LCD display device is in a wide-angle state. By switching and controlling the voltage applied to the upper display driver and the voltage applied to the lower display driver, the direction of the electric field is changed, the angle of the orientation of liquid crystal molecules in the electric field is further changed, and the purpose of switching between the wide-angle mode and the narrow-angle mode is achieved. When ctl1 is in a high potential and ctl2 is in a low potential, both the upper display driver 30a and the lower display driver 30b are turned on, and the LCD display device enters a narrow-angle mode. When ctl1 is in a low potential and ctl2 is in a high potential, the upper display driver 30a is turned on, the lower display driver 30b is turned off, and the LCD display device enters a wide-angle mode.”
Consider Claim 10:
Ohara in view of Xu discloses the display device of claim 9, wherein the second logic circuit receives the gate high voltage and the gate low voltage from a power supply. (Xu, [0018], [0019], “In a preferred embodiment of the present invention, referring to FIG. 1, there are two display drivers 30 and two conductive pixel films 32, respectively. The display drivers 30 are an upper display driver 30a and a lower display driver 30b. When the upper display driver 30a and the lower display driver 30b are turned on simultaneously, the LCD display device is switched to a narrow-angle mode; and, when the upper display driver 30a or the lower display driver 30b is turned on separately, the LCD display device is switched to a wide-angle mode. The upper display driver 30a and the lower display driver 30b are controlled by different control signals, so that the drive states of the upper display driver 30a and the lower display driver 30b are controlled separately to realize a switchover between the wide-angle and narrow-angle display modes. With reference to FIG. 2 and FIG. 3, in panel control signal diagrams at different angles of view, when ctl1 is in a high potential and ctl2 is in a low potential, the upper display driver 30a and the lower display driver 30b are activated simultaneously, the two conductive pixel films 32 connected thereto are both turned on, and the LCD display device is in a narrow-angle state. When ctl1 is in a low potential and ctl2 is in a high potential, the upper display driver 30a or the lower display driver 30b is activated separately, the conductive pixel film 32 connected thereto is turned on separately, and the LCD display device is in a wide-angle state. By switching and controlling the voltage applied to the upper display driver and the voltage applied to the lower display driver, the direction of the electric field is changed, the angle of the orientation of liquid crystal molecules in the electric field is further changed, and the purpose of switching between the wide-angle mode and the narrow-angle mode is achieved. When ctl1 is in a high potential and ctl2 is in a low potential, both the upper display driver 30a and the lower display driver 30b are turned on, and the LCD display device enters a narrow-angle mode. When ctl1 is in a low potential and ctl2 is in a high potential, the upper display driver 30a is turned on, the lower display driver 30b is turned off, and the LCD display device enters a wide-angle mode.”
Consider Claim 12:
Ohara in view of Xu discloses the display device of claim 4, wherein the second viewing angle is smaller than the first viewing angle. (Xu, [0004], “The present invention provides an LCD display device with a switchable angle of view, including two grating lines, a signal line and pixel components, the signal line running between the two grating lines, wherein each group of the pixel components includes at least two display drivers and at least two conductive pixel films, the display drivers and the conductive pixel films being electrically connected to each other correspondingly; the display drivers are embedded into the grating lines, respectively, and are electrically connected to the grating lines; when the display drivers respectively disposed on different sides are turned on simultaneously, the LCD display device is switched to a narrow-angle mode; and, when one of the display drivers is turned on separately or the display drivers disposed on a same side are turned on simultaneously, the LCD display device is switched to a wide-angle mode.”)
Consider Claim 14:
Ohara in view of Xu discloses the display device of claim 13, 4, wherein the first mode selection signal and the second mode selection signal have the same value for a predetermined time interval between a rising time point of the first mode selection signal and a falling time point of the second mode selection signal. (Ohara, [0211], “Next, a drive method of the present embodiment will be described on the basis of the above-described operation of the demultiplexers DM. FIG. 31 is a timing chart showing the waveforms of scanning signals provided to scanning signal lines SL, light-emission enable signals provided to the emission lines EM, and selection signals CTL1 and CTL2. As with the above-described first embodiment, a flyback period between two consecutive subframes is a black display period. During the black display period, the value of the selection signal CTL1 is set to 1 and the value of the selection signal CTL2 is set to 1. By this, during the black display period, all the emission lines EM go into a non-selected state and all organic EL elements OLED in a display unit 500 go into a light-off state. Note that at the end time point of each subframe, the value of a light-emission enable signal GGem outputted from the emission driver 400 is set to 0 based on a subframe reset signal SUBF_RST. Therefore, it is not necessarily required to set both the value of the selection signal CTL1 and the value of the selection signal CTL2 to 1 during the black display period. However, by setting both the value of the selection signal CTL1 and the value of the selection signal CTL2 to 1, all the emission lines EM can be securely brought into a non-selected state during the black display period.”)
Claim Rejections - 35 USC § 103
Claim(s) 6-8 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ohara et al. U.S. Patent Application Publication No. 2016/0210892 A1 in view of Xu et al. U.S. Patent Application Publication No. 2017/0199403 A1 as applied to claim 5 above, and further in view of Cho et al. U.S. Patent Application Publication No. 2021/0183319 A1 hereinafter Cho.
Consider Claim 6:
Ohara in view of Xu discloses the display device of claim 5, however Cho further teaches wherein the level shifter is disposed in a control printed circuit board (CPCB), and the mode lines pass through a flexible printed circuit (FPC), a source printed circuit board (SPCB), and a chip on film (COF) and then are connected to the pixel circuits through a non-display area of the display panel. (Cho, [0041], “Referring to FIGS. 1 to 4, the source driver may receive the intra-interface signal IIFS from the timing controller TCON. The source driver may generate data driving signal based on the source driving bit information included in the intra-interface signal IIFS and may supply the data driving signal to the data lines DL. The source driver may include a plurality of source integrated circuits SICs installed on a conductive film. The conductive film may be a chip on film (COF), but the present disclosure is not limited thereto. The conductive film may be embodied as a tape carrier package (TCP) instead of a chip on film (COF). The source printed circuit board (SPCB) may be electrically connected to the display panel PNL through the conductive film COF and may also be electrically connected to the control board CBD through a cable CBL. The source printed circuit board (SPCB) may be configured in a singular or plural number. The cable CBL may be connected to the source printed circuit board (SPCB) and the control board CBD through a connector. The number of the cable CBL may be the same as the number of the source printed circuit boards (SPCBs), but the present disclosure is not limited thereto.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide portions of the display hardware located in non-display area outside of the display panel itself as this was known technique in view of Cho and would have been utilized for the art recognized purpose solving the issues related to the number of output pins of the timing controller being high, and the areas of a connection cable, a connector, and a source printed circuit board (SPCB) used as a transmission path are also high. In addition, the number of information for driving a gate has increased due to various functions of a display device, and thus, a circuit for signal transmission has been complicated and an installation area thereof has increased. (Cho, [0005])
Consider Claim 7:
Ohara in view of Xu in view of Cho discloses the display device of claim 6, wherein the mode lines are arranged side by side in the non-display area of the display panel and are arranged in parallel with the gate lines in a display area of the display panel. (Ohara, [0132], “FIG. 3 is a diagram for describing a configuration of the display unit 500 in the present embodiment. In the display unit 500, as shown in FIG. 3, m data lines DL(1) to DL(m) and n scanning signal lines SL(1) to SL(n) are disposed so as to intersect each other. Pixel circuits 50 are provided at the respective intersections of the data lines DL(1) to DL(m) and the scanning signal lines SL(1) to SL(n). That is, in the display unit 500, the pixel circuits 50 are arranged in a matrix form so as to form a plurality of rows (n rows) and a plurality of columns (m columns). In addition, in the display unit 500, n first emission lines EM1(1) to EM1(n), n second emission lines EM2(1) to EM2(n), and n third emission lines EM3(1) to EM3(n) are disposed for the respective n scanning signal lines SL(1) to SL(n). Furthermore, in the display unit 500, high-level power supply lines ELVDD and low-level power supply lines ELVSS are disposed. In the present embodiment, a first power supply line is implemented by the high-level power supply lines ELVDD, and a second power supply line is implemented by the low-level power supply lines ELVSS. A detailed configuration of the pixel circuits 50 will be described later.”)
Consider Claim 8:
Cho in view of Chun in view of Cho discloses the display device of claim 6, wherein the mode lines are arranged side by side in the non-display area of the display panel and are arranged in parallel with the data lines in a display area of the display panel. (Ohara, [0132], “FIG. 3 is a diagram for describing a configuration of the display unit 500 in the present embodiment. In the display unit 500, as shown in FIG. 3, m data lines DL(1) to DL(m) and n scanning signal lines SL(1) to SL(n) are disposed so as to intersect each other. Pixel circuits 50 are provided at the respective intersections of the data lines DL(1) to DL(m) and the scanning signal lines SL(1) to SL(n). That is, in the display unit 500, the pixel circuits 50 are arranged in a matrix form so as to form a plurality of rows (n rows) and a plurality of columns (m columns). In addition, in the display unit 500, n first emission lines EM1(1) to EM1(n), n second emission lines EM2(1) to EM2(n), and n third emission lines EM3(1) to EM3(n) are disposed for the respective n scanning signal lines SL(1) to SL(n). Furthermore, in the display unit 500, high-level power supply lines ELVDD and low-level power supply lines ELVSS are disposed. In the present embodiment, a first power supply line is implemented by the high-level power supply lines ELVDD, and a second power supply line is implemented by the low-level power supply lines ELVSS. A detailed configuration of the pixel circuits 50 will be described later.”)
Consider Claim 11:
Ohara in view of Xu discloses the display device of claim 4, however Cho further teaches wherein the level shifter is disposed in any one of a control printed circuit board (CPCB), a source printed circuit board (SPCB), and a driver integrated circuit (DIC). (Cho, [0041], “Referring to FIGS. 1 to 4, the source driver may receive the intra-interface signal IIFS from the timing controller TCON. The source driver may generate data driving signal based on the source driving bit information included in the intra-interface signal IIFS and may supply the data driving signal to the data lines DL. The source driver may include a plurality of source integrated circuits SICs installed on a conductive film. The conductive film may be a chip on film (COF), but the present disclosure is not limited thereto. The conductive film may be embodied as a tape carrier package (TCP) instead of a chip on film (COF). The source printed circuit board (SPCB) may be electrically connected to the display panel PNL through the conductive film COF and may also be electrically connected to the control board CBD through a cable CBL. The source printed circuit board (SPCB) may be configured in a singular or plural number. The cable CBL may be connected to the source printed circuit board (SPCB) and the control board CBD through a connector. The number of the cable CBL may be the same as the number of the source printed circuit boards (SPCBs), but the present disclosure is not limited thereto.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide portions of the display hardware located in non-display area outside of the display panel itself as this was known technique in view of Cho and would have been utilized for the art recognized purpose solving the issues related to the number of output pins of the timing controller being high, and the areas of a connection cable, a connector, and a source printed circuit board (SPCB) used as a transmission path are also high. In addition, the number of information for driving a gate has increased due to various functions of a display device, and thus, a circuit for signal transmission has been complicated and an installation area thereof has increased. (Cho, [0005])
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
Applicant Representatives are reminded of CFR 1.4(d)(2)(ii) which states “A patent practitioner (§ 1.32(a)(1) ), signing pursuant to §§ 1.33(b)(1) or 1.33(b)(2), must supply his/her registration number either as part of the S-signature, or immediately below or adjacent to the S-signature. The number (#) character may be used only as part of the S-signature when appearing before a practitioner’s registration number; otherwise the number character may not be used in an S-signature.” When an unsigned or improperly signed amendment is received the amendment will be listed in the contents of the application file, but not entered. The examiner will notify applicant of the status of the application, advising him or her to furnish a duplicate amendment properly signed or to ratify the amendment already filed. In an application not under final rejection, applicant should be given a two month time period in which to ratify the previously filed amendment (37 CFR 1.135(c) ).
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J JANSEN II whose telephone number is (571)272-5604. The examiner can normally be reached Normally Available Monday-Friday 9am-4pm EST.
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626
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