DETAILED ACTION
This communication is in response to Application No. 18/960,989 originally filed 11/26/2024. The Request for Continued Examination and Amendment presented on 01/16/2026 which provides amendments to claims 1, 4, 14, and 17 and claims 13 and 16 are cancelled is hereby acknowledged. Currently claims 1-12, 14-15, and 17 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/16/2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12, 14-15, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The Office notes that amendments to claim 1 and claim 4 are different in scope and thus the rejection applied below is in view of the language now presented.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. U.S. Patent Application Publication No. 2021/0183319 A1 hereinafter Cho in view of Chun et al. U.S. Patent Application Publication No. 2025/0022420 A1 hereinafter Chun in view of Ji et al. U.S. Patent Application Publication No. 2024/0178198 A1 hereinafter Ji.
Consider Claim 1:
Cho discloses a level shifter comprising: (Cho, See Abstract.)
a first logic circuit configured to receive a mode selection signal of a first voltage level for selectively driving first and second light-emitting elements that emit light at different viewing angles of a pixel circuit from a timing controller and transmit the mode selection signal of the first voltage level, (Cho, [0057], “Referring to FIG. 6, the level shifter LS may include a LVDS receiver LVDS Rx, a GD restorer, and a voltage shifting circuit. The LVDS receiver LVDS Rx may receive the logic timing information GD of the gate control signal in the LVDS interface form. The GD restorer may process the logic timing information GD of the gate control signal received in the LVDS interface form every 1 line quantity and may generate the gate control logic signal LGDC. The LVDS receiver LVDS Rx may be integrated into the GD restorer. In this case, a function of the LVDS receiver LVDS Rx may be performed by the GD restorer. As shown in FIG. 8, the voltage shifting circuit may boost a voltage swing width of the gate control logic signal LGDC, which swings between 0 V to 3.3 V, and may generate the gate control signal GDC that swings between a gate-on voltage VGH and a gate-off voltage VGL. The gate-on voltage VGH and the gate-off voltage VGL may be voltages required for an operation of a switching device included in pixels of the display panel. The gate-on voltage VGH may be a voltage (e.g., 25 V of FIG. 8) for turning on the switching device, and the gate-off voltage VGL may be a voltage (e.g., −5 V of FIG. 8) for turning off the switching device.”)
a second logic circuit configured to convert the mode selection signal of the first voltage level into a converted mode selection signal of a second voltage level higher than the first voltage level and output the converted mode selection signal of the second voltage level to the pixel circuit. (Cho, [0057], “Referring to FIG. 6, the level shifter LS may include a LVDS receiver LVDS Rx, a GD restorer, and a voltage shifting circuit. The LVDS receiver LVDS Rx may receive the logic timing information GD of the gate control signal in the LVDS interface form. The GD restorer may process the logic timing information GD of the gate control signal received in the LVDS interface form every 1 line quantity and may generate the gate control logic signal LGDC. The LVDS receiver LVDS Rx may be integrated into the GD restorer. In this case, a function of the LVDS receiver LVDS Rx may be performed by the GD restorer. As shown in FIG. 8, the voltage shifting circuit may boost a voltage swing width of the gate control logic signal LGDC, which swings between 0 V to 3.3 V, and may generate the gate control signal GDC that swings between a gate-on voltage VGH and a gate-off voltage VGL. The gate-on voltage VGH and the gate-off voltage VGL may be voltages required for an operation of a switching device included in pixels of the display panel. The gate-on voltage VGH may be a voltage (e.g., 25 V of FIG. 8) for turning on the switching device, and the gate-off voltage VGL may be a voltage (e.g., −5 V of FIG. 8) for turning off the switching device.”)
Chun teaches … to receive a mode selection signal of a first voltage level for selectively driving first and second light-emitting elements that emit light at different viewing angles of a pixel circuit from a timing controller and transmit the mode selection signal of the first voltage level, (Chun, [0067], “Accordingly, the second pixels PX2 in the privacy region PVR, or the second pixels PX2 located in the fourth and sixth rows R4 and R6 and the second through fifth columns may receive the data voltages DV corresponding to the black data, or the data voltages DV corresponding to the 0-gray level, and may be OFF (do not emit light) based on the data voltages DV corresponding to the 0-gray level. The first pixels PX1 in the privacy region PVR, or the first pixels PX1 located in the third and fifth rows R3 and R5 and the second through fifth columns may receive the data voltages DV corresponding to the input image data IDAT, and may be ON (may emit light) based on the data voltages DV corresponding to the input image data IDAT. Therefore, since only the first pixels PX1 having the first viewing angle, or the privacy pixels having the relatively narrow viewing angle emit light in the privacy region PVR, the privacy region PVR may display an image with the relatively narrow viewing angle, and the image displayed in the privacy region PVR may be viewed only by a user located in front of the display device 100.”)
wherein the different viewing angles of the pixel circuit include a first viewing angle and a second viewing angle different from the first viewing angle, (Chun, [0063], [0056], “The light emitting element EL1 of the first pixel PX1 may have the first viewing angle, and the light emitting element EL2 of the second pixel PX2 may have the second viewing angle greater than the first viewing angle. That is, the light emitting element EL1 of the first pixel PX1 may have a relatively narrow viewing angle, and the light emitting element EL2 of the second pixel PX2 may have a relatively wide viewing angle. In some embodiments, to have the relatively narrow viewing angle, the light emitting element EL1 of the first pixel PX1 may include, but is limited not to, a light emitting layer and a partition that prevents light emitted by the light emitting layer from spreading laterally.”)
wherein the mode selection signal includes a first mode selection signal for a first mode corresponding to the first viewing angle and a second mode selection signal for a second mode corresponding to the second viewing angle, and wherein the first mode selection signal is different from the second mode selection signal; and (Chun, [0062], “In the display device 100 according to embodiments, the panel driver 120 may receive the privacy region position information PVRPI indicating the position of the privacy region. In some embodiments, the privacy region may have a rectangular shape, and the privacy region position information PVRPI may include, but is not limited to, a start position indicating an upper-left coordinate of the privacy region and an end position indicating a lower-right coordinate of the privacy region. The panel driver 120 may set at least a partial region of the display panel 110 as the privacy region based on the privacy region position information PVRPI. Further, the panel driver 120 may set the remaining region of the display panel 110 excluding the privacy region as a public region.”)
… configured to convert the mode selection signal of the first voltage level into a converted mode selection signal of a second voltage level higher than the first voltage level and output the converted mode selection signal of the second voltage level to the pixel circuit, (Chun, [0068], “Further, the first pixels PX1 in the public region PBR may receive the data voltages DV corresponding to the black data, or the data voltages DV corresponding to the 0-gray level, and may be OFF (do not emit light) based on the data voltages DV corresponding to the 0-gray level. The second pixels PX2 in the public region PBR may receive the data voltages DV corresponding to the input image data IDAT, and may be ON (may emit light) based on the data voltages DV corresponding to the input image data IDAT. Therefore, since the second pixels PX2 having the second viewing angle, or the public pixels having the relatively wide viewing angle emit light in the public region PBR, the public region PBR may display an image with the relatively wide viewing angle.”)
Cho in view of Chun does not appear to provide specifics of the signals wherein the first mode selection signal and the second mode selection signal have different values except during a switching process between the first mode and the second mode while the first mode selection signal and the second mode selection signal have a same value.
Ji however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide controlling signal on opposite schedules with a same value between switching states. Ji therefore teaches wherein the first mode selection signal and the second mode selection signal have different values except during a switching process between the first mode and the second mode while the first mode selection signal and the second mode selection signal have a same value. (Ji, [0098-0100], [0098], “In some optional embodiments, referring to FIGS. 1, 4, 5, 12-14 and 16, FIG. 16 illustrates a drive time sequence diagram of a gate signal of the first control transistor and a gate signal of the second control transistor in FIG. 14. In one embodiment, in the first light-emitting mode A1, the first control transistor M1 may be in conduction, and the second control transistor M2 may be in cutoff; and in the second light-emitting mode A2, the first control transistor M1 may be in cutoff, and the second control transistor M2 may be in conduction.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide controlling signal on opposite schedules with a same value between switching states as taught in Ji as this was a known technique and would have been utilized for the art recognized purpose a free switching effect of a wide and narrow viewing angles of the light-emitting panel may be realized through a simple drive sequence. (Ji, [0100])
Consider Claim 2:
Cho in view of Chun in view of Ji discloses the level shifter of claim 1, wherein the second voltage level of the converted mode selection signal swings between a gate high voltage and a gate low voltage. (Cho, [0057], “Referring to FIG. 6, the level shifter LS may include a LVDS receiver LVDS Rx, a GD restorer, and a voltage shifting circuit. The LVDS receiver LVDS Rx may receive the logic timing information GD of the gate control signal in the LVDS interface form. The GD restorer may process the logic timing information GD of the gate control signal received in the LVDS interface form every 1 line quantity and may generate the gate control logic signal LGDC. The LVDS receiver LVDS Rx may be integrated into the GD restorer. In this case, a function of the LVDS receiver LVDS Rx may be performed by the GD restorer. As shown in FIG. 8, the voltage shifting circuit may boost a voltage swing width of the gate control logic signal LGDC, which swings between 0 V to 3.3 V, and may generate the gate control signal GDC that swings between a gate-on voltage VGH and a gate-off voltage VGL. The gate-on voltage VGH and the gate-off voltage VGL may be voltages required for an operation of a switching device included in pixels of the display panel. The gate-on voltage VGH may be a voltage (e.g., 25 V of FIG. 8) for turning on the switching device, and the gate-off voltage VGL may be a voltage (e.g., −5 V of FIG. 8) for turning off the switching device.”)
Consider Claim 3:
Cho in view of Chun in view of Ji discloses the level shifter of claim 2, wherein the second logic circuit receives the gate high voltage and the gate low voltage from a power supply. (Cho, [0057], [0043], “Referring to FIGS. 1 to 4, the level shifter LS may be connected to a source integrated circuit (SIC) using various interface methods. When the level shifter LS communicates with the source integrated circuit SIC using a low voltage differential signaling (LVDS) interface method, a subject that generates a gate control logic signal LGDC from the logic timing information GD of the gate control signal may be the level shifter LS. In this case, the source integrated circuit SIC may separate the gate driving bit information from the intra-interface signal IIFS, and may convert the logic timing information GD of the separated gate control signal into the LVDS interface form and may transmit the LVDS interface form to the level shifter LS. When the level shifter LS communicates with the source integrated circuit SIC using a simple interface method, the source integrated circuit SIC may separate the gate driving bit information from the intra-interface signal IIFS, and may generate the gate control logic signal LGDC from the logic timing information GD of the separated gate control signal and may then transmit the gate control logic signal LGDC to the level shifter LS. Differently from the LVDS interface method, the simple interface method may not require an additional processing procedure for transmission form.”)
Consider Claim 17:
Cho in view of Chun in view of Ji discloses the level shifter of claim 1, wherein the first mode selection signal and the second mode selection signal have the same value for a predetermined time interval between a rising time point of the first mode selection signal and a falling time point of the second mode selection signal. (Ji, [0098-0100], [0098], “In some optional embodiments, referring to FIGS. 1, 4, 5, 12-14 and 16, FIG. 16 illustrates a drive time sequence diagram of a gate signal of the first control transistor and a gate signal of the second control transistor in FIG. 14. In one embodiment, in the first light-emitting mode A1, the first control transistor M1 may be in conduction, and the second control transistor M2 may be in cutoff; and in the second light-emitting mode A2, the first control transistor M1 may be in cutoff, and the second control transistor M2 may be in conduction.”)
Claim Rejections - 35 USC § 103
Claim(s) 4, 9-12, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. U.S. Patent Application Publication No. 2021/0183319 A1 hereinafter Cho in view of Chun et al. U.S. Patent Application Publication No. 2025/0022420 A1 hereinafter Chun.
Consider Claim 4:
Cho discloses a display device comprising: (Cho, See Abstract.)
a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits each including first and second light-emitting elements that emit light at different viewing angles are disposed…; (Cho, [0034], “Referring to FIGS. 1 to 4, the display panel PNL may include a pixel array for embodying an image. A pixel array PARY may include data lines DL, gate lines GL, and pixels connected thereto DL and GL.”)
a data driver configured to supply a data voltage of pixel data to the data lines; (Cho, [0041], “Referring to FIGS. 1 to 4, the source driver may receive the intra-interface signal IIFS from the timing controller TCON. The source driver may generate data driving signal based on the source driving bit information included in the intra-interface signal IIFS and may supply the data driving signal to the data lines DL. The source driver may include a plurality of source integrated circuits SICs installed on a conductive film.”)
a level shifter configured to output a gate timing control signal and …, (Cho, [0043], “Referring to FIGS. 1 to 4, the level shifter LS may be connected to a source integrated circuit (SIC) using various interface methods. When the level shifter LS communicates with the source integrated circuit SIC using a low voltage differential signaling (LVDS) interface method, a subject that generates a gate control logic signal LGDC from the logic timing information GD of the gate control signal may be the level shifter LS. In this case, the source integrated circuit SIC may separate the gate driving bit information from the intra-interface signal IIFS, and may convert the logic timing information GD of the separated gate control signal into the LVDS interface form and may transmit the LVDS interface form to the level shifter LS. When the level shifter LS communicates with the source integrated circuit SIC using a simple interface method, the source integrated circuit SIC may separate the gate driving bit information from the intra-interface signal IIFS, and may generate the gate control logic signal LGDC from the logic timing information GD of the separated gate control signal and may then transmit the gate control logic signal LGDC to the level shifter LS. Differently from the LVDS interface method, the simple interface method may not require an additional processing procedure for transmission form.”)
a gate driver configured to generate a gate signal based on the gate timing control signal and supply the gate signal to the gate lines; (Cho, [0004], “A display device includes a panel driver for driving a display panel. The panel driver includes a source driver for driving data lines of the display panel, and a gate driver for driving gate lines of the display panel. The panel driver communicates with a timing controller and receives various pieces of information required for an operation. The source driver is connected to the timing controller through an intra-interface and receives information for driving a source from the timing controller. The gate driver receives information driving a gate from the timing controller through a separate gate transmission wiring separated from the intra-interface.”)
a timing controller configured to control the data driver, the level shifter and the gate driver, (Cho, [0038], “Referring to FIGS. 1 to 4, the timing controller TCON may be connected to the source driver through an intra-interface method. The intra-interface method may be an EPI interface method for simplifying a signal transmission path between the timing controller TCON and the source driver, but the present disclosure is not limited thereto. The timing controller TCON may generate an intra-interface signal IIFS to include both source driving bit information and gate driving bit information, thereby simplifying a signal transmission path between the timing controller TCON and the panel driver.”)
wherein the timing controller generates a mode selection signal of a first voltage level for selectively driving the first and second light-emitting elements of the pixel circuits and transmits the generated mode selection signal of the first voltage level to the level shifter, and (Cho, [0043], “Referring to FIGS. 1 to 4, the level shifter LS may be connected to a source integrated circuit (SIC) using various interface methods. When the level shifter LS communicates with the source integrated circuit SIC using a low voltage differential signaling (LVDS) interface method, a subject that generates a gate control logic signal LGDC from the logic timing information GD of the gate control signal may be the level shifter LS. In this case, the source integrated circuit SIC may separate the gate driving bit information from the intra-interface signal IIFS, and may convert the logic timing information GD of the separated gate control signal into the LVDS interface form and may transmit the LVDS interface form to the level shifter LS. When the level shifter LS communicates with the source integrated circuit SIC using a simple interface method, the source integrated circuit SIC may separate the gate driving bit information from the intra-interface signal IIFS, and may generate the gate control logic signal LGDC from the logic timing information GD of the separated gate control signal and may then transmit the gate control logic signal LGDC to the level shifter LS. Differently from the LVDS interface method, the simple interface method may not require an additional processing procedure for transmission form.”)
a first logic circuit configured to receive a mode selection signal of a first voltage level for selectively driving the first and second light-emitting elements of the pixel circuits from a timing controller and transmit the mode selection signal; and (Cho, [0057], “Referring to FIG. 6, the level shifter LS may include a LVDS receiver LVDS Rx, a GD restorer, and a voltage shifting circuit. The LVDS receiver LVDS Rx may receive the logic timing information GD of the gate control signal in the LVDS interface form. The GD restorer may process the logic timing information GD of the gate control signal received in the LVDS interface form every 1 line quantity and may generate the gate control logic signal LGDC. The LVDS receiver LVDS Rx may be integrated into the GD restorer. In this case, a function of the LVDS receiver LVDS Rx may be performed by the GD restorer. As shown in FIG. 8, the voltage shifting circuit may boost a voltage swing width of the gate control logic signal LGDC, which swings between 0 V to 3.3 V, and may generate the gate control signal GDC that swings between a gate-on voltage VGH and a gate-off voltage VGL. The gate-on voltage VGH and the gate-off voltage VGL may be voltages required for an operation of a switching device included in pixels of the display panel. The gate-on voltage VGH may be a voltage (e.g., 25 V of FIG. 8) for turning on the switching device, and the gate-off voltage VGL may be a voltage (e.g., −5 V of FIG. 8) for turning off the switching device.”)
a second logic circuit configured to convert the mode selection signal of the first voltage level into a converted mode selection signal of a second voltage level higher than the first voltage level and output the converted mode selection signal of the second voltage level to the pixel circuits. (Cho, [0057], “Referring to FIG. 6, the level shifter LS may include a LVDS receiver LVDS Rx, a GD restorer, and a voltage shifting circuit. The LVDS receiver LVDS Rx may receive the logic timing information GD of the gate control signal in the LVDS interface form. The GD restorer may process the logic timing information GD of the gate control signal received in the LVDS interface form every 1 line quantity and may generate the gate control logic signal LGDC. The LVDS receiver LVDS Rx may be integrated into the GD restorer. In this case, a function of the LVDS receiver LVDS Rx may be performed by the GD restorer. As shown in FIG. 8, the voltage shifting circuit may boost a voltage swing width of the gate control logic signal LGDC, which swings between 0 V to 3.3 V, and may generate the gate control signal GDC that swings between a gate-on voltage VGH and a gate-off voltage VGL. The gate-on voltage VGH and the gate-off voltage VGL may be voltages required for an operation of a switching device included in pixels of the display panel. The gate-on voltage VGH may be a voltage (e.g., 25 V of FIG. 8) for turning on the switching device, and the gate-off voltage VGL may be a voltage (e.g., −5 V of FIG. 8) for turning off the switching device.”)
Chun discloses a display device comprising: (Chun, See Abstract.)
a display panel in which a plurality of data lines, a plurality of gate lines intersecting the data lines, and a plurality of pixel circuits each including first and second light-emitting elements that emit light at different viewing angles are disposed, (Chun, [0045], “Referring to FIG. 1, a display device 100 according to embodiments may include a display panel 110 that includes first pixels PX1 and second pixels PX2, and a panel driver 120 (also referred to as a panel driver circuit) that drives a display panel 110. The panel driver 120 may include a data driver 130 (also referred to as a data driver circuit) that provides data voltages DV to the first and second pixels PX1 and PX2, and a controller 160 (also referred to as a controller circuit) that controls an operation of the display device 100. In some embodiments, the panel driver 120 may further include a scan driver 140 (also referred to as a scan driver circuit) that provides scan signals SS to the first and second pixels PX1 and PX2, and/or an emission driver 150 (also referred to as an emission driver circuit) that provides emission signals EM to the first and second pixels PX1 and PX2.”)
wherein the different viewing angles of the pixel circuits include a first viewing angle and a second viewing angle different from the first viewing angle; (Chun, [0063], [0056], “The light emitting element EL1 of the first pixel PX1 may have the first viewing angle, and the light emitting element EL2 of the second pixel PX2 may have the second viewing angle greater than the first viewing angle. That is, the light emitting element EL1 of the first pixel PX1 may have a relatively narrow viewing angle, and the light emitting element EL2 of the second pixel PX2 may have a relatively wide viewing angle. In some embodiments, to have the relatively narrow viewing angle, the light emitting element EL1 of the first pixel PX1 may include, but is limited not to, a light emitting layer and a partition that prevents light emitted by the light emitting layer from spreading laterally.”)
a data driver configured to supply a data voltage of pixel data to the data lines; (Chun, [0058], “The data driver 130 may generate the data voltages DV based on output image data ODAT and a data control signal DCTRL received from the controller 160, and may provide the data voltages DV to the first and second pixels PX1 and PX2. In some embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal and a load signal. Further, in some embodiments, the data driver 130 and the controller 160 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED). In some embodiments, the data driver 130 and the controller 160 may be implemented as separate integrated circuits.”)
[timing controller] configured to output a gate timing control signal and a mode selection signal, wherein the mode selection signal includes a first mode selection signal for a first mode corresponding to the first viewing angle and a second mode selection signal for a second mode corresponding to the second viewing angle, and wherein the first mode selection signal is different from the second mode selection signal; (Chun, [0061-0069], [0067], “Accordingly, the second pixels PX2 in the privacy region PVR, or the second pixels PX2 located in the fourth and sixth rows R4 and R6 and the second through fifth columns may receive the data voltages DV corresponding to the black data, or the data voltages DV corresponding to the 0-gray level, and may be OFF (do not emit light) based on the data voltages DV corresponding to the 0-gray level. The first pixels PX1 in the privacy region PVR, or the first pixels PX1 located in the third and fifth rows R3 and R5 and the second through fifth columns may receive the data voltages DV corresponding to the input image data IDAT, and may be ON (may emit light) based on the data voltages DV corresponding to the input image data IDAT. Therefore, since only the first pixels PX1 having the first viewing angle, or the privacy pixels having the relatively narrow viewing angle emit light in the privacy region PVR, the privacy region PVR may display an image with the relatively narrow viewing angle, and the image displayed in the privacy region PVR may be viewed only by a user located in front of the display device 100.”)
a gate driver configured to generate a gate signal based on the gate timing control signal and supply the gate signal to the gate lines; and a timing controller configured to control the data driver, the [timing controller] and the gate driver, wherein the timing controller generates a mode selection signal of a first voltage level for selectively driving the first and second light-emitting elements of the pixel circuits and transmits the generated mode selection signal. (Chun, [0068], “Further, the first pixels PX1 in the public region PBR may receive the data voltages DV corresponding to the black data, or the data voltages DV corresponding to the 0-gray level, and may be OFF (do not emit light) based on the data voltages DV corresponding to the 0-gray level. The second pixels PX2 in the public region PBR may receive the data voltages DV corresponding to the input image data IDAT, and may be ON (may emit light) based on the data voltages DV corresponding to the input image data IDAT. Therefore, since the second pixels PX2 having the second viewing angle, or the public pixels having the relatively wide viewing angle emit light in the public region PBR, the public region PBR may display an image with the relatively wide viewing angle.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide a viewing angle mode selection to selectively drive a series of first and second pixels to change a view mode as this was a known technique in view of Chun and would have been utilized for the purpose of a partial region of the display panel may be set as the privacy region PVR, the remaining region of the display panel may be set as the public region, an image may be displayed with a narrow viewing angle in the privacy region, and an image may be displayed with a wide viewing angle in the public region. Further, the position and the size of the privacy region may be readily controlled. (Chun, [0069])
Consider Claim 9:
Cho in view of Chun discloses the display device of claim 4, wherein the second voltage level of the converted mode selection signal swings between a gate high voltage and a gate low voltage. (Cho, [0057], “Referring to FIG. 6, the level shifter LS may include a LVDS receiver LVDS Rx, a GD restorer, and a voltage shifting circuit. The LVDS receiver LVDS Rx may receive the logic timing information GD of the gate control signal in the LVDS interface form. The GD restorer may process the logic timing information GD of the gate control signal received in the LVDS interface form every 1 line quantity and may generate the gate control logic signal LGDC. The LVDS receiver LVDS Rx may be integrated into the GD restorer. In this case, a function of the LVDS receiver LVDS Rx may be performed by the GD restorer. As shown in FIG. 8, the voltage shifting circuit may boost a voltage swing width of the gate control logic signal LGDC, which swings between 0 V to 3.3 V, and may generate the gate control signal GDC that swings between a gate-on voltage VGH and a gate-off voltage VGL. The gate-on voltage VGH and the gate-off voltage VGL may be voltages required for an operation of a switching device included in pixels of the display panel. The gate-on voltage VGH may be a voltage (e.g., 25 V of FIG. 8) for turning on the switching device, and the gate-off voltage VGL may be a voltage (e.g., −5 V of FIG. 8) for turning off the switching device.”)
Consider Claim 10:
Cho in view of Chun discloses the display device of claim 9, wherein the second logic circuit receives the gate high voltage and the gate low voltage from a power supply. (Cho, [0057], “Referring to FIG. 6, the level shifter LS may include a LVDS receiver LVDS Rx, a GD restorer, and a voltage shifting circuit. The LVDS receiver LVDS Rx may receive the logic timing information GD of the gate control signal in the LVDS interface form. The GD restorer may process the logic timing information GD of the gate control signal received in the LVDS interface form every 1 line quantity and may generate the gate control logic signal LGDC. The LVDS receiver LVDS Rx may be integrated into the GD restorer. In this case, a function of the LVDS receiver LVDS Rx may be performed by the GD restorer. As shown in FIG. 8, the voltage shifting circuit may boost a voltage swing width of the gate control logic signal LGDC, which swings between 0 V to 3.3 V, and may generate the gate control signal GDC that swings between a gate-on voltage VGH and a gate-off voltage VGL. The gate-on voltage VGH and the gate-off voltage VGL may be voltages required for an operation of a switching device included in pixels of the display panel. The gate-on voltage VGH may be a voltage (e.g., 25 V of FIG. 8) for turning on the switching device, and the gate-off voltage VGL may be a voltage (e.g., −5 V of FIG. 8) for turning off the switching device.”)
Consider Claim 11:
Cho in view of Chun discloses the display device of claim 4, wherein the level shifter is disposed in any one of a control printed circuit board (CPCB), a source printed circuit board (SPCB), and a driver integrated circuit (DIC). (Chun, [0045], Cho, [0041], “Referring to FIGS. 1 to 4, the source driver may receive the intra-interface signal IIFS from the timing controller TCON. The source driver may generate data driving signal based on the source driving bit information included in the intra-interface signal IIFS and may supply the data driving signal to the data lines DL. The source driver may include a plurality of source integrated circuits SICs installed on a conductive film. The conductive film may be a chip on film (COF), but the present disclosure is not limited thereto. The conductive film may be embodied as a tape carrier package (TCP) instead of a chip on film (COF). The source printed circuit board (SPCB) may be electrically connected to the display panel PNL through the conductive film COF and may also be electrically connected to the control board CBD through a cable CBL. The source printed circuit board (SPCB) may be configured in a singular or plural number. The cable CBL may be connected to the source printed circuit board (SPCB) and the control board CBD through a connector. The number of the cable CBL may be the same as the number of the source printed circuit boards (SPCBs), but the present disclosure is not limited thereto.”)
Consider Claim 12:
Cho in view of Chun discloses the display device of claim 4, wherein the second viewing angle is smaller than the first viewing angle. (Chun, [0063], [0056], “The light emitting element EL1 of the first pixel PX1 may have the first viewing angle, and the light emitting element EL2 of the second pixel PX2 may have the second viewing angle greater than the first viewing angle. That is, the light emitting element EL1 of the first pixel PX1 may have a relatively narrow viewing angle, and the light emitting element EL2 of the second pixel PX2 may have a relatively wide viewing angle. In some embodiments, to have the relatively narrow viewing angle, the light emitting element EL1 of the first pixel PX1 may include, but is limited not to, a light emitting layer and a partition that prevents light emitted by the light emitting layer from spreading laterally.”)
Consider Claim 15:
Cho in view of Chun discloses the level shifter of claim 1, wherein the second viewing angle is smaller than the first viewing angle. (Chun, [0063], [0056], “The light emitting element EL1 of the first pixel PX1 may have the first viewing angle, and the light emitting element EL2 of the second pixel PX2 may have the second viewing angle greater than the first viewing angle. That is, the light emitting element EL1 of the first pixel PX1 may have a relatively narrow viewing angle, and the light emitting element EL2 of the second pixel PX2 may have a relatively wide viewing angle. In some embodiments, to have the relatively narrow viewing angle, the light emitting element EL1 of the first pixel PX1 may include, but is limited not to, a light emitting layer and a partition that prevents light emitted by the light emitting layer from spreading laterally.”)
Claim Rejections - 35 USC § 103
Claim(s) 5-8 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. U.S. Patent Application Publication No. 2021/0183319 A1 hereinafter Cho in view of Chun et al. U.S. Patent Application Publication No. 2025/0022420 A1 hereinafter Chun in view of Ji et al. U.S. Patent Application Publication No. 2024/0178198 A1 hereinafter Ji.
Consider Claim 5:
Cho in view of Chun discloses the level shifter and the pixel circuits of the display device of claim 4, however does not specify that the pixel circuits are electrically connected through mode lines, and wherein the mode selection signal of the second voltage level outputted from the level shifter is applied to the pixel circuits through the mode lines.
Ji however teaches pixel circuits are electrically connected through mode lines, and wherein the mode selection signal of the second voltage level outputted from the level shifter is applied to the pixel circuits through the mode lines. (Ji, [0098-0100], [0098], “In some optional embodiments, referring to FIGS. 1, 4, 5, 12-14 and 16, FIG. 16 illustrates a drive time sequence diagram of a gate signal of the first control transistor and a gate signal of the second control transistor in FIG. 14. In one embodiment, in the first light-emitting mode A1, the first control transistor M1 may be in conduction, and the second control transistor M2 may be in cutoff; and in the second light-emitting mode A2, the first control transistor M1 may be in cutoff, and the second control transistor M2 may be in conduction.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide controlling signal on opposite schedules with a same value between switching states as taught in Ji as this was a known technique and would have been utilized for the art recognized purpose a free switching effect of a wide and narrow viewing angles of the light-emitting panel may be realized through a simple drive sequence. (Ji, [0100])
Consider Claim 6:
Cho in view of Chun in view of Ji discloses the display device of claim 5, wherein the level shifter is disposed in a control printed circuit board (CPCB), and the mode lines pass through a flexible printed circuit (FPC), a source printed circuit board (SPCB), and a chip on film (COF) and then are connected to the pixel circuits through a non-display area of the display panel. (Cho, [0041], “Referring to FIGS. 1 to 4, the source driver may receive the intra-interface signal IIFS from the timing controller TCON. The source driver may generate data driving signal based on the source driving bit information included in the intra-interface signal IIFS and may supply the data driving signal to the data lines DL. The source driver may include a plurality of source integrated circuits SICs installed on a conductive film. The conductive film may be a chip on film (COF), but the present disclosure is not limited thereto. The conductive film may be embodied as a tape carrier package (TCP) instead of a chip on film (COF). The source printed circuit board (SPCB) may be electrically connected to the display panel PNL through the conductive film COF and may also be electrically connected to the control board CBD through a cable CBL. The source printed circuit board (SPCB) may be configured in a singular or plural number. The cable CBL may be connected to the source printed circuit board (SPCB) and the control board CBD through a connector. The number of the cable CBL may be the same as the number of the source printed circuit boards (SPCBs), but the present disclosure is not limited thereto.”)
Consider Claim 7:
Cho in view of Chun in view of Ji discloses the display device of claim 6, wherein the mode lines are arranged side by side in the non-display area of the display panel and are arranged in parallel with the gate lines in a display area of the display panel. (Cho, [0046], “Referring to FIGS. 1 to 4, the GIP circuit GIP may be formed on a non-display region outside a pixel array on the display panel PNL. The GIP circuit GIP may be embodied using a single feeding method or a dual feeding method. In the single feeding method, the GIP circuit GIP may be formed only at one side of the display panel PNL. In contrast, in the dual feeding method, the GIP circuit GIP may be formed at opposite sides of the display panel PNL, and opposite gate stages connected to the same gate line may be simultaneously driven. In the dual feeding method, signal delay due to RC delay may be easily reduced compared with the single feeding method.”)
Consider Claim 8:
Cho in view of Chun in view of Ji discloses the display device of claim 6, wherein the mode lines are arranged side by side in the non-display area of the display panel and are arranged in parallel with the data lines in a display area of the display panel. (Cho, [0046], “Referring to FIGS. 1 to 4, the GIP circuit GIP may be formed on a non-display region outside a pixel array on the display panel PNL. The GIP circuit GIP may be embodied using a single feeding method or a dual feeding method. In the single feeding method, the GIP circuit GIP may be formed only at one side of the display panel PNL. In contrast, in the dual feeding method, the GIP circuit GIP may be formed at opposite sides of the display panel PNL, and opposite gate stages connected to the same gate line may be simultaneously driven. In the dual feeding method, signal delay due to RC delay may be easily reduced compared with the single feeding method.”)
Consider Claim 14:
Cho in view of Chun discloses display device of claim 4, however does not appear to specify wherein the first mode selection signal and the second mode selection signal have the same value for a predetermined time interval between a rising time point of the first mode selection signal and a falling time point of the second mode selection signal.
Ji however teaches that it was a known technique to those having ordinary skill in the art before the effective filing date of the invention to provide controlling signal on opposite schedules with a same value between switching states. Ji therefore teaches wherein the first mode selection signal and the second mode selection signal have the same value for a predetermined time interval between a rising time point of the first mode selection signal and a falling time point of the second mode selection signal.
(Ji, [0098-0100], [0098], “In some optional embodiments, referring to FIGS. 1, 4, 5, 12-14 and 16, FIG. 16 illustrates a drive time sequence diagram of a gate signal of the first control transistor and a gate signal of the second control transistor in FIG. 14. In one embodiment, in the first light-emitting mode A1, the first control transistor M1 may be in conduction, and the second control transistor M2 may be in cutoff; and in the second light-emitting mode A2, the first control transistor M1 may be in cutoff, and the second control transistor M2 may be in conduction.”)
It therefore would have been obvious to those having ordinary skill in the art before the effective filing date of the invention to provide controlling signal on opposite schedules with a same value between switching states as taught in Ji as this was a known technique and would have been utilized for the art recognized purpose a free switching effect of a wide and narrow viewing angles of the light-emitting panel may be realized through a simple drive sequence. (Ji, [0100])
Conclusion
Prior art made of record and not relied upon which is still considered pertinent to applicant's disclosure is cited in a current or previous PTO-892. The prior art cited in a current or previous PTO-892 reads upon the applicants claims in part, in whole and/or gives a general reference to the knowledge and skill of persons having ordinary skill in the art before the effective filing date of the invention. Applicant, when responding to this Office action, should consider not only the cited references applied in the rejection but also any additional references made of record.
In the response to this office action, the Examiner respectfully requests support be shown for any new or amended claims. More precisely, indicate support for any newly added language or amendments by specifying page, line numbers, and/or figure(s). This will assist The Office in compact prosecution of this application. The Office has cited particular columns, paragraphs, and/or line numbers in the applied rejection of the claims above for the convenience of the applicant. Citations are representative of the teachings in the art and are applied to the specific limitations within each claim, however other passages and figures may apply. Applicant, in preparing a response, should fully consider the cited reference(s) in its entirety and not only the cited portions as other sections of the reference may expand on the teachings of the cited portion(s).
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/Michael J Jansen II/ Primary Examiner, Art Unit 2626