DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statements filed on December 12, 2024 are considered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2016/0224272 A1) in view of Manning (US 8,971,124 B1).
Regarding claim 1, Kim discloses a device as shown in figure 8, comprising: a plurality of banks of memory cells (figure 8, 1880a-1880d and [0102], the memory cell array may include first to fourth bank arrays 1880a, 1880b, 1880c, and 1880d); and at least one compute component (figure 8, control logic 1810) coupled with the plurality of banks of memory cells, the at least one compute component configured to: retrieve, from a register of the device, instructions for one or more logical operations to be executed on a set of operands, the register comprising an instruction buffer for the instructions that are associated with an operating mode of the device, wherein the instructions are retrieved based at least in part on the operating mode ([0106]-[0108] and [0113], control logic 1810 may control operations of the memory device, and address buffer 1820 may provide the bank address BANK_ADDR to the bank control logic 1830, provide the row address ROW_ADDR to the row address multiplexer 1840, and provide the column address COL_ADDR to the column address latch). Kim differs from the claimed invention in not specifically teaching to manage execution of the instructions for the one or more logical operations on the set of operands in accordance with the operating mode and without enabling an input/output (I/O) line associated with a host. However, Manning teaches a sensing circuitry being used to perform logical operations using data stored in array as inputs and store the results of the logical operations back to the array without transferring via a sense line address access such that sensing circuitry is configured to perform logical operations on data stored in memory and store the result back to the memory without activating an I/O line coupled to the sensing circuitry, which can be formed on pitch with the memory cells of the array (col. 4 line 47 through col. 5 line 23), in order to conserve time and power in processing. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim to manage execution of the instructions for the one or more logical operations on the set of operands in accordance with the operating mode and without enabling an input/output (I/O) line associated with a host, as per teaching of Manning, in order to conserve time and power in processing.
Regarding claim 2, Kim discloses that the operating mode is based at least in part on a first value included in a mode register of the device, and wherein the operating mode comprises a mode in which performance of the one or more logical operations is enabled ([0108], a mode register 1813 may store an information selection signal and an information output signal for selecting at least one from among the mode register information, the refresh information, the operation state information and the temperature information of the memory device 1800 when the memory device 1800 is in the idle period).
Regarding claim 3, Kim discloses that the device exits the operating mode associated with the one or more logical operations based at least in part on a second value included in the mode register of the device ([0056], memory device 200 may set a mode register 210 by using the predetermined bit values provided via the address bus 120 in response to the MRS command).
Regarding claim 4, Kim discloses that the operating mode is from a plurality of selectable modes, the plurality of selectable modes including at least one mode in which performance of the one or more logical operations is disabled ([0057], mode register 210 may set a burst length, a read burst type, column address strobe (CAS) latency, a test mode, delay locked loop (DLL) reset, write recovery and read command-to-precharge command characteristics, DLL usage during precharge power-down, and DLL enable/disable of the memory device 200).
Regarding claims 5-6, Manning teaches that the at least one compute component is further configured to: retrieve, from the plurality of banks of memory cells, one or more operands associated with the one or more logical operations based at least in part on the instructions, wherein the at least one compute component is further configured to: retrieve, from an additional register of the device, one or more operands associated with the one or more logical operations based at least in part on the instructions (col. 4 line 67 through col. 5 line 7, data associated with an operand would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines, and data associated with an operand, for instance, would be read from memory via sensing circuitry and provided to external ALU circuitry via I/O lines) in order to conserve time and power in processing.
Regarding claim 7, Manning discloses that the one or more logical operations comprise a multiplication operation, an addition operation, or both (col. 1 lines 31-43, the functional unit circuitry (FUC) may be used to perform arithmetic operations such as addition, subtraction, multiplication, and/or division on operand).
Regarding claim 8, Kim discloses that the plurality of banks of memory cells comprise dynamic random access memory (DRAM) cells ([0047], the memory device 200 may include dynamic random access memory (DRAM) devices, synchronous DRAM (SDRAM) devices, double data rate (DDR) SDRAM devices, or other memory devices).
Regarding claim 9, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 10, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 11, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Regarding claim 12, the limitations of the claim are rejected as the same reasons as set forth in claim 4.
Regarding claims 13-14, the limitations of the claims are rejected as the same reasons as set forth in claims 5-6.
Regarding claim 15, Manning teaches storing a result of the one or more logical operations to one or more banks of memory cells without enabling the I/O line (col. 5 lines 8-12, sensing circuitry is configured to perform logical operations on data stored in memory and store the result back to the memory without activating (e.g., enabling) an I/O line coupled to the sensing circuitry) in order to conserve time and power in processing.
Regarding claim 16, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 17, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 18, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Regarding claim 19, the limitations of the claim are rejected as the same reasons as set forth in claim 4.
Regarding claim 20, the limitations of the claim are rejected as the same reasons as set forth in claims 5-6.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Terechko et al. (US 20110231688 A1) discloses a circuit arrangement and method of executing program code which utilize power control instructions capable of dynamically controlling power dissipation of multiple hardware resources during execution of a program by a processor having an enable logic is coupled to such a register file to selectively gate off or disable the clock, data and address input lines for any unused bank of registers in the register file (abstract and [0027]).
Loh et al. (US 2017/0221546A1) discloses a volatile memory device includes a refresh controller configured to control a hidden refresh operation performed on a first portion of memory cells while a valid operation is performed on a second portion of the memory cells (abstract and figure 2).
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/ZHUO H LI/Primary Examiner, Art Unit 2133