DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Priority
This Application claims priority to parent applications 17/017,286 and 18/081,474. However, as indicated below, the instant specification fails to provide adequate support for subject matter pertaining to “identify a first portion of a physical address corresponding to the logical address using the section of the L2P table”. Since this Application is continuation of said parent applications, the same instant specification is also found in said parent applications. As such, said parent applications also do not provide adequate written support to said subject matter. Therefore, said subject matter is not entitled to priority benefit of said parent applications.
Specification
The disclosure is objected to because of the following informalities. Appropriate correction is required.
¶[64] should be amended to “The LBAs 425 associated with page 420-c and page [[420-b]] 402-d may be an example of a second section”. This is a typo as page 420-b is already associated with first section (see ¶[64]).
Claim Objections
Claims 1 – 20 are objected to because of the following informalities. Appropriate correction is required.
Claim 1 should be amended to “identify a first portion of a physical address, corresponding , using [[using]] the section of the L2P table”. This is so that it is clear what (first portion or correspondence to logical address) uses L2P table section.
Claim 11 is the method claim corresponding to system claim 1, and is objected on the same grounds as claim 1.
Claim 20 is the non-transitory storage medium claim corresponding to system claim 1, and is objected on the same grounds as claim 1.
Claims, dependent upon above identified claims, are also objected on the same grounds as said above identified claims.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, “identify a first portion of a physical address corresponding to the logical address using the section of the L2P table” is not adequately disclosed in the instant specification. An original claim may lack written support when the claim defines the invention in a functional language specifying the desired result but the disclosure fails to sufficiently identify how the function is performed or the result is achieved (see MPEP 2163.03(V)). In this instance, the instant specification fails to disclose how said section is used to identify said first portion of said physical address. Rather, the instant specification discloses that it is LBA that is used to determine said first portion of said physical address, and that said section is itself said first portion of said physical address (see spec ¶[54-55]). There is no disclosure of how said section is used to identify said first portion of said physical address. Therefore, the limitation in question lacks written support.
Claim 11 is the method claim corresponding to system claim 1, and is rejected on the same grounds as claim 1.
Claim 20 is the non-transitory storage medium claim corresponding to system claim 1, and is rejected on the same grounds as claim 1.
Claims, dependent upon independent claims 1 or 11, are also rejected on the same grounds as said independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mohan (US 20170147499) in view of Lee (US 20070204128).
Regarding claim 1, Mohan teaches
A memory system (memory system = Fig. 1 data storage system 100), comprising:
one or more memory devices (one or more memory devices = Fig. 1 one or more NVM devices 140); and
one or more controllers (one or more controllers = Fig. 1 storage device controller 128 + NVM module controller 130) coupled with the one or more memory devices and configured to cause the memory system to: (Mohan teaches storage device controller 128 coupled to NVM module 160 that includes one or more NVM devices 140 that are coupled to NVM module controller 130 (see Fig. 1, ¶[42]). Mohan also teaches said storage device controller 128 and/or NVM controller 130 performing disclosed method (see ¶[98]).)
perform a look-up procedure on a logical-to-physical (L2P) table (L2P table = Figs. 3A-3B table 312 + table 324 + table 338) associated with the memory system to identify a section of the L2P table associated with a logical address; (Mohan teaches table 312 (L2P table) is example of first address translation table 170 while tables 324 and 338 (L2P table) are examples of second address translation tables 190 (see ¶[87]) wherein said first and second address translation tables are part of (associated with) data storage system 100 (see Fig. 1).)
identify a first portion of a physical address corresponding to the logical address using the section of the L2P table; (Mohan teaches specified logical address (logical address) is converted to predefined portion of said specified logical address that is located in (look-up procedure) a respective row (section) of table 312 (L2P table) wherein said respective row (section) maps (using) said predefined portion of said specified logical address to (identify) partial physical address (first portion of a physical address) (see Fig. 3A, ¶[87]). In exemplary embodiment, said specified logical address (logical address) is 4182 which is converted to said predefined portion of 1045 which is located in (look-up procedure) said respective row (section) of 318 that maps (using) said predefined portion of 1045 to said partial physical address (first portion of a physical address) of channel 3, chip 0, die 2 that is also mapped to (corresponding to) said specified logical address of 4182 (see Fig. 3A).)
perform [a modulo] operation on the logical address;
identify a second portion of the physical address based at least in part on performing the [modulo] operation; and
access the physical address using the first portion of the physical address and the second portion of the physical address (Mohan teaches mapping/indexing (performing operation) said specified logical address (logical address) to (identify based at least in part on performing the operation) corresponding entry/physical address offset (second portion of the physical address), in table 324/338, that maps said specified logical address to (identify) physical address (physical address) (see ¶[91-93]) which is used to locate a page when performing read/write (access) operation (see ¶85]). In exemplary embodiment, said partial physical address (first portion of physical address) of channel 3, chip 0, die 2 corresponds to (using) table 324 where said specified logical address (logical address) of 4182 is used to map/index (perform operation) into said entry (second portion of the physical address) 332 that maps (using) said specified logical address of 4182 to (identify) said physical address (physical address) of PA k (see Fig. 3A-3B).)
Mohan teaches a base system that maps/indexes (performing operation) specified logical address (logical address) to (identify based at least in part on performing the operation) entry/physical address offset (second portion of the physical address) (see claim 1). The claimed invention improves upon said base system by mapping/indexing said specified logical address via modulo operation on said specified logical address.
This improvement to said base method is an application of known technique from Lee – performing modulo (perform a modulo operation) on LBA (logical address) to index into an entry/PBA (portion of the physical address) (see Lee Fig. 2, ¶[40]).
One of ordinary skill in the art would recognize that this known technique of using modulo of logical address to index into an entry can also be applied to index into said entry/physical address offset of Mohan, and the result would have been predictable. In this instance, indexing/mapping (performing operation) of said specified logical address (logical address) to (identify based on performing operation) said entry/physical offset is by performing a modulo operation (modulo operation) on said specified logical address. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Lee’s known technique would have yielded i) predictable result of indexing/mapping (performing operation) said specified logical address (logical address) to (identify based on performing operation) said entry/physical offset is by performing a modulo operation (modulo operation) on said specified logical address, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claim 11 is the method claim corresponding to system claim 1, and is rejected on the same grounds as claim 1.
Claim 20 is the non-transitory storage medium claim corresponding to system claim 1, and is rejected on the same grounds as claim 1. Mohan also teaches
A non-transitory storage medium storing code comprising instructions, which when executed by one or more processors of an electronic device, cause the electronic device to (Mohan teaches non-transitory computer readable storage medium (non-transitory storage medium) storing one or more programs (code) for execution by one or more processors (one or more processors) of a storage device (electronic device), the one or more programs including instructions (instructions) for performing disclosed methods (see ¶[33]).)
Regarding claim 2, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
receive a command to access the logical address, wherein performing the look-up procedure is based at least in part on receiving the command (Mohan teaches specified logical address (logical address) is converted to predefined portion of said specified logical address that is located in (look-up procedure) a respective row of table 312 where said respective row maps said predefined portion of said specified logical address to partial physical address (see Fig. 3A, ¶[87]), and wherein a host command, received (receive) from a command queue, specifies operation (read/write(access)) to be performed at said specified logical address (see ¶[99]). Mohan also teaches subsequent to (based at least in part on) receiving said host command, said respective row (in which said predefined portion of said specified logical address is located (look-up procedure)) is used to map said predefined portion of said specified logical address to said partial physical address (see Fig. 4A, ¶[99-100].)
Claim 12 is the method claim corresponding to system claim 2, and is rejected on the same grounds as claim 2.
Regarding claim 3, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
receive a write command to write data to the logical address, wherein performing the look-up procedure is based at least in part on receiving the write command (Mohan teaches specified logical address (logical address) is converted to predefined portion of said specified logical address that is located in (look-up procedure) a respective row (section) of table 312 (L2P table) where said respective row maps said predefined portion of said specified logical address to partial physical address (see Fig. 3A, ¶[87]), and wherein a host command (write command), received (receive) from a command queue, specifies operation (read/write(write)) to be performed at said specified logical address, and said host command is to also write data (data) to a block of memory (see ¶[99]). Mohan also teaches subsequent to (based at least in part on) receiving said host command (write command), said respective row (in which said predefined portion of said specified logical address is located (look-up procedure)) is used to map said predefined portion of said specified logical address to said partial physical address (see Fig. 4A, ¶[99-100]).)
Claim 13 is the method claim corresponding to system claim 3, and is rejected on the same grounds as claim 3.
Regarding claim 4, Mohan in view of Lee teach the memory system of claim 3 where Mohan also teaches
wherein accessing the physical address comprises writing the data to the physical address of the memory system (Mohan teaches host command specifying operation (read/write) to be performed at specified logical address where said host command is to also write data (data) to a block of memory of NVM device 140/142 (see Fig. 4A, ¶[99]) in data storage system (memory system) (see Fig. 1). Mohan teaches identifying physical address (physical address) (or fine memory portion) from specified logical address in table 324 (see Fig. 4B, ¶[104]) wherein said write operation is executed on said physical address (physical address) (or said fine memory portion) to write (writing) said write data (data) (see Fig, 4C, ¶[107]).)
Claim 14 is the method claim corresponding to system claim 4, and is rejected on the same grounds as claim 4.
Regarding claim 5, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
receive a read command to retrieve data to the logical address, wherein performing the look-up procedure is based at least in part on receiving the read command (Mohan teaches specified logical address (logical address) is converted to predefined portion of said specified logical address that is located in (look-up procedure) a respective row (section) of table 312 (L2P table) where said respective row maps said predefined portion of said specified logical address to partial physical address (see Fig. 3A, ¶[87]), and wherein a host command (read command), received (receive) from a command queue, specifies operation (read (read)/write) to be performed at said specified logical address, and said read operation retrieves (retrieve) data (data) from NVM module 140/142 (see ¶[111]). Mohan also teaches subsequent to (based at least in part on) receiving said host command (read command), said respective row (in which said predefined portion of said specified logical address is located (look-up procedure)) is used to map said predefined portion of said specified logical address to said partial physical address (see Fig. 4A, ¶[99-100]).)
Claim 15 is the method claim corresponding to system claim 5, and is rejected on the same grounds as claim 5.
Regarding claim 6, Mohan in view of Lee teach the memory system of claim 5 where Mohan also teaches
wherein accessing the physical address comprises reading the data from the physical address of the memory system (Mohan teaches table 324/338 mapping specified logical address to physical address (physical address) (see ¶[91-93]) which is used to locate a page when performing read operation (see ¶85]) that retrieves (reading) data (data) from NVM device 140/142 (see ¶[111]) in data storage system 100 (memory system) (see Fig. 1).)
Claim 16 is the method claim corresponding to system claim 6, and is rejected on the same grounds as claim 6.
Regarding claim 7, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
wherein the L2P table of the memory system stores a mapping between logical addresses and sections of the memory system (Mohan teaches table 312 (L2P table) mapping logical addresses (logical addresses) to portions of logical addresses to channels + chips + dies (sections) (see Fig. 3A, ¶[87]). Note that said channels + chips + dies are also partial physical addresses (see Fig. 3A) that corresponds to coarse memory portions of respective NVM module 160 (see ¶[31]) in data storage system 100 (memory system) (see Fig. 1).)
Claim 17 is the method claim corresponding to system claim 7, and is rejected on the same grounds as claim 7.
Regarding claim 8, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
identify, based at least in part on identifying the second portion of the physical address, a first page of the memory system for storing data (Mohan teaches mapping/indexing specified logical address to (identifying) corresponding entry/physical address offset (second portion of the physical address), in table 324/338, that (based at least in part) maps said specified logical address to physical address (physical address) (see ¶[91-93]) which is used to locate (identify) a page (first page) when performing write operation (see ¶85]) that writes (storing) data (data) (see ¶[107]).)
Claim 18 is the method claim corresponding to system claim 8, and is rejected on the same grounds as claim 8.
Regarding claim 9, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
wherein the second portion corresponds to a first page of the section within the L2P table (Mohan teaches mapping/indexing specified logical address to (identifying) corresponding entry/physical address offset (second portion of the physical address), in table 324/338, that (corresponds) maps said specified logical address to physical address (see ¶[91-93]) which is used to locate a page (first page) when performing read/write operation (see ¶85]) wherein said specified logical address is converted to predefined portion of said specified logical address that is located in a respective row (section) of table 312 (L2P table) (see Fig. 3A, ¶[87]). Note that said specified logical address is used to associate said page (first page) and (of) said respective row (section).)
Claim 19 is the method claim corresponding to system claim 9, and is rejected on the same grounds as claim 9.
Regarding claim 10, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
identify corrupt data[, unmapped data, garbage collection data, or a combination thereof] based at least in part on one or more bits included in the L2P table (Mohan teaches table 324 (L2P table) includes valid flag value (one or more bits) to indicate whether data stored at particular physical address is valid wherein said valid flag value is changed to invalid (see Fig. 3B, ¶[55]) indicating that said data is invalid (corrupt) (see ¶[49]).)
Additional Remarks
In order to address §112(a) written description, independent claims should be amended to recite identifying, using the logical address, a first portion of a physical address. While this amendment would address said §112(a) written description, further search and consideration is required.
In the event Applicant amends as noted supra for §112(a) written description, double patenting rejection would apply to parent applications 17/017,286 and 18/081,474. Applicant is advised to consider this when filing a response.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mohan (US 20160232088) teaches using entire logical address to map to i) first subset of PA (first portion of a physical address) and ii) second subset of PA (second portion of the physical address (see Mohan ‘088 Fig. 3 and corresponding paragraphs). This is relevant to claims 1, 11 and 20.
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139