DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action has been issued in response to amendments filed 05 May 2026.
Claims 1 – 20 are pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1 – 2, 7 – 12 and 17 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 2, 8 and 11 of U.S. Patent No. 12,169,458 in view of Lee (US 20070204128). The claims at issue are obvious over said US Patent in view of Lee as outlined below.
Instant Application
Patent 12,169,458
1. A memory system, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
perform a look-up procedure on a logical-to-physical (L2P) table associated with the memory system to identify a section of the L2P table associated with a logical address;
identify, using the logical address, a first
portion of a physical address;
perform [a modulo] operation on the logical address;
identify a second portion of the physical address based at least in part on performing the [modulo] operation; and
access the physical address using the first portion of the physical address and the second portion of the physical address.
1. A memory device, comprising:
one or more memory arrays; and
one or more controllers coupled with the one or more memory arrays and configured to cause the memory device to:
perform a first operation, based at least in part on receiving the command, on an entirety of the LBA included in the received command and on a logical-to-physical (L2P) table associated with the memory device;
identify a first portion of a location in the memory device associated with the LBA based at least in part on performing the first operation, wherein first portion corresponds to a section within the L2P table
perform a second operation, based at least in part on receiving the command, on the entirety of the LBA included in the received command and on the L2P table;
identify a second portion of the location in the memory device associated with the LBA based at least in part on performing the second operation, wherein the second portion corresponds to a first page of the section, within the L2P table, for storing data
write the data to the first page associated with a physical address of the memory device based on location in the L2P table indicated by the first portion and the second portion
2. The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to:
receive a command to access the logical address, wherein performing the look-up procedure is based at least in part on receiving the command
1. receive a command to access a logical block address (LBA) associated with the memory device
1. perform a first operation, based at least in part on receiving the command, on an entirety of the LBA included in the received command and on a logical-to-physical (L2P) table associated with the memory device
7. The memory system of claim 1, wherein the L2P table of the memory system stores a mapping between logical addresses and sections of the memory system.
2. The apparatus memory device of claim 1, wherein the L2P table of the memory device stores a mapping between logical block addresses and sections of the memory device.
8. The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to:
identify, based at least in part on identifying the second portion of the physical address, a first page of the memory system for storing data.
1. identify a second portion of the location in the memory device associated with the LBA based at least in part on performing the second operation, wherein the second portion corresponds to a first page of the section, within the L2P table, for storing data
9. The memory system of claim 1, wherein the second portion corresponds to a first page of the section within the L2P table.
1. identify a second portion of the location in the memory device associated with the LBA based at least in part on performing the second operation, wherein the second portion corresponds to a first page of the section, within the L2P table, for storing data
10. The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to:
identify corrupt data, unmapped data, garbage collection data, or a combination thereof based at least in part on one or more bits included in the L2P table.
8. The memory device of claim 1, wherein the one or more controllers are further configured to cause the memory device to:
identify corrupt data, unmapped data, garbage collection data, or a combination thereof based at least in part on one or more bits included in the L2P table.
20. A non-transitory storage medium storing code comprising instructions, which when executed by one or more processors of an electronic device, cause the electronic device to:
perform a look-up procedure on a logical-to-physical (L2P) table to identify a section of the L2P table associated with a logical address;
identify, using the logical address, a first portion of a physical address;
perform [a modulo] operation on the logical address;
identify a second portion of the physical address based at least in part on performing the [modulo] operation; and
access the physical address using the first portion of the physical address and the second portion of the physical address.
11. A non-transitory storage medium storing code comprising instructions, which when executed by one or more processors of an electronic device, cause the electronic device to:
perform a first operation, based at least in part on receiving the command, on an entirety of the LBA included in the received command and on a logical-to-physical (L2P) table associated with the memory device;
identify a first portion of a location in the memory device associated with the LBA based at least in part on performing the first operation, wherein first portion corresponds to a section within the L2P table
perform a second operation, based at least in part on receiving the command, on the entirety of the LBA included in the received command and on the L2P table;
identify a second portion of the location in the memory device associated with the LBA based at least in part on performing the second operation, wherein the second portion corresponds to a first page of the section, within the L2P table, for storing data
write the data to the first page associated with a physical address of the memory device based on location in the L2P table indicated by the first portion and the second portion
Regarding claim 1, Patent 12,169,458 teaches a base system that uses (performing operation) logical address to identify/indexes a second portion of a physical address (see claim 1). The claimed invention improves upon said base system by using modulo operation, on said logical address, to index said second portion of physical address.
This improvement to said base system is an application of known technique from Lee – performing modulo (perform a modulo operation) on LBA (logical address) to index into an entry/PBA (portion of the physical address) (see Lee Fig. 2, ¶[40]).
One of ordinary skill in the art would recognize that this known technique of using modulo of logical address to index into an entry/PBA can also be applied to index into said second portion of said physical address of Patent 12,169,458, and the result would have been predictable. In this instance, said second portion of said physical address is indexed/identified using modulo operation on said logical address. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Lee’s known technique would have yielded i) predictable result of said second portion of said physical address being indexed/identified using modulo operation on said logical address, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claim 11 is the method claim corresponding to system claim 1, and is rejected on the same grounds as claim 1.
Claim 12 is the method claim corresponding to system claim 2, and is rejected on the same grounds as claim 2.
Claim 17 is the method claim corresponding to system claim 7, and is rejected on the same grounds as claim 7.
Claim 18 is the method claim corresponding to system claim 8, and is rejected on the same grounds as claim 8.
Claim 19 is the method claim corresponding to system claim 9, and is rejected on the same grounds as claim 9.
Regarding claim 20, Patent 12,169,458 teaches a based non-transitory storage medium that uses (performing operation) logical address to identify/indexes a second portion of a physical address (see claim 1). The claimed invention improves upon said base non-transitory storage medium by using modulo operation, on said logical address, to index said second portion of physical address.
This improvement to said base non-transitory storage medium is an application of known technique from Lee – performing modulo (perform a modulo operation) on LBA (logical address) to index into an entry/PBA (portion of the physical address) (see Lee Fig. 2, ¶[40]).
One of ordinary skill in the art would recognize that this known technique of using modulo of logical address to index into an entry/PBA can also be applied to index into said second portion of said physical address of Patent 12,169,458, and the result would have been predictable. In this instance, said second portion of said physical address is indexed/identified using modulo operation on said logical address. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Lee’s known technique would have yielded i) predictable result of said second portion of said physical address being indexed/identified using modulo operation on said logical address, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claims 1 – 2, 7 – 12 and 17 – 20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 – 2, 9 and 11 of U.S. Patent No. 11,537,526 in view of Lee (US 20070204128). The claims at issue are obvious over said US Patent in view of Lee as outlined below.
Instant Application
Patent 11,537,526
1. A memory system, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
perform a look-up procedure on a logical-to-physical (L2P) table associated with the memory system to identify a section of the L2P table associated with a logical address;
identify, using the logical address, a first
portion of a physical address;
perform [a modulo] operation on the logical address;
identify a second portion of the physical address based at least in part on performing the [modulo] operation; and
access the physical address using the first portion of the physical address and the second portion of the physical address.
1. A memory device, comprising:
a memory array; and
a controller coupled with the memory array and configured to cause the apparatus to:
identify, based at least in part on the logical block address and a logical-to-physical table stored by the memory device, a first portion of a physical address of the memory device associated with the logical block address, wherein the first portion comprises a section of the memory device associated with the logical block address, the section comprising a plurality of pages that are each mapped to one of a plurality of physical addresses;
perform, based at least in part on receiving the command, an operation on an entirety of the logical block address included in the received command;
identify, based at least in part on i) performing the operation on the entirety of the logical block address and ii) a size of the section, a second portion of the physical address, wherein the second portion is a first page of the plurality of pages in the section; and
access the physical address of the memory device based at least in part on the first page.
2. The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to:
receive a command to access the logical address, wherein performing the look-up procedure is based at least in part on receiving the command
1. receive a command to access a logical block address associated with a memory device
1. identify, based at least in part on the logical block address and a logical-to-physical table stored by the memory device, a first portion of a physical address of the memory device associated with the logical block address, wherein the first portion comprises a section of the memory device associated with the logical block address, the section comprising a plurality of pages that are each mapped to one of a plurality of physical addresses
7. The memory system of claim 1, wherein the L2P table of the memory system stores a mapping between logical addresses and sections of the memory system.
2. The apparatus of claim 1, wherein the logical-to-physical table of the memory device stores a mapping between logical block addresses and sections of the memory device
8. The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to:
identify, based at least in part on identifying the second portion of the physical address, a first page of the memory system for storing data.
1. identify, based at least in part on i) performing the operation on the entirety of the logical block address and ii) a size of the section, a second portion of the physical address, wherein the second portion is a first page of the plurality of pages in the section
9. The memory system of claim 1, wherein the second portion corresponds to a first page of the section within the L2P table.
1. identify, based at least in part on the logical block address and a logical-to-physical table stored by the memory device, a first portion of a physical address of the memory device associated with the logical block address, wherein the first portion comprises a section of the memory device associated with the logical block address, the section comprising a plurality of pages that are each mapped to one of a plurality of physical addresses
1. identify, based at least in part on i) performing the operation on the entirety of the logical block address and ii) a size of the section, a second portion of the physical address, wherein the second portion is a first page of the plurality of pages in the section
10. The memory system of claim 1, wherein the one or more controllers are further configured to cause the memory system to:
identify corrupt data, unmapped data, garbage collection data, or a combination thereof based at least in part on one or more bits included in the L2P table.
9. The apparatus of claim 1, wherein the controller is further configured to cause the apparatus to:
identify corrupt data, unmapped data, garbage collection data, or a combination thereof based at least in part on one or more bits included in the logical-to-physical table.
20. A non-transitory storage medium storing code comprising instructions, which when executed by one or more processors of an electronic device, cause the electronic device to:
perform a look-up procedure on a logical-to-physical (L2P) table to identify a section of the L2P table associated with a logical address;
identify, using the logical address, a first portion of a physical address;
perform [a modulo] operation on the logical address;
identify a second portion of the physical address based at least in part on performing the [modulo] operation; and
access the physical address using the first portion of the physical address and the second portion of the physical address.
11. A non-transitory storage medium storing code comprising instructions, which when executed by one or more processors of an electronic device, cause the electronic device to:
identify, based at least in part on the logical block address and a logical-to-physical table stored by the memory device, a first portion of a physical address of the memory device associated with the logical block address, wherein the first portion comprises a section of the memory device associated with the logical block address, the section comprising a plurality of pages that are each mapped to one of a plurality of physical addresses;
perform, based at least in part on receiving the command, an operation on an entirety of the logical block address included in the received command;
identify, based at least in part on i) performing the operation on the entirety of the logical block address and ii) a size of the section, a second portion of the physical address, wherein the second portion is a first page of the plurality of pages in the section
access the physical address of the memory device based at least in part on the first page
Regarding claim 1, Patent 11,537,526 teaches a base system that uses (performing operation) logical address to identify/indexes a second portion of a physical address (see claim 1). The claimed invention improves upon said base system by using modulo operation, on said logical address, to index said second portion of physical address.
This improvement to said base system is an application of known technique from Lee – performing modulo (perform a modulo operation) on LBA (logical address) to index into an entry/PBA (portion of the physical address) (see Lee Fig. 2, ¶[40]).
One of ordinary skill in the art would recognize that this known technique of using modulo of logical address to index into an entry/PBA can also be applied to index into said second portion of said physical address of Patent 11,537,526, and the result would have been predictable. In this instance, said second portion of said physical address is indexed/identified using modulo operation on said logical address. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Lee’s known technique would have yielded i) predictable result of said second portion of said physical address being indexed/identified using modulo operation on said logical address, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claim 11 is the method claim corresponding to system claim 1, and is rejected on the same grounds as claim 1.
Claim 12 is the method claim corresponding to system claim 2, and is rejected on the same grounds as claim 2.
Claim 17 is the method claim corresponding to system claim 7, and is rejected on the same grounds as claim 7.
Claim 18 is the method claim corresponding to system claim 8, and is rejected on the same grounds as claim 8.
Claim 19 is the method claim corresponding to system claim 9, and is rejected on the same grounds as claim 9.
Regarding claim 20, Patent 11,537,526 teaches a based non-transitory storage medium that uses (performing operation) logical address to identify/indexes a second portion of a physical address (see claim 1). The claimed invention improves upon said base non-transitory storage medium by using modulo operation, on said logical address, to index said second portion of physical address.
This improvement to said base non-transitory storage medium is an application of known technique from Lee – performing modulo (perform a modulo operation) on LBA (logical address) to index into an entry/PBA (portion of the physical address) (see Lee Fig. 2, ¶[40]).
One of ordinary skill in the art would recognize that this known technique of using modulo of logical address to index into an entry/PBA can also be applied to index into said second portion of said physical address of Patent 11,537,526, and the result would have been predictable. In this instance, said second portion of said physical address is indexed/identified using modulo operation on said logical address. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Lee’s known technique would have yielded i) predictable result of said second portion of said physical address being indexed/identified using modulo operation on said logical address, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mohan (US 20170147499) in view of Lee (US 20070204128).
Regarding claim 1, Mohan teaches
A memory system (memory system = Fig. 1 data storage system 100), comprising:
one or more memory devices (one or more memory devices = Fig. 1 one or more NVM devices 140); and
one or more controllers (one or more controllers = Fig. 1 storage device controller 128 + NVM module controller 130) coupled with the one or more memory devices and configured to cause the memory system to: (Mohan teaches storage device controller 128 coupled to NVM module 160 that includes one or more NVM devices 140 that are coupled to NVM module controller 130 (see Fig. 1, ¶[42]). Mohan also teaches said storage device controller 128 and/or NVM controller 130 performing disclosed method (see ¶[98]).)
perform a look-up procedure on a logical-to-physical (L2P) table (L2P table = Figs. 3A-3B table 312 + table 324 + table 338) associated with the memory system to identify a section of the L2P table associated with a logical address; (Mohan teaches table 312 (L2P table) is example of first address translation table 170 while tables 324 and 338 (L2P table) are examples of second address translation tables 190 (see ¶[87]) wherein said first and second address translation tables are part of (associated with) data storage system 100 (see Fig. 1).)
identify, using the logical address, a first portion of a physical address; (Mohan teaches specified logical address (logical address) is converted to (using) predefined portion of said specified logical address that is located in (look-up procedure) a respective row (section) of table 312 (L2P table) wherein said respective row (section) maps said predefined portion of said specified logical address to (identify) partial physical address (first portion of a physical address) (see Fig. 3A, ¶[87]). In exemplary embodiment, said specified logical address (logical address) is 4182 which is converted to (using) said predefined portion of 1045 which is located in (look-up procedure) said respective row (section) of 318 that maps said predefined portion of 1045 to said partial physical address (first portion of a physical address) of channel 3, chip 0, die 2 that is also mapped to said specified logical address of 4182 (see Fig. 3A).)
perform [a modulo] operation on the logical address;
identify a second portion of the physical address based at least in part on performing the [modulo] operation; and
access the physical address using the first portion of the physical address and the second portion of the physical address (Mohan teaches mapping/indexing (performing operation) said specified logical address (logical address) to (identify based at least in part on performing the operation) corresponding entry/physical address offset (second portion of the physical address), in table 324/338, that maps said specified logical address to (identify) physical address (physical address) (see ¶[91-93]) which is used to locate a page when performing read/write (access) operation (see ¶85]). In exemplary embodiment, said partial physical address (first portion of physical address) of channel 3, chip 0, die 2 corresponds to (using) table 324 where said specified logical address (logical address) of 4182 is used to map/index (perform operation) into said entry (second portion of the physical address) 332 that maps (using) said specified logical address of 4182 to (identify) said physical address (physical address) of PA k (see Fig. 3A-3B).)
Mohan teaches a base system that maps/indexes (performing operation) specified logical address (logical address) to (identify based at least in part on performing the operation) entry/physical address offset (second portion of the physical address) (see claim 1). The claimed invention improves upon said base system by mapping/indexing said specified logical address via modulo operation on said specified logical address.
This improvement to said base method is an application of known technique from Lee – performing modulo (perform a modulo operation) on LBA (logical address) to index into an entry/PBA (portion of the physical address) (see Lee Fig. 2, ¶[40]).
One of ordinary skill in the art would recognize that this known technique of using modulo of logical address to index into an entry can also be applied to index into said entry/physical address offset of Mohan, and the result would have been predictable. In this instance, indexing/mapping (performing operation) of said specified logical address (logical address) to (identify based on performing operation) said entry/physical offset is by performing a modulo operation (modulo operation) on said specified logical address. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Lee’s known technique would have yielded i) predictable result of indexing/mapping (performing operation) said specified logical address (logical address) to (identify based on performing operation) said entry/physical offset is by performing a modulo operation (modulo operation) on said specified logical address, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Claim 11 is the method claim corresponding to system claim 1, and is rejected on the same grounds as claim 1.
Claim 20 is the non-transitory storage medium claim corresponding to system claim 1, and is rejected on the same grounds as claim 1. Mohan also teaches
A non-transitory storage medium storing code comprising instructions, which when executed by one or more processors of an electronic device, cause the electronic device to (Mohan teaches non-transitory computer readable storage medium (non-transitory storage medium) storing one or more programs (code) for execution by one or more processors (one or more processors) of a storage device (electronic device), the one or more programs including instructions (instructions) for performing disclosed methods (see ¶[33]).)
Regarding claim 2, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
receive a command to access the logical address, wherein performing the look-up procedure is based at least in part on receiving the command (Mohan teaches specified logical address (logical address) is converted to predefined portion of said specified logical address that is located in (look-up procedure) a respective row of table 312 where said respective row maps said predefined portion of said specified logical address to partial physical address (see Fig. 3A, ¶[87]), and wherein a host command, received (receive) from a command queue, specifies operation (read/write(access)) to be performed at said specified logical address (see ¶[99]). Mohan also teaches subsequent to (based at least in part on) receiving said host command, said respective row (in which said predefined portion of said specified logical address is located (look-up procedure)) is used to map said predefined portion of said specified logical address to said partial physical address (see Fig. 4A, ¶[99-100].)
Claim 12 is the method claim corresponding to system claim 2, and is rejected on the same grounds as claim 2.
Regarding claim 3, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
receive a write command to write data to the logical address, wherein performing the look-up procedure is based at least in part on receiving the write command (Mohan teaches specified logical address (logical address) is converted to predefined portion of said specified logical address that is located in (look-up procedure) a respective row (section) of table 312 (L2P table) where said respective row maps said predefined portion of said specified logical address to partial physical address (see Fig. 3A, ¶[87]), and wherein a host command (write command), received (receive) from a command queue, specifies operation (read/write(write)) to be performed at said specified logical address, and said host command is to also write data (data) to a block of memory (see ¶[99]). Mohan also teaches subsequent to (based at least in part on) receiving said host command (write command), said respective row (in which said predefined portion of said specified logical address is located (look-up procedure)) is used to map said predefined portion of said specified logical address to said partial physical address (see Fig. 4A, ¶[99-100]).)
Claim 13 is the method claim corresponding to system claim 3, and is rejected on the same grounds as claim 3.
Regarding claim 4, Mohan in view of Lee teach the memory system of claim 3 where Mohan also teaches
wherein accessing the physical address comprises writing the data to the physical address of the memory system (Mohan teaches host command specifying operation (read/write) to be performed at specified logical address where said host command is to also write data (data) to a block of memory of NVM device 140/142 (see Fig. 4A, ¶[99]) in data storage system (memory system) (see Fig. 1). Mohan teaches identifying physical address (physical address) (or fine memory portion) from specified logical address in table 324 (see Fig. 4B, ¶[104]) wherein said write operation is executed on said physical address (physical address) (or said fine memory portion) to write (writing) said write data (data) (see Fig, 4C, ¶[107]).)
Claim 14 is the method claim corresponding to system claim 4, and is rejected on the same grounds as claim 4.
Regarding claim 5, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
receive a read command to retrieve data to the logical address, wherein performing the look-up procedure is based at least in part on receiving the read command (Mohan teaches specified logical address (logical address) is converted to predefined portion of said specified logical address that is located in (look-up procedure) a respective row (section) of table 312 (L2P table) where said respective row maps said predefined portion of said specified logical address to partial physical address (see Fig. 3A, ¶[87]), and wherein a host command (read command), received (receive) from a command queue, specifies operation (read (read)/write) to be performed at said specified logical address, and said read operation retrieves (retrieve) data (data) from NVM module 140/142 (see ¶[111]). Mohan also teaches subsequent to (based at least in part on) receiving said host command (read command), said respective row (in which said predefined portion of said specified logical address is located (look-up procedure)) is used to map said predefined portion of said specified logical address to said partial physical address (see Fig. 4A, ¶[99-100]).)
Claim 15 is the method claim corresponding to system claim 5, and is rejected on the same grounds as claim 5.
Regarding claim 6, Mohan in view of Lee teach the memory system of claim 5 where Mohan also teaches
wherein accessing the physical address comprises reading the data from the physical address of the memory system (Mohan teaches table 324/338 mapping specified logical address to physical address (physical address) (see ¶[91-93]) which is used to locate a page when performing read operation (see ¶85]) that retrieves (reading) data (data) from NVM device 140/142 (see ¶[111]) in data storage system 100 (memory system) (see Fig. 1).)
Claim 16 is the method claim corresponding to system claim 6, and is rejected on the same grounds as claim 6.
Regarding claim 7, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
wherein the L2P table of the memory system stores a mapping between logical addresses and sections of the memory system (Mohan teaches table 312 (L2P table) mapping logical addresses (logical addresses) to portions of logical addresses to channels + chips + dies (sections) (see Fig. 3A, ¶[87]). Note that said channels + chips + dies are also partial physical addresses (see Fig. 3A) that corresponds to coarse memory portions of respective NVM module 160 (see ¶[31]) in data storage system 100 (memory system) (see Fig. 1).)
Claim 17 is the method claim corresponding to system claim 7, and is rejected on the same grounds as claim 7.
Regarding claim 8, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
identify, based at least in part on identifying the second portion of the physical address, a first page of the memory system for storing data (Mohan teaches mapping/indexing specified logical address to (identifying) corresponding entry/physical address offset (second portion of the physical address), in table 324/338, that (based at least in part) maps said specified logical address to physical address (physical address) (see ¶[91-93]) which is used to locate (identify) a page (first page) when performing write operation (see ¶85]) that writes (storing) data (data) (see ¶[107]).)
Claim 18 is the method claim corresponding to system claim 8, and is rejected on the same grounds as claim 8.
Regarding claim 9, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
wherein the second portion corresponds to a first page of the section within the L2P table (Mohan teaches mapping/indexing specified logical address to (identifying) corresponding entry/physical address offset (second portion of the physical address), in table 324/338, that (corresponds) maps said specified logical address to physical address (see ¶[91-93]) which is used to locate a page (first page) when performing read/write operation (see ¶85]) wherein said specified logical address is converted to predefined portion of said specified logical address that is located in a respective row (section) of table 312 (L2P table) (see Fig. 3A, ¶[87]). Note that said specified logical address is used to associate said page (first page) and (of) said respective row (section).)
Claim 19 is the method claim corresponding to system claim 9, and is rejected on the same grounds as claim 9.
Regarding claim 10, Mohan in view of Lee teach the memory system of claim 1 where Mohan also teaches
identify corrupt data[, unmapped data, garbage collection data, or a combination thereof] based at least in part on one or more bits included in the L2P table (Mohan teaches table 324 (L2P table) includes valid flag value (one or more bits) to indicate whether data stored at particular physical address is valid wherein said valid flag value is changed to invalid (see Fig. 3B, ¶[55]) indicating that said data is invalid (corrupt) (see ¶[49]).)
Response to Remarks
Applicant’s amendments addressed claims/specification objections, and 112(a) written description rejections. Therefore, corresponding objections and 112(a) written description rejections are withdrawn.
Applicant’s remarks, with respect to prior art rejection, has been considered but are not persuasive. Applicant alleges that prior art fails to teach claim 1 by pointing to i) Lee failing to teach “identify, using the logical address, a first portion of a physical address”, and ii) Mohan for failing to teach “performing a modulo operation on the logical address” and “identify a second portion of the physical address based at least in part on performing the modulo operation”. Applicant's remarks appear to be attacking the references individually. However, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references (see In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986)). In this instance, the combination of Mohan and Lee is relied upon to teach these limitations (see rejection supra).
Applicant further alleges that combining Lee with Mohan would yield unpredictable results (and change operation of Mohan) because Mohon’s tree-based indexing would be replaced with second address translation table. Applicant’s remarks appear to be bodily incorporating Lee into Mohan by incorporating Lee’s second address translation table into Mohan’s tree-based indexing. The rejection is clear that Lee is relied upon to teach how to index into an entry in a translation table, and not replacement of Mohan’s tree with second translation table as alleged by Applicant. It is noted that the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art (see In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981)).
Applicant further alleges i) there is no motivation to combine because Lee solves a different problem than Mohan, and ii) there is no articulated reasoning for the combination of Mohan and Lee. It is noted that combination of Mohan and Lee is based on KSR Rationale D Applying a known technique to a known device (method, or product) ready for improvement to yield predictable results (see MPEP 2143(I)(D)). For rationale D, the following articulation is needed.
(1) a finding that the prior art contained a "base" device (method, or product) upon which the claimed invention can be seen as an "improvement;"
(2) a finding that the prior art contained a known technique that is applicable to the base device (method, or product);
(3) a finding that one of ordinary skill in the art would have recognized that applying the known technique would have yielded predictable results and resulted in an improved system; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
As noted supra, the rejection laid out articulation (1)-(4) as needed for rationale D. As such, the reasoning (and motivation) for combining Mohan and Lee has been properly articulated.
Claims, dependent upon independent claims 1 or 11, stand rejected as noted supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHIE YEW/ Primary Examiner, Art Unit 2139
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