DETAILED ACTION
This action is in response to communication filed on 11/26/2024.
Claims 1-17 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/25/2025, 8/11/2025, 10/25/2025, 2/28/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Computing System with Fusion Nodes and Orthogonally Connected Switching Nodes”.
Claim Objections
Claim 4 is objected to because of the following informalities: On line 3 of the claim, “…and at least of the plurality of switching nodes…” is missing a word and the intent appears to be “…and at least one of the plurality of switching nodes…”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2, 4, 6, 9, 11, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Doll et al. (US 2020/0214164) in view of Faw et al. (US 2017/0102510).
Regarding claim 1, Doll discloses a computing system, wherein the computing system comprises a plurality of fusion nodes and a plurality of switching nodes (Doll discloses a computing cabinet configured to accommodate multiple compute chassis (fusion nodes) and multiple switch chassis (switching nodes); [0027-0028] “compute cabinet 10 is specifically configured to accommodate at least one compute chassis 20, at least one switch chassis 30…four shelves are utilized. Further, this embodiment includes the ability to house two (2) compute chassis 20, two (2) switch chassis 30”);
the plurality of fusion nodes comprise a first fusion node that includes a plurality of computing chips (Doll discloses that each compute chassis (first fusion node) houses multiple compute blades, each containing processors that function as computing chips; [0029] “each compute cabinet 10 supports sixty-four (64) compute blades 22 that are serviced from the front of rack 10 without requiring a lift”) and;
a first switching node in the plurality of switching nodes is coupled to the first fusion node through a connector, and the first switching node is configured to implement communication connection between the first fusion node and another fusion node in the plurality of fusion nodes (Doll discloses that switch chassis (first switching node) are couple orthogonally and directly to the compute chassis (first fusion node) via rear connectors, enabling communication between multiple compute chassis though the switch blades; [0026] “Compute cabinet architecture also allows for vertical compute blades to be installed from the front, and connected orthogonally to horizontal switch blades to be installed from the rear” and [0030] “the switch blades 32 are orthogonally oriented to the compute blades 32 and plug in directly” and [0032] “For this design, each cabinet represents a local group in the Dragonfly topology. These groups consist of 512 nodes with 32 switches”).
However, the prior art does not explicitly disclose at least one first switching chip, and the at least one first switching chip is configured to implement communication connection between the plurality of computing chips.
Faw in the fields of the same endeavor provides techniques and configurations for a rack assembly. In particular, Faw teaches the following:
at least one first switching chip, and the at least one first switching chip is configured to implement communication connection between the plurality of computing chips (Faw discloses a rack tray/sled (fusion node) that includes multiple compute nodes (computing chips) together with a networking element containing a switch chip that manages communicative connections between those compute nodes within the same tray; [0024] “The compute nodes 110 included in the sled 142 in the tray 102 may be communicatively connected with one or more other components of the rack assembly 100… The communications between the compute nodes 110 included in the sled 142 on the tray 102 and other components… may be managed by one or more networking elements 112 disposed in the tray 102” [0025] “The networking element 112 may include a switch 122 (e.g., a switch chip) and a control unit 126 (e.g., CPU control module) configured to manage communicative connections provided by the switch 122”. This places the first switching chip inside the fusion node (tray/sled) to handle local communication between its computing chips)
Therefore, it would have been obvious to a person of ordinary skill in the art before the effectively filing date of the claimed invention to modify the compute chassis of Doll by incorporating a switch chip (as taught by Faw) inside the compute chassis/fusion node to handle intra-node communication between the compute blades/chips. One would have been motivated because both references are directed to scalable high performance computing rack systems that seek to reduce latency and improve bandwidth by co-locating compute and switching functions where appropriate (Doll [0025-0026] and Faw [0028]). Combining the orthogonal inter-node connector architecture of Doll with the integrated local switch chip of Faw would yield predictable results of high-density, lower latency communication within each fusion node while retaining the orthogonal coupling for inter-node traffic, thereby resolving known performance bottlenecks in large-scale computing clusters.
Regarding claim 2, Doll-Faw discloses the system according to claim 1, wherein a coupling manner between the first fusion node and the first switching node is orthogonal connection, and the connector comprises a backplane-free orthogonal connector or an optical blind-mate connector (Doll [0026] “compute cabinet 10 is optimized for density, power, cooling, scalability, and future upgradability. In this embodiment, compute cabinet 10 supports direct warm water liquid cooling and high voltage (400-480V) 3-phase AC power input. Compute cabinet architecture also allows for vertical compute blades to be installed from the front, and connected orthogonally to horizontal switch blades to be installed from the rear” and [0030] “In addition to the compute blades 22 discussed above, compute cabinet 10 supports up to sixty-four (64) switch blades 32 that are serviced from the rear of rack 12. This configuration may populate thirty-two (32) of these blades 32 for a single data plane, with expansion to 2 full data planes as an option. The switch blades 32 are orthogonally oriented to the compute blades 32 and plug in directly”).
Regarding claim 4, Doll-Faw discloses the system according to claim 1, wherein a network topology structure that comprises the plurality of computing chips, the at least one first switching chip, and the first switching node, is a network topology structure having no central switching node (Doll’s Dragonfly is a well-known networking topology structure that operates without any central switching node and instead, local groups (each cabinet) are interconnected directly via the switch blades in a hierarchical, all-to-all manner at the group level. The compute blades, switch ASICs, and switch chassis together form exactly the non-centralized topology; [0032] “each cabinet represents a local group in the Dragonfly topology. These groups consist of 512 nodes with 32 switches. A group size this large allows jobs of 512 or fewer nodes to have fully all-to-all connectivity”), and
at least of the plurality of switching nodes are configured to implement communication connection between the computing system and another computing system (Doll [0052] “Also situated on this side of switch blade 32 are a number of cable connectors 35. As will be appreciated, these cable connectors will provide appropriate networking connections and related communication capabilities. Also included are a number of global links 37 to provide a further expansion of the computing systems. It is anticipated that these global links 37 will provide connections to related cabinets, in those situations where multiple cabinets are utilized for the high performance computing system”).
Regarding claim 6, Doll-Faw discloses the system according to claim 1, wherein quantities of the plurality of fusion nodes and the plurality of switching nodes in the computing system are determined based on at least one of a bandwidth requirement of the computing chip, a quantity of ports and a switching capacity of the first switching chip, or a quantity of ports and a switching capacity of the first switching node (Doll [0030] “The switch blades 32 are orthogonally oriented to the compute blades 32 and plug in directly. The number of switch blades 32 varies to support the desired injection, intra-group, and global bandwidths”).
Regarding claim(s) 9, do(es) not teach or further define over the limitation in claim(s) 1 respectively. Therefore claim(s) 9 is/are rejected for the same rationale of rejection as set forth in claim(s) 1 respectively. Further, the additional limitations are rejected as follows:
generating, by a first computing chip of the first fusion node, a data packet, wherein a destination address of the data packet is an address of a second computing chip (Doll’s compute blades are processor that actively generate and transmit data packets containing destination addresses during normal operation of the high-performance computing cluster; [0037] “compute blade 22 contains drip-free fluid connectors 28 at the front for liquid cooling, along with L0 network connectors 26, power connectors 24, and HSS connector 29 at the rear. The blade structure includes a physical container or housing 21 which creates the EMI boundary” (the compute blades are the active processing elements that originate traffic, the L0 connectors are used to send the generated packets outward) and [0032] “each cabinet represents a local group in the Dragonfly topology. These groups consist of 512 nodes with 32 switches” (the 512 node are the compute blades that generate the inter-node packet carrying destination addresses)); and
forwarding, by the first fusion node, the data packet based on an address of a fusion node in which the second computing chip is located (Doll’s compute chasses (first fusion node) forwards packets it receives from its own compute blades to the destination compute chassis (another fusion node) by using the address of the destination group/node and routing through the switch chassis. The forwarding decision is made precisely based on the destination fusion-node address in the Dragonfly topology; [0032] “For this design, each cabinet represents a local group in the Dragonfly topology. These groups consist of 512 nodes with 32 switches” (forwarding between groups is performed by the compute chassis routing packets via the switch blades to the addressed destination group/fusion node) and [0026] “compute cabinet 10 supports direct warm water liquid cooling and high voltage (400-480V) 3-phase AC power input. Compute cabinet architecture also allows for vertical compute blades to be installed from the front, and connected orthogonally to horizontal switch blades to be installed from the rear” (the compute chassis (fusion node) performs the initial forwarding of the packet to the orthogonal switch blades for delivery to the destination fusion node)).
Regarding claim 15, Doll-Faw discloses the method according to claim 9, wherein quantities of the fusion nodes and the switching nodes in the computing system are determined based on a bandwidth requirement of the computing chip, a quantity of ports and a switching capacity of the first switching chip, and a quantity of ports and a switching capacity of the first switching node (Doll discloses determining qualities of compute nodes (fusion nodes) and switch blades/nodes based on bandwidth requirements of the computing elements (injection bandwidth) and the port/switching capacity of the switch blades (switching nodes). The design inherently accounts for ports counts and switching capacity in the blade configurations to achieve the target bandwidths; [0030] “The number of switch blades 32 varies to support the desired injection, intra-group, and global bandwidths” and [0032] “each cabinet represents a local group in the Dragonfly topology. These groups consist of 512 nodes with 32 switches”).
Regarding claim(s) 11 and 13, do(es) not teach or further define over the limitation in claim(s) 2 and 4 respectively. Therefore claim(s) 11 and 13 is/are rejected for the same rationale of rejection as set forth in claim(s) 2 and 4 respectively.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Doll et al. (US 2020/0214164) in view of Faw et al. (US 2017/0102510) in view of Dunham (US 2014/0098508).
Regarding claim 3, Doll-Faw discloses the system according to claim 1, wherein the connector comprises a high-speed connector, and the orthogonal connection between the first fusion node (Doll [0026] “Compute cabinet architecture also allows for vertical compute blades to be installed from the front, and connected orthogonally to horizontal switch blades to be installed from the rear”, [0030] “The switch blades 32 are orthogonally oriented to the compute blades 32 and plug in directly” and [0037] “HSS connector 29 at the rear” (high speed serial)).
However, the prior art does not explicitly disclose the first switching node is implemented by twisting the high-speed connector by 90 degrees.
Dunham in the field of the same endeavor discloses a direct-connect orthogonal electrical connection system with improved high frequency performance. In particular, Dunham teaches the following:
the first switching node is implemented by twisting the high-speed connector by 90 degrees (Dunham discloses high-speed orthogonal connection system in which the connector (or conductive elements with the high-speed connector assembly) is twisted at a 90 degree angle to implement the orthogonal interconnection between boards/nodes while maintaining signal integrity; [0089] “To form conductive elements that run continuously through the wafers and continue, with mating contact portions extending through conductive member 102 in the orientation illustrated, those conductive elements must be twisted at a 90.degree. angle. Such a twist allows the broad sides of the conductive elements within conductive member 102 to be perpendicular to the broad sides of the same conductive elements within the wafers of connector 100”)
Regarding claim(s) 12, do(es) not teach or further define over the limitation in claim(s) 3 respectively. Therefore claim(s) 12 is/are rejected for the same rationale of rejection as set forth in claim(s) 3 respectively.
Claims 5 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Doll et al. (US 2020/0214164) in view of Faw et al. (US 2017/0102510) in view of Johnsen et al. (US 2008/0315889).
Regarding claim 5, Doll-Faw discloses the system according to claim 1, wherein a network topology structure that comprises the plurality of computing chips, the at least one first switching chip, and the first switching node (Doll [0032] “each cabinet represents a local group in the Dragonfly topology. These groups consist of 512 nodes with 32 switches. A group size this large allows jobs of 512 or fewer nodes to have fully all-to-all connectivity”).
However, the prior art does not explicitly disclose the following:
is a network topology structure having a central switching node, and
communication connection between the computing system and another computing system is implemented through the central switching node.
Johnsen in the field of the same endeavor discloses a loopback connector for a system can include a connector arrangement connectable to connector of a system component and/or a cable. In particular, Johnsen teaches the following:
is a network topology structure having a central switching node (Johnsen [0110] “a single centralized switch with known topology that provides a 300:1 reduction in entities that need to be managed”)
communication connection between the computing system and another computing system is implemented through the central switching node (Johnsen [0110] “An example cable-based switch chassis can provide a very large switch having, for example, one or more of the following advantages, namely a 3456 ports non-blocking Clos (or Fat Tree) fabric, a 110 Terabit/sec bandwidth, major improvements in reliability, a 6:1 reduction in interconnect cables versus leaf and core switches, a new connector with superior mechanical design, major improvement in manageability, a single centralized switch with known topology that provides a 300:1 reduction in entities that need to be managed”).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was effectively field to modify the computing system of Doll by substituting its Dragonfly topology with the fat-free/Clos topology having a central switching node as taught by Johnsen. One would have been motivated because both references are directed to scalable high-performance computing cluster infrastructures that seek to provide full bisectional bandwidth, reduced cabling, and low-latency inter-node communication. The substitution yields predictable results of improved reliability and manageability in large-scale cluster.
Regarding claim(s) 14, do(es) not teach or further define over the limitation in claim(s) 5 respectively. Therefore claim(s) 14 is/are rejected for the same rationale of rejection as set forth in claim(s) 5 respectively.
Claims 7-8, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Doll et al. (US 2020/0214164) in view of Faw et al. (US 2017/0102510) in view of Heidelberger et al. (US 2020/0053002).
Regarding claim 7, Doll-Faw discloses the system according to claim 1, the first switching node comprises a plurality of second switching chips (Doll discloses the switch chassis contain plural switch blades 32, each a second switching chip; [0028] “this embodiment includes the ability to house two (2) compute chassis 20, two (2) switch chassis 30, one rectifier chassis 40 and two (2) chassis management modules 50, all supported by a single shelf”).
However, the prior art does not explicitly disclose the following:
wherein the at least one first switching chip comprises a first switching chip on a first switching plane and a first switching chip on a second switching plane,
the plurality of second switching chips comprise a second switching chip on the first switching plane and a second switching chip on the second switching plane, and
the first switching plane and the second switching plane bear different services.
Heidelberger in the field of the same endeavor discloses techniques for a switch-connected Dragonfly network system and method of operating. In particular, Heidelberger teaches the following:
wherein the at least one first switching chip comprises a first switching chip on a first switching plane and a first switching chip on a second switching plane (Heidelberger discloses switches within a group (first switching chip inside a fusion node/compute group) having multiple S ports that connect the switch to multiple parallel planes of columns switches. This places distinct first switching functionality on a first plane verse a second plane; [0026] “each switch 110 of a group may include multiple S ports for connections to multiple planes of column switches 150. For example, as shown in FIG. 1A, there is a single plane S=1 of column switches per column of switch groups (e.g., column switches 150A, . . . , 150D associated with column 111A). However, with multiple S ports, each switch can connect to multiple planes of single level crossbar column switches”),
the first switching node comprises a plurality of second switching chips (Doll discloses the switch chassis contain plural switch blades 32, each a second switching chip; [0028] “this embodiment includes the ability to house two (2) compute chassis 20, two (2) switch chassis 30, one rectifier chassis 40 and two (2) chassis management modules 50, all supported by a single shelf”),
the plurality of second switching chips comprise a second switching chip on the first switching plane and a second switching chip on the second switching plane (Heidelberger provides multiple parallel planes (S>1) of columns switches, each plane contains its own columns switches (directly mapping to second switching chips inside the switching node), so the plurality of second switching chips are distributed across a first plane and a second plane; [0028] “besides the column switches 150A-150D forming a single plane (S=1) of column switches associated with column 111A of row switch groups 105A-105D, in one embodiment, there are provided additional planes of column switches 155A, in parallel, resulting in S>1 planes of column switches for each group of row switches. As shown in FIG. 1B, the an arbitrary number of planes “s” of column switches are provided and labeled s=0, s=1, . . . s=S−1, where S is a total number of planes of column switches”), and
the first switching plane and the second switching plane bear different services (Heidelberger assigns distinct planes to different sockets or partitions within 2-way SMP nodes (e.g., socket 0 traffic on plane 0 vs. socket 1 traffic on plane 1/partition 2). These partitions logicially bear different services (different processing workloads or tenant traffic; [0090-0091] “if nodes 110 are 2-way SMPs and each socket has a port to a router, for scale, one can consider dual planes of networks where all the socket 0's of the SMPs are on network plane 0, e.g., a partition 0, and all the socket 1's of the SMP are on network plane 1, e.g., a partition 2”).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was effectively filed to modify the prior art by incorporating Heidelberger’s multi-plane (s>1) column-switch architecture with partition-based plane assignment. One would have been motivated to combine the prior art to allow the first and second switching chips to operate on separate plane that bear different services (or provide isolation), yielding predictable improvements in scalability and reliability without undue experimentation.
Regarding claim 8, Doll-Faw-Heidelberg discloses the system according to claim 7, wherein the first switching plane and the second switching plane are switching planes with network isolation; or the first switching plane and the second switching plane use different communication protocols (Heidelberger [0091] “dual planes of networks where all the socket 0's of the SMPs are on network plane 0, e.g., a partition 0, and all the socket 1's of the SMP are on network plane 1, e.g., a partition 2”).
Regarding claim(s) 16-17, do(es) not teach or further define over the limitation in claim(s) 7-8 respectively. Therefore claim(s) 16-17 is/are rejected for the same rationale of rejection as set forth in claim(s) 7-8 respectively.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Doll et al. (US 2020/0214164) in view of Faw et al. (US 2017/0102510) in view of Heidelberger et al. (US 2020/0053002) in view of Davis et al. (US 2013/0089104).
Regarding claim 10, Doll-Faw-Heidelberg discloses the method according to claim 9, wherein the forwarding, by the first fusion node, the data packet based on the address of the fusion node in which the second computing chip is located comprises:
sending, by the first switching node, the data packet to the second fusion node (Heidelberger [0045] “FIG. 5 shows a network switching configuration 500 including an order of LDSLDL hops where the network is configured to forward packets from a “source” node over an L link hop, a D link hop, an S link (2 hops) to switch 150, an L Link hop, a D link hop and over an L link hop to the destination (Dest) node. As shown in FIG. 5, column 111A functions as an intermediate column and not a final column”. The rationale to combine is similar to claim 7).
However, the prior art does not explicitly disclose the following:
when the second computing chip is a computing chip in the first fusion node, forwarding, by the first fusion node, the data packet to the destination address through the at least one first switching chip; and
when the second computing chip is a computing chip in a second fusion node, sending, by the first fusion node, the data packet to the first switching node in the plurality of switching nodes;
Davis in the fields of the same endeavor discloses techniques for support a routing using a tree-like or graph topology that supports multiple links per node, where each link is designated as an Up, Down, or Lateral link, or both, within the topology. In particular, Davis teaches the following:
when the second computing chip is a computing chip in the first fusion node, forwarding, by the first fusion node, the data packet to the destination address through the at least one first switching chip Davis discloses the Smooth-Stone nodes (first fusion node) contains both “computational processor”. When the destination ins inside the same node, the data packet is forwarded internally through that embedded/local switch; [0037] “Ovals 802a-n are Smooth-Stone nodes that comprise both computational processors as well as the embedded switch. The nodes have five XAUI links connected to the internal switch. The switching layers use all five XAUI links for switching”); and
when the second computing chip is a computing chip in a second fusion node, sending, by the first fusion node, the data packet to the first switching node in the plurality of switching nodes; and (Davis describes the first fusion node (Smooth-Stone) using its internal embedded switch to forward traffic out to the external aggregation router; [0031] “In a first rack 303a, the network aggregation system provides multiple high-speed 10 Gb paths, represented by thick lines, between one or more Smooth-Stone computing unit 306a-d, such as server computers, on shelves within a rack… An embedded switch 306a-d in the Smooth-Stone computing units can replace a top-of-rack switch, thus saving a dramatic amount of power and cost, while still providing a 10 Gb Ethernet port to the aggregation router 302”).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was effectively filed to combine the prior art with teachings of Davis. One would have been motivated to achieve scalable, high-bandwidth inter-node communication in large computing clusters by using Davis’s local embedded switch, thereby predictably resolving the performance bottlenecks of the prior art.
Conclusion
For the reason above, claims 1-17 have been rejected and remain pending.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIMMY H TRAN whose telephone number is (571)270-5638. The examiner can normally be reached Monday-Friday 9am-5pm PST.
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JIMMY H TRAN
Primary Examiner
Art Unit 2451
/JIMMY H TRAN/Primary Examiner, Art Unit 2451
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