DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, & 15 and determination of the slope of the gate voltage signal have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding claims 1, 8, & 15, in response to applicants arguments that Laulanet (US 2018/0241390 A1) does not explicitly disclose a substantially constant current that flows through the semiconductor switch, this is not persuasive. Laulanet discloses, in figure 1B & 2, that the output of the transistor, in the on state, maintains 80% to 100% output in voltage or current (Para [0016]). Accordingly, in the on state, the transistor causes a substantially constant current to flow (see also figure 1B depicting a substantially constant current flowing in the on state) while the gate voltage signal is applied to the transistor. Thus, a substantially constant current flows through the semiconductor switch while the gate voltage signal is applied to the semiconductor is switch is disclosed, as required by the invention as claimed.
Regarding claims 5 & 12, in response to applicants arguments that Frank et al. (US 10,469,057 B1), hereinafter Frank, does not explicitly disclose determining a slope for the gate voltage signal and controlling the gate driver based on the determined slope, this is not persuasive. Frank, discloses, in figure 4, that the correction factor unit 42 “determines the slope of V.sub.GE” (Frank, Col. 10, Line 5). The correction factor unit 42 then transmits a correction factor to the gate control unit 42 which then adjusts the gate control signals input to the gate driver transistors 44 & 45. The gate driver transistors 44/45 are controlled in an on/off state, respectively, to adjust the slope of the gate voltage signal supplied to the transistor 10 (Frank, Col. 10, Lines 5-28). Thus, determining a slope for the gate voltage signal and controlling the gate driver transistors based on the determined slope is disclosed, as required by the invention as claimed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 & 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Laulanet (US 2018/0241390 A1) in view of Frank et al. (US 10,469,057 B1), hereinafter Frank.
Regarding claim 1, Laulanet discloses, in figure 1A & 2, a solid-state circuit interrupt device, comprising:
a semiconductor switch operable to control current flow therethrough (transistor 204 is operable to control current flow therethrough);
a gate driver electrically coupled to the semiconductor switch and configured to apply a gate voltage signal to the semiconductor switch (Para [0022], “driver 202 coupled to the…transistor 204 to regulate slope of the transistor 204 based on output of the comparator 210 by increasing or decreasing voltage or current supplied to the transistor 204”); and
a microcontroller (comparator 210) electrically coupled to the gate driver and configured to control the gate driver (Para [0022], “driver 202 coupled to the comparator 210…to regulate the slope of the transistor 204 based on the output of the comparator 210”) by:
determining a slope for the gate voltage signal (Para [0022], “regulate the slope of the transistor 204…until the slope reaches the target slope”); and
controlling the gate driver to apply the gate voltage signal to the semiconductor switch based on the slope (Para [0022], “driver 202 coupled to the comparator 210 and the transistor 204 to regulate the slope of the transistor 204 based on output of the comparator 210 by increasing or decreasing voltage or current supplied to the transistor 204 at most once per pulse cycle until the slope reaches the target slope”);
wherein the gate voltage signal causes a substantially constant current to flow through the semiconductor switch while the gate voltage signal is applied to the semiconductor switch (driver 202 supplies a signal to the gate of transistor 204 which turns on the transistor 204 and allows a current to flow), but fails to explicitly disclose the comparator as a microcontroller and determining a slope for the gate voltage signal, wherein the slope is a linear slope.
However, Frank discloses, in figures 3 & 4, determining a slope for the gate voltage signal (Col. 10, Lines 5-10, “Once the correction factor unit 42 determines the slope of V.sub.GE, the correction factor unit 42 may determine a correction factor that is proportional to the input capacitance Ciss. The correction factor unit 42 may then transmit the correction factor to the gate control unit 41”), wherein the slope is a linear slope (linear slope VGE, see figure 3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the slope determination of Frank in the gate driver of Laulanet, to achieve the benefit of adjusting the slope as necessary for improving the timing and voltage response of the transistor and/or a load connected to the output of the transistor (Frank, Col. 7 & 8, Lines 56-67 & 1-5).
In combination, Laulanet and Frank do not explicitly disclose the microcontroller.
However, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a microcontroller as the comparator, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385). Further, Laulanet discloses that in other embodiments the comparator 210 may be implemented as a microcontroller to implement the capabilities of multi-step increases or decreases in the gate control signal (Laulanet, Para [0021]). Further still, Frank discloses the implementation of one or more microprocessors to implement the various aspects of the described techniques (Frank, Col. 13, Lines 49-58).
Regarding claim 2, Laulanet in view of Frank discloses the solid-state interrupt device of claim 1, and Laulanet continues to disclose, in figure 2 & 3, wherein the microcontroller is further configured to obtain one or more load control parameters and determine the slope for the gate voltage signal based on the one or more load control parameters (Para [0020], “comparator 210 coupled to the monitor module 206 to compare the voltage or the current across the transistor 204 with one or more reference currents or voltages”), the one or more load control parameters including: a constant load current, a load ON voltage, and a load ON time (Para [0021] & [0007], “the comparator 210 changes its output depending on whether the output of the monitor module 206 is greater or less than the reference voltage or current at a specific time provided by the clock 208”…further disclosure of load control parameters include ”Comparing the slope may also include simultaneously tracking a second circuit condition different from the slope using the comparator. The second circuit condition may be an under load, an open load, an over voltage load, an over current, and/or a short circuit”).
Regarding claim 3, Laulanet in view of Frank discloses the solid-state interrupt device of claim 2, and Laulanet continues to disclose, in figure 2 & 3, wherein the microcontroller obtains the one or more load control parameters by retrieving the parameters from a predefined source or by prompting a user to enter one or more of the parameters (Para [0021], “the comparator 210 changes its output depending on whether the output of the monitor module 206 is greater or less than the reference voltage or current at a specific time provided by the clock 208”).
Regarding claim 4, Laulanet in view of Frank discloses the solid-state interrupt device of claim 1, and Laulanet continues to disclose, in figure 2, wherein the microcontroller is configured to control the gate driver to apply the gate voltage signal to the semiconductor switch using a plurality of voltage steps (Para [0021], “comparator 210 may be relatively complex such as a microcontroller implementing an algorithm resulting in a multi-step increase or decrease in voltage or current”).
Regarding claim 5, Laulanet in view of Frank discloses the solid-state circuit interrupt device of claim 4, and Frank continues to disclose, in figure 3 & 4, wherein the gate driver comprises a plurality of transistors (transistors 44 and 45 of gate driver IC 40), at least two of the transistors configured to turn off and on in an alternating sequence to produce the plurality of voltage steps of the gate voltage signal (Col. 10, Lines 5-17, “Once the correction factor unit 42 determines the slope of V.sub.GE, the correction factor unit 42 may determine a correction factor that is proportional to the input capacitance Ciss. The correction factor unit 42 may then transmit the correction factor to the gate control unit 41 which is configured to use the correction factor to adjust the amplitudes of the preboost-on current and the turn-on current by adjusting the gate control signals output to the FETs 44 and 45. Similarly, the correction factor may also be used by the gate control unit 41 to adjust the amplitudes of the preboost-off current and the turn-off current. The gate control unit 41 may also, or in the alternative, adjust the pulse length of the preboost currents”…i.e., plurality of voltage steps to adjust the slope of the voltage gate signal V.sub.GE via the transistors 44, 45).
Regarding claim 6, Laulanet in view of Frank discloses the solid-state interrupt device of claim 4, and Frank continues to disclose, in figure 3, wherein each voltage step comprises a horizontal increment and a vertical increment (figure 3 discloses the gate voltage VGE with horizontal and vertical increments), the horizontal increment and the vertical increment defining the slope of the gate voltage signal (horizontal and vertical increments define the slope of the gate voltage signal VGE).
Regarding claim 8, Laulanet discloses, in figure 1A & 2, a method of controlling current flow in a solid-state circuit interrupt device, the method comprising:
providing a semiconductor switch in the solid-state circuit interrupt device (transistor 204), the semiconductor switch operable to control current flow therethrough (transistor 204 is operable to control current flow therethrough);
coupling a gate driver electrically to the semiconductor switch in the solid-state circuit interrupt device (driver 202 coupled to transistor 204), the gate driver configured to apply a gate voltage signal to the semiconductor switch (Para [0022], “driver 202 coupled to the…transistor 204 to regulate slope of the transistor 204 based on output of the comparator 210 by increasing or decreasing voltage or current supplied to the transistor 204”);
coupling a microcontroller electrically to the gate driver in the solid-state circuit interrupt device (comparator 210 coupled to driver 202), the microcontroller configured to control the gate driver (Para [0022], “driver 202 coupled to the comparator 210…to regulate the slope of the transistor 204 based on the output of the comparator 210”); and
configuring the microcontroller (210) to:
control the gate driver to apply the gate voltage signal to the semiconductor switch based on the slope (Para [0022], “driver 202 coupled to the comparator 210 and the transistor 204 to regulate the slope of the transistor 204 based on output of the comparator 210 by increasing or decreasing voltage or current supplied to the transistor 204 at most once per pulse cycle until the slope reaches the target slope”);
wherein the gate voltage signal causes a substantially constant current to flow through the semiconductor switch while the gate voltage signal is applied to the semiconductor switch (driver 202 supplies a signal to the gate of transistor 204 which turns on the transistor 204 and allows a current to flow), but does not explicitly disclose the comparator as a microcontroller and determining a slope for the gate voltage signal, wherein the slope is a linear slope.
However, Frank discloses, in figures 3 & 4, determining a slope for the gate voltage signal (Col. 10, Lines 5-10, “Once the correction factor unit 42 determines the slope of V.sub.GE, the correction factor unit 42 may determine a correction factor that is proportional to the input capacitance Ciss. The correction factor unit 42 may then transmit the correction factor to the gate control unit 41”), wherein the slope is a linear slope (linear slope VGE, see figure 3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the slope determination of Frank in the gate driver of Laulanet, to achieve the benefit of adjusting the slope as necessary for improving the timing and voltage response of the transistor and/or a load connected to the output of the transistor (Frank, Col. 7 & 8, Lines 56-67 & 1-5).
In combination, Laulanet and Frank do not explicitly disclose the microcontroller.
However, It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include a microcontroller as the comparator, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. (KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415‐421, 82 USPQ2d 1385). Further, Laulanet discloses that in other embodiments the comparator 210 may be implemented as a microcontroller to implement the capabilities of multi-step increases or decreases in the gate control signal (Laulanet, Para [0021]). Further still, Frank discloses the implementation of one or more microprocessors to implement the various aspects of the described techniques (Frank, Col. 13, Lines 49-58).
Regarding claim 9, Laulanet in view of Frank discloses the method of claim 8, and Frank continues to disclose, in figure 2 & 3, wherein the microcontroller is further configured to obtain one or more load control parameters and determine the slope for the gate voltage signal based on the one or more load control parameters (Para [0020], “comparator 210 coupled to the monitor module 206 to compare the voltage or the current across the transistor 204 with one or more reference currents or voltages”), the one or more load control parameters including: a constant load current, a load ON voltage, and a load ON time (Para [0021] & [0007], “the comparator 210 changes its output depending on whether the output of the monitor module 206 is greater or less than the reference voltage or current at a specific time provided by the clock 208”…further disclosure of load control parameters include ”Comparing the slope may also include simultaneously tracking a second circuit condition different from the slope using the comparator. The second circuit condition may be an under load, an open load, an over voltage load, an over current, and/or a short circuit”).
Regarding claim 10, Laulanet in view of Frank discloses the method of claim 9, and Laulanet continues to disclose, in figure 2 & 3, wherein the microcontroller obtains the one or more load control parameters by retrieving the parameters from a predefined source or by prompting a user to enter one or more of the parameters (Para [0021], “the comparator 210 changes its output depending on whether the output of the monitor module 206 is greater or less than the reference voltage or current at a specific time provided by the clock 208”).
Regarding claim 11, Laulanet in view of Frank discloses the method of claim 8, and Laulanet continues to disclose, in figure 2, wherein the microcontroller is configured to control the gate driver to apply the gate voltage signal to the semiconductor switch using a plurality of voltage steps (Para [0021], “comparator 210 may be relatively complex such as a microcontroller implementing an algorithm resulting in a multi-step increase or decrease in voltage or current”).
Regarding claim 12, Laulanet in view of Frank discloses the method of claim 11, and Frank continues to disclose, in figure 3 & 4, wherein the gate driver comprises a plurality of transistors (transistors 44 and 45 of gate driver IC 40), at least two of the transistors configured to turn off and on in an alternating sequence to produce the plurality of voltage steps of the gate voltage signal (Col. 10, Lines 5-17, “Once the correction factor unit 42 determines the slope of V.sub.GE, the correction factor unit 42 may determine a correction factor that is proportional to the input capacitance Ciss. The correction factor unit 42 may then transmit the correction factor to the gate control unit 41 which is configured to use the correction factor to adjust the amplitudes of the preboost-on current and the turn-on current by adjusting the gate control signals output to the FETs 44 and 45. Similarly, the correction factor may also be used by the gate control unit 41 to adjust the amplitudes of the preboost-off current and the turn-off current. The gate control unit 41 may also, or in the alternative, adjust the pulse length of the preboost currents”…i.e., plurality of voltage steps to adjust the slope of the voltage gate signal V.sub.GE via the transistors 44, 45).
Regarding claim 13, Laulanet in view of Frank discloses the method of claim 11, and Frank continues to disclose, in figure 3, wherein each voltage step comprises a horizontal increment and a vertical increment (figure 3 discloses the gate voltage VGE with horizontal and vertical increments), the horizontal increment and the vertical increment defining the slope of the gate voltage signal (horizontal and vertical increments define the slope of the gate voltage signal VGE).
Claim 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Narayanasamy (US 2024/0213975 A1) in view of Laulanet, and further in view of Frank.
Regarding claim 15, Narayanasamy discloses, in figure 19, a non-transitory computer-readable medium having computer-readable instructions stored thereon for controlling current flow in a solid-state circuit interrupt device (Para [0079] & [0083], “storage system 1930 can comprise any non-transitory computer readable storage media capable of storing software 1960 that is executable by processing circuitry 1920… software 1960 can, when loaded into processing circuitry 1920 and executed, transform processing circuitry 1920 overall from a general-purpose computing system into a special-purpose computing system customized to operate as described herein for a microcontroller unit 1900 configured to control a power switch”), but fails to explicitly disclose the computer-readable instructions, when executed by a controller in the solid-state circuit interrupt device, cause the controller to:
determine a slope for a gate voltage signal; and
control a gate driver of the solid-state circuit interrupt device to apply the gate voltage signal to a semiconductor switch of the solid-state circuit interrupt device based on the slope;
wherein the slope is a linear slope and the gate voltage signal causes a substantially constant current to flow through the semiconductor switch while the gate voltage signal is applied to the semiconductor switch.
However, Laulanet discloses, in figure 2, the computer-readable instructions, when executed by a controller in the solid-state circuit interrupt device (Para [0021], “the comparator 210 may be relatively complex such as a microcontroller implementing an algorithm resulting in a multi-step increase or decrease in voltage or current”), cause the controller (210) to:
control a gate driver of the solid-state circuit interrupt device to apply the gate voltage signal to a semiconductor switch of the solid-state circuit interrupt device based on the slope (Para [0022], “driver 202 coupled to the comparator 210 and the transistor 204 to regulate the slope of the transistor 204 based on output of the comparator 210 by increasing or decreasing voltage or current supplied to the transistor 204 at most once per pulse cycle until the slope reaches the target slope”);
wherein the gate voltage signal causes a substantially constant current to flow through the semiconductor switch while the gate voltage signal is applied to the semiconductor switch (driver 202 supplies a signal to the gate of transistor 204 which turns on the transistor 204 and allows a current to flow).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the microcontroller of Laulanet in the system of Narayanasamy, to achieve the benefit of implementing the capabilities of multi-step increases or decreases in the gate control signal for more precise control over the slope of the gate control signal (Laulanet, Para [0021]).
In combination, Narayanasamy and Laulanet do not explicitly disclose determining a slope for the gate voltage signal, wherein the slope is a linear slope.
However, Frank discloses, in figures 3 & 4, determining a slope for the gate voltage signal (Col. 10, Lines 5-10, “Once the correction factor unit 42 determines the slope of V.sub.GE, the correction factor unit 42 may determine a correction factor that is proportional to the input capacitance Ciss. The correction factor unit 42 may then transmit the correction factor to the gate control unit 41”), wherein the slope is a linear slope (linear slope VGE, see figure 3).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to include the slope determination of Frank in the gate driver of Narayanasamy and Laulanet, to achieve the benefit of adjusting the slope as necessary for improving the timing and voltage response of the transistor and/or a load connected to the output of the transistor (Frank, Col. 7 & 8, Lines 56-67 & 1-5).
Regarding claim 16, the combination of Narayanasamy, Laulanet, and Frank discloses the non-transitory computer-readable medium of claim 15, and Laulanet continues to disclose, in figure 2 & 3, wherein the controller is further configured to obtain one or more load control parameters and determine the slope for the gate voltage signal based on the one or more load control parameters (Para [0020], “comparator 210 coupled to the monitor module 206 to compare the voltage or the current across the transistor 204 with one or more reference currents or voltages”), the one or more load control parameters including: a constant load current, a load ON voltage, and a load ON time (Para [0021] & [0007], “the comparator 210 changes its output depending on whether the output of the monitor module 206 is greater or less than the reference voltage or current at a specific time provided by the clock 208”…further disclosure of load control parameters include ”Comparing the slope may also include simultaneously tracking a second circuit condition different from the slope using the comparator. The second circuit condition may be an under load, an open load, an over voltage load, an over current, and/or a short circuit”).
Regarding claim 17, the combination of Narayanasamy, Laulanet, and Frank discloses the non-transitory computer-readable medium of claim 16, and continues to disclose, in figure 2 & 3, wherein the controller obtains the one or more load control parameters by retrieving the parameters from a predefined source or by prompting a user to enter one or more of the parameters (Para [0021], “the comparator 210 changes its output depending on whether the output of the monitor module 206 is greater or less than the reference voltage or current at a specific time provided by the clock 208”).
Regarding claim 18, the combination of Narayanasamy, Laulanet, and Frank discloses the non-transitory computer-readable medium of claim 15, and continues to disclose, in figure 2, wherein the controller is configured to control the gate driver to apply the gate voltage signal to the semiconductor switch using a plurality of voltage steps (Para [0021], “comparator 210 may be relatively complex such as a microcontroller implementing an algorithm resulting in a multi-step increase or decrease in voltage or current”).
Regarding claim 19, the combination of Narayanasamy, Laulanet, and Frank disclose the non-transitory computer-readable medium of claim 18, and Frank continues to disclose, in figure 3 & 4, wherein the gate driver comprises a plurality of transistors (transistors 44 and 45 of gate driver IC 40), at least two of the transistors configured to turn off and on in an alternating sequence to produce the plurality of voltage steps of the gate voltage signal (Col. 10, Lines 5-17, “Once the correction factor unit 42 determines the slope of V.sub.GE, the correction factor unit 42 may determine a correction factor that is proportional to the input capacitance Ciss. The correction factor unit 42 may then transmit the correction factor to the gate control unit 41 which is configured to use the correction factor to adjust the amplitudes of the preboost-on current and the turn-on current by adjusting the gate control signals output to the FETs 44 and 45. Similarly, the correction factor may also be used by the gate control unit 41 to adjust the amplitudes of the preboost-off current and the turn-off current. The gate control unit 41 may also, or in the alternative, adjust the pulse length of the preboost currents”…i.e., plurality of voltage steps to adjust the slope of the voltage gate signal V.sub.GE via the transistors 44, 45).
Regarding claim 20, the combination of Narayanasamy, Laulanet, Frank discloses the non-transitory computer-readable medium of claim 18, and Frank continues to disclose, in figure 3, wherein each voltage step comprises a horizontal increment and a vertical increment (figure 3 discloses the gate voltage VGE with horizontal and vertical increments), the horizontal increment and the vertical increment defining the slope of the gate voltage signal (horizontal and vertical increments define the slope of the gate voltage signal VGE).
Allowable Subject Matter
Claims 7 & 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Joos (US 2020/0266737 A1) [Figure 1. Discloses a method for controlling a semiconductor bridge of an electrically operable motor, the semiconductor bridge being controlled depending on a pulse width modulation signal by a first controllable semiconductor switch and a separate second controllable semiconductor switch for supplying the electrically operable motor with electrical energy, a ramp signal with a predeterminable ramp slope for controlling one of the two controllable semiconductor switches being generated by a ramp generator].
Horsky (US 2018/0309439 A1) [Figure 2. Discloses a driver circuit generating a drive signal having a first and second voltage state for controlling a power transistor switch coupled to a power supply node. A control circuit operates to sense a supply voltage at the power supply node and compare the sensed supply voltage to one or more voltage thresholds. In response to the comparison, the control circuit adjusts a switching slope of the drive signal from the first voltage state to the second voltage state].
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/TYLER J PERENY/ Examiner, Art Unit 2836
