DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a1/a2) as being anticipated by Shih et al. (US 20210035537 A1, hereinafter “Shih”).
Regarding claim 7,
Shih teaches:
A display device comprising: at least one communication module; and a processing circuit (Shih: Claim 1, “A display device comprising: a first graphics input port to receive a first video signal; a second graphics input port to receive a second video signal; a processor to select extended display identification data (EDID) information associated with the display device, and change the EDID information of a full-screen resolution of the first and second video signals while a split screen output command is generated; and a video scaler to generate a split screen output with a full-screen display for both the first and second video signals based on the changed EDID information”; NOTE: The first and second graphics input ports are the communication modules for receiving video signals communicated between a first machine 85 and/or a second machine 90 as shown in Fig. 5.);
wherein the processing circuit connects with a first image source device through the at least one communication module (Shih: ¶33, “. . . the first graphics input port 15 is to receive the first video signal 20 from a first machine 85. . .”; NOTE: Also see Fig. 1 processor 35 linked to the communication modules input ports connected to first machine 85 which is the first image source device.),
transmits an original Extended Display Identification Data (EDID) to the first image source device, and receives first image data from the first image source device (Shih: ¶35, “FIG. 6A, with reference to FIGS. 1 through 5, is a block diagram illustrating a system 100 to split the screen output of the display device 10, according to an example. The example system 100 may include a memory 105 to store EDID information 40a, 40b associated with a display device 10. . . The EDID information 40a, 40b includes capabilities for the display device 10, which may be read by a graphics card, which is not shown, to display graphics 133a, 133b at a full-screen display resolution 110. . . the resolution of the display device 10 refers to the number of pixels in the width and height dimensions, which can be displayed on the display device 10. In a full-screen display resolution 110, a sufficient number of pixels are provided, which are capable of providing a display on the full screen; e.g., entire width and height of the display device 10”; ¶18, “. . . the display reloads the EDID information, which triggers the host device to read a corrected/different EDID resolution associated with a PiP/PbP. . . “; ¶21, “. . . display device 10 including a first graphics input port 15 to receive a first video signal 20, and a second graphics input port 25 to receive a second video signal 30. . .”
NOTE: Since the image source device (host device first machine 85) can read EDID information from the display device, then display device inherently transmits the original EDID information to the first machine 85. The display device transmits original EDID information to the first image device (host machine, first machine 85) when the first machine 85 reads the EDID information from the display device. The original EDID transmitted to the first image device is EDID 40a which contains the original full-screen resolution of the display device providing sufficient number of pixels for full screen display. Then first image data (video signal 20) is received from the first machine 85, which is the first image source device.
Display device 10 provides original EDID 40a with full screen resolution information >> first machine 85 reads the original EDID 40a transmitted and provided by the display device 10 >> first image data video signal 20 is sent by the first image source and received by the display device, also see Fig. 1);
the processing circuit further connects with a second image source device through the at least one communication module, and receives second image data from the second image source device (Shih: ¶33, “. . . the second graphics input port 25 is to receive the second video signal 30 from a second machine 90 that is different from the first machine 85. . .”),
wherein the first image data and the second image data are displayed on the display device simultaneously, and the first image data and the second image data are displayed on a first display area and a second display area of the display device, respectively (Shih: ¶29, “. . . a split screen output 55 displayed on the display device 10 of FIG. 1, according to an example. More particularly, FIG. 3 is a block diagram illustrating an example where the full-screen display 60 for both the first video signal 20 and second video signal 30. . .”,
NOTE: As shown in Fig. 3, first image data video signal 20, and second image data video signal 30 are displayed simultaneously in a split screen mode and have respective first and second display areas. Also see Fig. 9.);
and the processing circuit modifies the original EDID to generate a modified EDID according to a size/resolution of the first display area, and provides the modified EDID to the first image source device (Shih: ¶26, “. . . the display device 10 is shown having the first graphics input port 15 to receive the first video signal 20, and the second graphics port 25 to receive the second video signal 30. The processor 35 is provided to change the EDID information 40a, 40b, and the video scaler 50 is provided to generate the split screen output 55 based on the changed EDID information 40aa, 40bb. . .”; ¶29, “. . . the changed EDID information 40aa, 40bb, as described above, changes the screen resolution associated with the graphics data 65a, 65b to allow for the full-screen display 60 for the graphics data 65a, 65b associated with the first video signal 20 and second video signal 30, respectively. . .”; ¶18, “. . . then the display reloads the EDID information, which triggers the host device to read a corrected/different EDID resolution associated with a PiP/PbP. . .”;
NOTE: The processing circuit changes the original EDID 40a to 40aa, the display then reloads the EDID information which is then transmitted to the host device(s) first/second machine so they can read the different EDID resolution. Because the first machine 85 reads the modified EDID 40aa from the display device, the modified EDID is therefore provided by the processing circuit of the display device (modifying original EDID 40a to modified EDID 40aa) to the first image source first machine 85.).
Regarding claim 8, depending on 7,
Shih teaches:
The display device of claim 7,
Shih further teaches:
wherein the processing circuit modifies a default resolution/optimal resolution in the original EDID to generate the modified EDID according to the size/resolution of the first display area (Shih: ¶54, “. . . the processor 35 utilizes up-conversion, down-conversion, upscaling, and downscaling techniques to change the resolution of the graphics 133a, 133b provided by the multiple host machines 135a, 135b, respectively. Accordingly, in one example, the graphics 133a, 133b provided by the host machines 135a, 135b, respectively may be set to full-screen display resolution 110, and by changing the EDID information 40aa, 40bb, the processor 35 is provided to change the resolution of the graphics 133a, 133b to be displayed on the display device 10 to a half-screen display resolution 140; i.e., for display on the multiple output displays 120a, 120b of the display device 10. . .”).
Regarding claim 9, depending on 8,
Shih teaches:
The display device of claim 8,
Shih further teaches:
wherein a default resolution/optimal resolution included in the modified EDID is smaller than the default resolution/optimal resolution included in the original EDID (Shih: Fig. 6, ¶54, “. . . the processor 35 is provided to change the resolution of the graphics 133a, 133b to be displayed on the display device 10 to a half-screen display resolution. . .”; NOTE: As discussed in the rejection of claim 7, the original EDID information contains the full-screen resolution of the display device; changing to half-screen display resolution constitutes in a smaller resolution than a full-screen resolution)
Regarding claim 10, depending on 7,
Shih teaches:
The display device of claim 7,
Shih further teaches:
wherein if the size of the first display area changes, the processing circuit modifies the modified EDID again according to the size/resolution of the first display area to generate another modified EDID; and the processing circuit provides the another modified EDID to the first image source device (Shih: ¶18, “. . . when a PiP/PbP mode is selected due to multiple image sources transmitting display data to a single display screen/monitor. In some examples, the display device adds an additional EDID information in erasable programmable read-only memory (EPROM) or flash memory, and then the display reloads the EDID information, which triggers the host device to read a corrected/different EDID resolution associated with a PiP/PbP feature enabled. . .”; ¶46, “. . . the output displays 120a-120b in FIG. 9 may be arranged as picture-in-picture or picture-by-picture formats, and may be uniformly sized or have different sizes; e.g., display 120a and 120b may be the same size or may be different sizes with respect to one another. . .”; Claim 14, “. . . wherein the computer-executable instructions, when executed, further cause the processor to process a split screen output command, wherein the split screen output command comprises any of a picture-in-picture output command and a picture-by-picture output command”; ¶53, “. . . the processor 35 may change the EDID information 40a, 40b into EDID information 40aa, 40bb. . .”
NOTE: Since the image source device (host device first machine 85) can read the modified EDID information with changes in association to a PiP selection from the display device, then the processing circuit of the display device 10 inherently transmits the another modified EDID information (associated with the PiP selection changes) to the first image source device first machine 85.
As discussed in the rejection of claim 7, the original EDID 40a/40b are modified to 40aa/40bb to support split screen mode. The split screen command comprises a PIP or picture-in-picture mode wherein if the user selects the PIP option, the display output is changed that have different sizes constituting to a first display area change because it transitions from a split-screen to PIP mode. The previously modified EDID (associated to half-screen resolution for split screen mode) is again modified to accommodate the PIP resolution and generates another modified EDID and is reloaded providing the another modified EDID to the host device triggering it to read the corrected/different EDID associated with the PIP mode.
Display device provides original EDID 40a (full screen resolution) >> modifies it to EDID 40aa according to half-screen resolution for split-screen mode >> when user selects PIP mode, the previously modified EDID 40aa is once again modified according to the resolution of the PIP mode >> triggers the host device to read the updated/modified EDID 40aa for PiP mode.)
Regarding claim 11, depending on 7,
Shih teaches:
The display device of claim 7,
wherein the modified EDID is a first modified EDID (Shih: ¶53, “. . . the processor 35 may change the EDID information 40a, 40b into EDID information 40aa, 40bb. . .”;
NOTE: The first modified EDID is EDID 40aa corresponding to the first image source.),
and the processing circuit further modifies the original EDID to generate a second modified EDID according to a size/resolution of the second display area, and provides the second modified EDID to the second image source device (Shih: ¶18, “. . . the display device adds an additional EDID information in erasable programmable read-only memory (EPROM) or flash memory, and then the display reloads the EDID information, which triggers the host device to read a corrected/different EDID resolution. . .”; ¶53, “. . . the processor 35 may change the EDID information 40a, 40b into EDID information 40aa, 40bb. . .”; ¶54, “. . . by changing the EDID information 40aa, 40bb, the processor 35 is provided to change the resolution of the graphics 133a, 133b to be displayed on the display device 10 to a half-screen display resolution. . .”; ¶31, “. . . the changed EDID information 40aa, 40bb includes half-screen resolution information . . “;
NOTE: The second modified EDID is EDID 40bb which is associated to the second machine 90. Since the second image source device (host device second machine 90) can read EDID information from the display device, then display device inherently transmits the second modified EDID 40bb information and is provided to the second machine 90. The second image source is the second machine 90 as illustrated in Fig. 5. The processing circuit of the display device 10 modifies the original EDID 40b to generate a second modified EDID 40bb according to half-screen resolution of the second display area (the right half of the display screen area as illustrated in fig. 3). When the host device (second machine 90/first machine 85) reads the modified EDID generated by the processing circuit processor 35 from the display device, then the second modified EDID 40bb is provided to the second image source device (second machine 90). Also see Fig. 1, 5, 6A-6B).
Regarding claim 12, depending on 11,
Shih teaches:
The display device of claim 11,
Shih further teaches:
wherein the processing circuit modifies a default resolution/optimal resolution in the original EDID to generate the first modified EDID according to the size/resolution of the first display area, and modifies the default resolution/optimal resolution in the original EDID to generate the second modified EDID according to the size/resolution of the second display area (Shih: ¶31, “. . . the changed EDID information 40aa, 40bb includes half-screen resolution information . . “; ¶54, “. . . the processor 35 utilizes up-conversion, down-conversion, upscaling, and downscaling techniques to change the resolution of the graphics 133a, 133b provided by the multiple host machines 135a, 135b, respectively;
NOTE: As discussed in the rejection of claim 7, the original EDID 40a/40b are modified to 40aa/40bb to support split screen mode. The original EDIDs 40a/40b contains the default full screen resolution, and the first modified EDIDs is 40aa/40bb which has the modified EDID according to the size/resolution of the first/second display area, which is the first half/second half of the split screen display area. Also see paragraphs 18, and 29).
Regarding method claims 1-6, method claims 1-6 are drawn to the methods corresponding to the configuration of using same as claimed in the apparatus of claims 7-12 respectively. Therefore, method claims 1-6 correspond to the configuration in the apparatus of claims 7-12 respectively, and are rejected for the same reasons of anticipation as used above.
Conclusion
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/PATRICK P GALERA/Examiner, Art Unit 2617 /KING Y POON/Supervisory Patent Examiner, Art Unit 2617
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