DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner’s Note
Examiner notes that the deletion of “4” in claim 5, line 1 and claim 7, line 1 does not comply with 37 CFR 1.121(c)(2), which states "The text of any deleted matter must be shown by strike-through except that double brackets placed before and after the deleted characters may be used to show deletion of five or fewer consecutive characters. The text of any deleted subject matter must be shown by being placed within double brackets if strike-through cannot be easily perceived." Ensure that deletions comply with 37 CFR 1.121(c)(2) in the future.
Drawings
The lengthy set of drawings has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 19 is objected to because of the following informalities:
Claim 19, line 12: The “and” at the end of the line is not needed and should be deleted.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-7, 13-14, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Evers et al. (US 20190369999 A1, see IDS filed 12/18/2025) in view of Seznec et al. (“A case for (partially) tagged geometric history length branch prediction.”, see IDS filed 03/30/2026).
Ishii et al. (US 20210089472 A1) is cited as extrinsic evidence to explain how a global history register is updated. Carlson (US 20160139932 A1) is cited as extrinsic evidence to explain how global history works and how it’s updated.
Regarding claim 1, Evers teaches an apparatus (Fig. 2: Processor core 205) comprising:
branch prediction circuitry (Figs. 2 and 4: Branch prediction unit 215) configured to generate predictions in respect of a given block of one or more instructions (Fig. 4 and [0028]), the predictions comprising at least:
a main path prediction in respect of a given branch instruction ([0028]: Branch prediction unit 215 predicts the outcome of a first branch); and
at least one alternate path prediction in respect of an alternate path of program flow predicted to be followed if the main path prediction is incorrect ([0028]: Branch prediction unit 215 predicts the second branch and stores the prediction in the instance that the first branch prediction is incorrect. The second branch prediction as the alternate path prediction, which corresponds to an alternate path of program flow to be followed if the first branch predicted to be taken was incorrect),
wherein the branch prediction circuitry is configured to store the at least one alternate path prediction in an alternate prediction cache (Fig. 4 and [0028, 0036]: The second branch prediction is stored in an alternate prediction storage array 462 within branch prediction unit 215. The alternate prediction storage array as the alternate prediction cache); and
block skipping circuitry (Fig. 2 and 5: The method 500 may be implemented in some embodiment within processing system 200, which includes branch prediction unit 215) responsive to a flush signal indicative of the main path prediction being incorrect (Fig. 3 and 5, [0042-0044]: At step 525, in the instance that within the block of instructions that the prediction of one or more branch instructions were incorrect, regardless whether the method flows into step 540 or 545, the processing system 200 would rollback to the branch in which it mispredicted. The rollback as the flush signal) to control the branch prediction circuitry to begin generating predictions in respect of a subsequent block of instructions identified by a prediction resumption address (Fig. 3 and 5, [0029, 0042-0044]: At steps 540 or 545, the branch prediction unit 215 begins to generate target addresses indicated by the first branch instruction or second branch instruction to begin predicting. The target addresses as the prediction resumption address. Both target addresses would point to blocks of instructions, therefore whichever target address is used will be generating predictions in a subsequent block of instructions);
wherein the block skipping circuitry is configured to identify the prediction resumption address of the subsequent block of instructions based on the at least one alternate path prediction ([0042-0044]: The target address of the second branch instruction may be used to generate predictions if the prediction of the first branch instruction is to be taken is incorrect); and
the block skipping circuitry is configured to support an encoding of the at least one alternate path prediction that indicates that the alternate path of program flow includes at least one taken branch ([0036]: “The branch prediction information includes information that describes a branch (if any) in the remainder block, a predicted conditional outcome of the branch, the predicted target of the branch, and the location of the end of the remainder block, or a similar representation of the same information”; In other words, there exists some encoding within the alternate prediction storage array that indicates that whether the second branch prediction is predicted to be taken or not taken),
wherein the branch prediction circuitry comprises:
history tracking circuitry to maintain a program flow history(Fig. 4 and [0035]: Branch history information is provided to the conditional branch predictor storage 460 within branch predictor unit 215. Therefore there must be circuitry to store the branch history), and
at least one (Fig. 4: Conditional branch predictor storage 460 stores prediction data).
Evers does not teach that the history tracking circuitry is to maintain a program flow history based on predicted branch instructions satisfying a program flow history update condition and that the storage structure is a set-associative storage structure, in which the at least one set-associative storage structure comprises sets indexed by a portion of the program flow history that is independent of information relating to a most recently predicted branch instruction satisfying the program flow history update condition.
Seznec teaches to maintain a program flow history based on predicted branch instructions satisfying a program flow history update condition (Pages 5-6, Section 3.1 “Geometric history length prediction”, Figure 1: The TAGE predictor discussed uses a global branch history, which is based on predicted branch instructions satisfying a program flow history update condition (see Ishii. [0080])) and at least one set-associative storage structure configured to store prediction data (Page 6, Figure 1: TAGE predictor comprises a plurality of set-associative structures (T0-T4) to store prediction data), in which the at least one set-associative storage structure comprises sets indexed by a portion of the program flow history that is independent of information relating to a most recently predicted branch instruction satisfying the program flow history update condition (Pages 5-6, Section 3 “The TAGE conditional branch predictor”, Figure 1: Each set-associative structure is comprised of sets indexed based on different portions of a global history. Any given branch in the global history may be a most recently predicted branch. For example, T1 uses L(1)=2 (see section 3.1 “Geometric history length prediction”, paragraph 3), which means that the table doesn’t use a most recent branch prediction corresponding to bit 3 of the global history. Therefore, the instructions are indexed independent of a most recently predicted branch instruction).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Evers with the teachings of Seznec to have indicated that the branch history tracker is a global branch history and made the storage structure a set-associative storage structure indexed by a portion of the program flow history that is independent of information relating to a most recently predicted branch instruction. The global branch history indicates what branch directions were taken within a processor, which provides valuable information as it can be used with a branch predictor to help predict the next branch prediction as well as be used to index data. A set-associative storage structure provides better performance compared to other storage structures such as a direct-mapped storage structure as it provides multiple ways for a memory block, which reduces conflicts misses. Furthermore, TAGE predictors is a highly accurate predictor (Seznec, see Abstract and Figure 2), and therefore, one of ordinary skill may consider using over other known predictors.
Regarding claim 3, Evers, in view of Seznec, teaches the apparatus of claim 1, wherein the branch prediction circuitry is configured to generate the main path prediction and at least one alternate path prediction from a single lookup in prediction data (Evers, Fig. 4 and [0012, 0028]: Branch prediction unit concurrently predicts branch instructions within a prediction block (i.e., an instruction block). Therefore, the predictions are performed from a single lookup. The prediction block as the prediction data).
Regarding claim 5, Evers, in view of Seznec, teaches the apparatus of claim 4, wherein:
each set comprises two or more prediction entries each stored in association with a respective tag value to be compared with a tag (Evers, Fig. 4 [0035]; Pages 5-6, Section 3 “The TAGE conditional branch predictor”, Figure 1: In the current combination, the block address and branch history (e.g., global history) is to be used to store data into the set-associative predictor storage. The set-associative storage will contain two or more prediction entries due to the set-associative structure. The block address and branch history as the tag to be compared with tag values within the predictor storage), the tag being dependent on an indication of the given block and on a portion of the program flow history that is dependent on the information relating to the most recently predicted branch instruction satisfying the program flow history update condition (Evers, Fig. 4 [0035]; Pages 5-6, Section 3 “The TAGE conditional branch predictor”, Figure 1: In the current combination, the block address (recall that it indicates the given block) and branch history is used to index into the prediction storage (For example, see Carlson, Fig. 3 and [0060]). The global history would include the most recently predicted branch instruction when indexing into the set-associative storage); and
the branch prediction circuitry is configured to generate the predictions in respect of the given block in dependence on the two or more prediction entries (Evers, Fig. 4 [0035]; Pages 5-6, Section 3 “The TAGE conditional branch predictor”, Figure 1: In the current combination, the predictor storage of Evers will output data to conditional logic 465, which is used to generate branch predictions 470).
Regarding claim 6, Evers, in view of Seznec, teaches the apparatus of claim 5, wherein the indication of the given block is dependent on a program counter value (Evers, Fig. 4 [0035]: Block address (indicated as both 405 and 410) is the starting address of a block of instructions. The starting address is a program counter value).
Regarding claim 7, Evers, in view of Seznec, teaches the apparatus of claim 4, wherein
the at least one set-associative storage structure comprises a plurality of set-associative storage structures (Pages 5-6, Section 3.1 “Geometric history length prediction”, Figure 1: In the current combination, the tables (T0-T4) are the plurality of set-associative storage structures comprising of predictions).
in response to a given program flow history, the branch prediction circuitry is configured to identify one or more prediction entries associated with the given program flow history in the long-history storage structure or the short-history storage structure (Evers, Fig. 4 [0035]; Pages 5-6, Section 3.1 “Geometric history length prediction”, Figure 1: In the current combination, the branch predictor storage uses the block address and the branch history to identify prediction entries, which are then sent to the conditional prediction logic if an entry is identified. Each table of Seznec from T0-T4 use different history lengths of the global history (T0 does not use the history length whereas T4 uses the longest history length).
Regarding claim 13, Evers, in view of Seznec, teaches the apparatus of claim 1, wherein the alternate prediction cache is configured to store the at least one alternate path prediction in association with an identifier of the given block of one or more instructions (Evers, [0036]: “Branch prediction information associated with each prediction block in the alternate prediction storage array 462 is indexed based on the corresponding prediction block number.” The indexing of the branch prediction based on the corresponding prediction block number as the identifier).
Regarding claim 14, Evers, in view of Seznec, teaches the apparatus of claim 1, wherein the alternate prediction cache is configured to store the at least one alternate path prediction in association with an offset of the given branch instruction (Evers, Figs. 3 and 4, [0033, 0036, 0038]: Alternate prediction storage array stores the alternate prediction and indexes based on the prediction block number. The prediction block number is associated to a prediction block, which is indicated by a block address (i.e., address 405). The block address may be used to look into the BTB and as a result, give the offset of the first branch instruction. Therefore, the second branch prediction is stored in association with an offset of the first branch instruction).
Regarding claim 19, the claim recites a method similar to the apparatus of claim 1. Therefore, the claim is rejected on the same premises.
Regarding claim 20, the claim is mostly rejected for the same reasons as claim 1. Evers also teaches a non-transitory computer-readable medium storing computer-readable code for fabrication of an apparatus (see [0066-0067]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Evers et al. (US 20190369999 A1, see IDS filed 12/18/2025) in view of Seznec et al. (“A case for (partially) tagged geometric history length branch prediction.”, see IDS filed 03/30/2026) and Abdallah et al. (US 20140281438 A1).
Regarding claim 2, Evers, in view of Seznec, teaches the apparatus of claim 1, wherein
the branch prediction circuitry is configured to return the main path prediction and the at least one alternate path prediction at a prediction stage of a prediction pipeline (Evers, [0015, 0028]: Both the first branch instruction and second branch instruction are predicted at the branch prediction unit. The instructions entering the branch prediction unit as the prediction stage of a prediction pipeline);
the alternate prediction cache is configured to return the at least one alternate path prediction at a control stage later in the prediction pipeline than the prediction stage (Evers, Fig. 4 and [0015, 0028]: The second branch prediction is injected (i.e., returned) in a later stage of the prediction pipeline by the alternate prediction storage array 462. The later stage as the control stage).
Evers, in view of Seznec, does not teach that the alternate prediction cache is configured to return the at least one alternate path prediction at a control stage earlier in the prediction pipeline than the prediction stage.
Abdallah teaches to return a branch prediction at a control stage earlier in a prediction pipeline than the prediction stage (Fig. 4 and [0046-0047]: At the instruction fetch stage, branch prediction information may be sent to the fetch stage of the pipeline. The prediction pipeline being the fetch stage to the execute stage. The fetch stage being earlier in the prediction pipeline than the branch prediction stage).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Evers, in view of Seznec, with the teachings of Abdallah to have returned the branch prediction in the control stage earlier than the prediction stage. One of ordinary skill would recognize that branch predictions can occur after fetching instructions to be able to perform branch prediction on the fetched instructions, improving instruction throughput.
Claims 8-9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Evers et al. (US 20190369999 A1, see IDS filed 12/18/2025) in view of Seznec et al. (“A case for (partially) tagged geometric history length branch prediction.”, see IDS filed 03/30/2026) and Bouzguarrou et al. (US 20210124586 A1).
Regarding claim 8, Evers, in view of Seznec, teaches the apparatus of claim 1, wherein in response to the given branch instruction, the branch prediction circuitry is configured to store the at least one alternate path prediction in the alternate prediction cache (See claim 1 rejection).
Evers, in view of Seznec, does not teach flow tracking circuitry configured to maintain program flow information indicative of one or more observed paths after a candidate branch instruction; and
in a case where the given branch instruction corresponds to the candidate branch instruction, the branch prediction circuitry is configured to store the at least one alternate path prediction in the alternate prediction cache in response to the alternate path of program flow corresponding to one of the one or more observed paths.
Note that in the apparatus of Evers, the branch predictor will always store the alternate branch prediction regardless of whether or not the alternate path of program flow corresponds to an “observed path” (see Fig. 5 and [0037-0044]).
Bouzguarrou teaches flow tracking circuitry configured to maintain program flow information indicative of one or more observed paths after a candidate branch instruction (Figs. 1 and 3, [0064, 0077-0081]: Hard-to-predict branch circuitry 65 consists of cache location buffer 70, which stores hard-to-predict (HTP) branches and sequence of instructions if a HTP branch was taken (see 110) and a sequence of instructions if the HTP branch was not taken (see 125). A HTP branch as the candidate branch instruction and the sequence of instructions after a taken or not taken path as the one or more observed paths).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Evers, in view of Seznec, with the teachings of Bouzguarrou to have tracked HTP branches. HTP branches are known in the art to cause major issues due to being mispredicted more often than regular branch instruction. Therefore, one of ordinary skill is inclined to monitor the HTP branch instructions for further performance analysis or to use alternative means of predicting these instructions.
Regarding claim 9, Evers, in view of Seznec and Bouzguarrou, teaches the apparatus of claim 8, wherein the one or more observed paths comprise information identifying at least one subsequent branch instruction encountered after the candidate branch instruction (Evers, Figs. 4-5, [0033-0044]; Bouzguarrou, Figs. 1 and 3, [0064, 0077-0081]: In the current combination, when an instruction is tracked by the hard to predict circuitry, it will observe the instructions on the taken path and not taken path. When it’s identified that within the instruction block there are two branch instructions and the first branch instruction becomes a hard-to-predict branch to be tracked, then what will happen is that the observed instructions in the not taken path of the first branch instruction will include the second branch instruction. Therefore, one of the observed paths will identify at least one subsequent branch instruction after the first branch instruction).
Regarding claim 11, Evers, in view of Seznec and Bouzguarrou, teach the apparatus of claim 8, wherein the flow tracking circuitry is configured to select the candidate branch instruction in response to a determination that the candidate branch instruction has a misprediction rate exceeding a threshold (Bouzguarrou, Figs. 1 and 4, [0082]: A branch is stored in the cache location buffer 70 within the hard to predict branch circuitry 65 when a prediction accuracy of the instruction is below a threshold. A low prediction accuracy below a threshold can alternatively indicate a high misprediction rate exceeding a threshold).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Evers et al. (US 20190369999 A1, see IDS filed 12/18/2025) in view of Seznec et al. (“A case for (partially) tagged geometric history length branch prediction.”, see IDS filed 03/30/2026), Bouzguarrou et al. (US 20210124586 A1), and Gupta et al. (US 20140195789 A1).
Regarding claim 12, Evers, in view of Seznec and Bouzguarrou, teaches the apparatus of claim 11, comprising a branch target buffer (Evers, Fig. 4 and [0033]: Branch predictor unit 215 consists of a branch target buffer with BTB entries 415)
Evers, in view of Seznec and Bouzguarrou, does not teach that the branch target buffer is configured to store one or more values indicative of the misprediction rate for one or more branch instructions.
Gupta teaches to store one or more values indicative of the misprediction rate for one or more branch instructions (Fig. 3 and [0043-0045]: Each branch prediction entry within branch target buffer 302 corresponds to branch target addresses for one or more branch instructions, where each entry consists of a hysteresis value, which may contain information indicative of the number of mispredictions the entry has generated. The number of mispredictions as the misprediction rate).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Evers, in view of Seznec and Bouzguarrou, with the teachings of Gupta to have the BTB store a misprediction rate. One of ordinary skill may appreciate storing a misprediction rate for each BTB entry as it provides useful information when analyzing/debugging the processor. Additionally, it can be used in conjunction with other performance monitors such as the hard to predict branch circuit in Bouzguarrou to assist further in identifying these highly mispredicted branch instructions.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Evers et al. (US 20190369999 A1, see IDS filed 12/18/2025) in view of Seznec et al. (“A case for (partially) tagged geometric history length branch prediction.”, see IDS filed 03/30/2026) and McDonald et al. (US 20110016292 A1).
Regarding claim 15, Evers, in view of Seznec, teaches the apparatus of claim 1.
Evers, in view of Seznec, does not teach that in response to the at least one taken branch being a return instruction, the branch prediction circuitry is configured to generate the at least one alternate path prediction to comprise a pointer to a call-return stack.
Note that the at least one taken branch indicates that the return instruction is the second branch instruction (see claim 1 mapping above). Therefore, the alternate path prediction would be whatever prediction is used for the return instruction.
McDonald teaches that in response to a branch instruction, the branch prediction circuitry is configured to generate a prediction to comprise a pointer to a call-return stack (Figs. 1-4 [0016, 0019, 0023-0025]: At step 404, branch predictor 128 generates branch information. The branch information is then formatted at step 408 and stored as an entry in the branch information table (BIT) 107. The BIT entry includes the return stack pointer field 208 alongside a predicted target address field 202 for each branch instruction predicted. The BIT as the prediction. The return stack pointer as a type of call-return stack pointer).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Evers, in view of Seznec, with the teachings of McDonald to have a prediction comprise a pointer to a call-return stack. Storing a pointer that points to a call-return stack may be beneficial to one of ordinary skill as the pointer could be utilized by a performance monitor to aid in creating a performance profile or debugging module to trace the program flow in the situation that the processor runs into an error and needs to be debugged.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Evers et al. (US 20190369999 A1, see IDS filed 12/18/2025) in view of Seznec et al. (“A case for (partially) tagged geometric history length branch prediction.”, see IDS filed 03/30/2026) and Henry et al. (US 20050076193 A1).
Regarding claim 16, Evers, in view of Seznec, teaches the apparatus of claim 1.
Evers, in view of Seznec, does not teach that in a case where the given branch instruction is a polymorphic branch instruction, the main path prediction comprises a first target address of the given branch instruction, and the at least one alternate path prediction comprises a second target address of the given branch instruction, and
the alternate prediction cache is configured to store the at least one alternate path prediction in association with the second target address.
Henry teaches that in the case where the branch instruction is a polymorphic branch instruction, the main path prediction comprises a first target address of the given branch instruction (Fig. 1 and [0038]: When a return instruction is present, the address popped from the return stack 104 is provided as the target address (indicated as 142). The return instruction as the polymorphic branch instruction. The target address 142 as the first target address), and the at least one alternate path prediction comprises a second target address of the given branch instruction (Figs. 1 and 2, [0032, 0038]: Branch target address cache (BTAC) array 102 stores target addresses, which may be used as predictions for return instruction instructions. The addresses stored in the BTAC as the at least one alternate path prediction comprising at least one second target address), and
the alternate prediction cache is configured to store the at least one alternate path prediction in association with the second target address (Fig. 1 and [0032]: BTAC array 102 stores the second target addresses, which corresponds to the alternate path predictions).
It would have been obvious to one of ordinary skill in the art before the effective filing date to have combined the teachings of Evers, in view of Seznec, with the teachings of Henry to handle special cases regarding polymorphic instructions in which a second predicted target address corresponding to the polymorphic instruction is stored in an alternate prediction storage. One of ordinary skill would recognize that polymorphic instructions are difficult to predict due to having unusual cases such as non-standard call/return sequences (see [0012]). Therefore, one would be inclined to store alternative branch predictions for these kind of instructions.
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Evers et al. (US 20190369999 A1, see IDS filed 12/18/2025) in view of Seznec et al. (“A case for (partially) tagged geometric history length branch prediction.”, see IDS filed 03/30/2026) and Pant et al. (US 9973187 B1).
Regarding claim 17, Evers, in view of Seznec, teaches a system (Evers, Fig. 1 and [0019]: Processing system 100) comprising:
the apparatus of claim 1, implemented in at least one packaged chip (Evers, Fig. 1 and [0020-0023]: CPU 130 is a packaged chip, which consists of at least one of the cores 131-134 that implement the apparatus); and
at least one system component (Evers, Fig. 1 and [0021]: GPU 115 is a system component).
Evers, in view of Seznec, does not teach a board and that the at least one packaged chip and the at least one system component are assembled on the board.
Pant teaches a board (Col. 4, lines 29-37: SoC is a microchip containing computing components, the microchip to be interpreted as the board), wherein the at least one packaged chip and the at least one system component are assembled on the board (Col. 4, lines 29-37: A CPU and GPU may be assembled on the SoC).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Evers, in view of Seznec, with the teachings of Pant to implement the apparatus on a board as described above. Implementing the CPU alongside other components on a System on Chip would allow one of ordinary skill to implement their design in a compact manner, such that it could implemented within smaller devices such as smartphones or be an additional component for microcontrollers.
Regarding claim 18, Evers, in view of Seznec and Pant, teaches a chip-containing product comprising the system of claim 17, wherein the system is assembled on a further board with at least one other product component (Pant, Col. 4, lines 38-39: In other words, SoC may be mounted on a circuit board, the circuit board to be the further board and disposed on a smart phone, which consists of various product components).
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The statement of reasons for the indication of allowable subject matter can be seen in the Non-Final Office Action mailed December 29, 2025.
Response to Arguments/Amendments
Applicant’s amendments, filed March 30, 2026, with respect to the specification objection has been addressed. The objection of the specification has been withdrawn.
Applicant’s amendments, filed March 30, 2026, with respect to the 112(b) rejections has been addressed. The rejections of claims 5-7 and 13 under 112(b) has been withdrawn.
Applicant’s arguments, see page 12, paragraph 3 to page 16, last paragraph, filed March 30, 2026, with respect to the rejection(s) of claim(s) 1-20 under 102/103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art. See 103 rejections above.
Conclusion
This Office Action is Non-Final. Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILIO ALCANTARA-RAMOS whose telephone number is (571)272-4211. The examiner can normally be reached Mon-Fri 8:30-5:00 PST.
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/E.A./Examiner, Art Unit 2183
/David J. Huisman/Primary Examiner, Art Unit 2183
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