DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-12 are pending in this application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 11/27/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Williams (US 6172542 B1), and further in view of Hashimoto (US 20100007382 A1).
Regarding claim 1, Williams teaches a circuit device (abstract, circuit comprising an input circuit and an adjustable delay) for driving a differential signal bus (abstract, generate a differential signal), comprising:
a high-side device (i.e. output inverter 47, fig.1) placed between a power supply node (e.g. 47 is between VCC and A, fig.1) and a first output terminal (e.g. terminal at output A, fig.1) coupled to the differential signal bus (e.g. terminal at A is coupled to differential signal A, fig.1);
a low-side device (i.e. output inverter 49, fig.1) placed between a ground node (e.g. 49 is between VSS and B, figs.1-2) and a second output terminal (e.g. terminal at output B, fig.1) coupled to the differential signal bus (e.g. terminal at B is coupled to differential signal B, fig.1); and
a drive circuit (e.g. input section 11, squaring section 12, adjustable delay sections 14a and 14b, figs.1-3) configured to output a first drive signal (e.g. output 42, figs.1-3) to one of a control of the high-side device (e.g. input of inverter 47, fig.1) and to output a second drive signal (e.g. output 46, figs.1-3) to another one of the control of the low-side device (e.g. input of inverter 49, fig.1),
wherein the drive circuit includes:
a first delay circuit (e.g. circuit comprising control signal INC, fig.3) configured to set a first delay time (e.g. adjustable delay section 14a, figs.1-3) that is a delay time for a rising edge of the second drive signal (column 3 lines 39-45, when the signal INC is presented to the switch 54, the rising edge of the signal OUT is sped up), and a second delay circuit (e.g. circuit comprising control signal DECB, fig.3) configured to set a second delay time (e.g. adjustable delay section 14a, figs.1-3) that is a delay time for a falling edge of the second drive signal (column 3 lines 39-45, when the signal DECB is presented to the switch 56, the falling edge of the signal OUT is sped up).
Williams does not teach that the high-side device and low-side device is a transistor device.
Hashimoto teaches in a similar field of inverter design, a transistor device (i.e. MOS transistors 101 and 102, fig.1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the transistor device for the inverter in Williams, as taught by Hashimoto, as it provides the advantage of using conventional and optimal design to implement an inverter.
Regarding claim 2, Williams and Hashimoto teach the circuit device according to claim 1, wherein the first delay circuit is configured to set the first delay time based on first delay setting information (Williams, column 3 lines 39-45, when the signal INC is presented to the switch 54, the rising edge of the signal OUT is sped up), and the second delay circuit is configured to set the second delay time based on second delay setting information (Williams, column 3 lines 39-45, when the signal DECB is presented to the switch 56, the falling edge of the signal OUT is sped up).
Regarding claim 3, Williams and Hashimoto teach the circuit device according to claim 2, further comprising: a storage configured to store the first delay setting information and the second delay setting information (Williams, column 4 lines 46-63, the setting of the control signals INC and DECB … signals INC and DECB may be, in one example, adjusted during the edge transitions of the signals A and B) (it is necessarily true that INC and DECB are arriving from a different location, which can be claim equivalent of storage).
Regarding claim 4, Williams and Hashimoto teach the circuit device according to claim 1, wherein the low-side transistor is an n-type transistor (Hashimoto, e.g. N-type MOS transistor 102, fig.1), and the drive circuit is configured to output the second drive signal to a gate of the n-type transistor (Hashimoto, e.g. Vin is input to gate of 102, fig.1).
Regarding claim 5, Williams and Hashimoto teach the circuit device according to claim 1, wherein the first delay time and the second delay time differ in length (Williams, column 4 lines 5-9, the different edges of the signals A and B have different edge rates).
Allowable Subject Matter
Claims 6-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, Williams (US 6172542 B1) and Hashimoto (US 20100007382 A1) teach the circuit device according to claim 1.
Williams and Hashimoto do not teach, wherein the first delay circuit includes a first delay unit configured to delay an input signal to the first delay circuit; and an OR circuit configured to output an OR of the input signal and an output signal from the first delay unit.
Prior art Wrathall (US 6307409 B1), Han (US 20160329808 A1), Seok (US 11342907 B2) and Kishimoto (JP 2012044514 A) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the first delay circuit includes a first delay unit configured to delay an input signal to the first delay circuit; and an OR circuit configured to output an OR of the input signal and an output signal from the first delay unit.”
Regarding claim 7, Williams (US 6172542 B1) and Hashimoto (US 20100007382 A1) teach the circuit device according to claim 1.
Williams and Hashimoto do not teach, wherein the second delay circuit includes a second delay unit configured to delay an input signal to the second delay circuit; and an AND circuit configured to output an AND of the input signal and an output signal from the second delay unit.
Prior art Wrathall (US 6307409 B1), Han (US 20160329808 A1), Seok (US 11342907 B2) and Kishimoto (JP 2012044514 A) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the second delay circuit includes a second delay unit configured to delay an input signal to the second delay circuit; and an AND circuit configured to output an AND of the input signal and an output signal from the second delay unit.”
Regarding claim 8, Williams (US 6172542 B1) and Hashimoto (US 20100007382 A1) teach the circuit device according to claim 1.
Williams and Hashimoto do not teach, wherein the drive circuit further includes a third delay circuit configured to set a third delay time that is a delay time for both the rising edge and the falling edge of the second drive signal.
Prior art Wrathall (US 6307409 B1), Han (US 20160329808 A1), Seok (US 11342907 B2) and Kishimoto (JP 2012044514 A) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the drive circuit further includes a third delay circuit configured to set a third delay time that is a delay time for both the rising edge and the falling edge of the second drive signal.”
Claims 9-10 are indicated as allowable, as they depend on allowable claim 8.
Regarding claim 11, Williams (US 6172542 B1) and Hashimoto (US 20100007382 A1) teach the circuit device according to claim 1.
Williams and Hashimoto do not teach, wherein the drive circuit further includes a delay correction circuit configured to correct a delay time of the first delay circuit and a delay time of the second delay circuit.
Prior art Wrathall (US 6307409 B1), Han (US 20160329808 A1), Seok (US 11342907 B2) and Kishimoto (JP 2012044514 A) have been found to be the closest prior art.
However, none of the prior art, taken singly or in combination, teach “wherein the drive circuit further includes a delay correction circuit configured to correct a delay time of the first delay circuit and a delay time of the second delay circuit.”
Claim 12 is indicated as allowable, as it depends on allowable claim 11.
Conclusion
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/SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 06/18/2026
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