DETAILED ACTION
This Office action is in response to the application filed on November 27, 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on October 06, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings were filed on November 27, 2024. These drawings are accepted by the Examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chuang (U.S. Pat. No. 11,463,082 B2, reference provided as part of the Information Disclosure Statement “IDS”).
In re claim 1, Chaung discloses (Fig. 7) a driving circuit (700) for a switching device (10), comprising: a pulse width modulation circuit (110) comprising an input terminal and an output terminal; and a resistor-capacitor series circuit (R2, C1) comprising an input terminal (N1) and an output terminal (N2), wherein: the output terminal of the pulse width modulation circuit (110) is connected to an input terminal of the resistor-capacitor series circuit, the output terminal of the resistor-capacitor series circuit is connected to a control terminal of the switching device (10), the pulse width modulation circuit is configured to output a level pulse signal for turning on the switching device, and the resistor-capacitor series circuit is configured to reduce an edge slope of the level pulse signal (Col. 10, lines 14-55).
In re claim 2, Chaung discloses (Fig. 7) wherein: the resistor-capacitor series circuit (R2, C1) comprises a first resistor (R2) and a first capacitor (C1), a first terminal of the first resistor is connected to the output terminal of the pulse width modulation circuit (110), a second terminal of the first resistor is connected to a first terminal of the first capacitor (right side terminal of R2 is connected to C1), and a second terminal of the first capacitor is connected to the control terminal of the switching device (right side terminal of C1 is connected to the control terminal of 10).
In re claim 3, Chaung discloses (Fig. 7) further comprising a waveform conversion circuit comprising a second resistor (R1), wherein the second resistor is connected in parallel to the first resistor and the first capacitor (R1 is in parallel with R2 and C1).
In re claim 7, Chaung discloses (Fig. 7) wherein the input terminal of the pulse width modulation circuit is connected to an external power supply device (VH, VL).
In re claim 8, Chaung discloses (Fig. 7) wherein: an output terminal of the switching device is connected to a voltage stabilizing input device (UC), and a ground terminal of the pulse width modulation circuit and an input terminal of the switching device are connected to a ground node (Col. 10, lines 14-55).
In re claim 9, Chaung discloses (Fig. 7) wherein the switching device comprises one of a metal oxide semiconductor field effect transistor (MOSFET), a junction field-effect transistor (JFET), or an insulated gate bipolar transistor (IGBT) (10 is a MOSFET).
In re claim 10, Chaung discloses wherein the control terminal comprises a gate (Fig. 7).
Allowable Subject Matter
Claims 4-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 4, the prior art of record fails to disclose or suggest “a discharge circuit connected in parallel to the first resistor” in combination with other limitations of the claim. Claims 5-6 depend directly or indirectly from claim 4 and are, therefore, also objected at least for the same reasons set above.
Claims 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 11, the prior art of record fails to disclose or suggest “a discharge circuit connected in parallel to the first resistor” in combination with other limitations of the claim. Claims 12-20 depend directly or indirectly from claim 11 and are, therefore, also allowable at least for the same reasons set above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAFAEL O. DE LEÓN DOMENECH whose telephone number is (571)270-0517. The examiner can normally be reached 8:00 a.m. -5:00 p.m..
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/RAFAEL O DE LEON DOMENECH/Primary Examiner, Art Unit 2838
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