Prosecution Insights
Last updated: August 17, 2026
Application No. 18/961,859

RAPID BURST MODE SERDES TUNING

Non-Final OA §103
Filed
Nov 27, 2024
Examiner
SANCHEZ, DIBSON J
Art Unit
2634
Tech Center
2600 — Communications
Assignee
Avago Technologies International Sales Pte. Limited
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
394 granted / 532 resolved
+12.1% vs TC avg
Strong +22% interview lift
Without
With
+22.3%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
18 currently pending
Career history
550
Total Applications
across all art units

Statute-Specific Performance

§101
3.1%
-36.9% vs TC avg
§103
63.7%
+23.7% vs TC avg
§102
6.4%
-33.6% vs TC avg
§112
26.5%
-13.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 532 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-5 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over IIyama et al (US Pub 20210258075) in view of Van Veen et al (US Pub 20110255866). Regarding Claim 1. IIyama discloses an apparatus comprising: a receiver configured to: receive a stream of bursts from a plurality of units, one of the units being an electronic device (Fig 1, Fig 2, where an apparatus (e.g. 5) comprises a receiver (e.g. 11) (as shown in Fig 2) configured to receive a stream of bursts from a plurality of units (e.g. 50), one of the units (e.g. 50) being an electronic device); an analog-to-digital converter configured to: receive an upstream burst from the receiver during an active time slot, the upstream burst being one of the bursts, and convert, in response to sampling the upstream burst at a sample rate, the upstream burst from an analog waveform into a sequence of digital values (Fig 1, Fig 2, where the apparatus (e.g. 5) comprises an analog-to-digital converter (e.g. 12) (e.g. as shown in Fig 2) configured to receive an upstream burst from the receiver (e.g. 11) during an active time slot (i.e. an allocated time to transmit an uplink signal) (similar to Fig 29), the upstream burst being one of the bursts, and convert, in response to sampling the upstream burst at a sample rate, the upstream burst from an analog waveform into a sequence of digital values (para [78])); and control circuitry configured to: store, in response to a coefficient for the electronic device being a default coefficient, the digital values into memory during the active time slot (Fig 1, Fig 2, Fig 3, where the apparatus (e.g. 5) comprises control circuitry (e.g. 133, 135) (e.g. as shown in Fig 2) configured to store, in response to a coefficient (e.g. from 135) for the electronic device being a default coefficient (i.e. a coefficient given in advance) (para [83]), the digital values into a delay/memory (e.g. 31) (e.g. as shown in Fig 3) (here the delay 31 acts as a memory because data is trapped in the delay 31 and the data is preserved in time) during the active time slot (i.e. an allocated time to transmit an uplink signal) (similar to Fig 29)). IIyama fails to explicitly disclose the receiver being a transceiver. However, Van Veen discloses a receiver being a transceiver (Fig 5, where a receiver (e.g. 204) is a transceiver (e.g. 200, 204)). Therefore, it would have been obvious to one of ordinary skill in the art to combine the teachings of the receiver (e.g. 11) as described in IIyama, with the teachings of the receiver (e.g. 204) as described in Van Veen. The motivation being is that as shown a receiver (e.g. 204) is a transceiver (e.g. 200, 204) and one of ordinary skill in the art can implement this concept into the receiver (e.g. 11) as described in IIyama and better show and illustrate that the receiver (e.g. 11) is a transceiver (e.g. 200, 11) i.e. because the apparatus (e.g. 5) optimally communicates with the units (e.g. 50) in a bi-directionally manner and the apparatus (e.g. 5) comprises a transceiver with a transmitter that optimally transmits data to the units (e.g. 50) and with a receiver that optimally receives data from the units (e.g. 50) in order to perform PON communications and which combination is being made because the systems are similar and have overlapping components (e.g. PONs, receivers,…) and which combination is a simple implementation of a known concept of a known receiver (e.g. 204) into another similar receiver (e.g. 11), namely, for better clarifying its operation/configuration and which combination yields predictable results. Regarding Claim 2. IIyama as modified by Van Veen also discloses the apparatus, wherein the active time slot is a time period where the transceiver receives any one of the bursts in the stream (IIyama Fig 1, Fig 2, Fig 3, where the active time slot (i.e. an allocated time to transmit an uplink signal) (similar to Fig 29) is a time period where the receiver (e.g. 11) (transceiver) receives any one of the bursts in the stream). Regarding Claim 3. IIyama as modified by Van Veen also discloses the apparatus, wherein the transceiver is configured to receive the stream of bursts in real time (IIyama Fig 1, Fig 2, Fig 3, where the receiver (e.g. 11) (transceiver) is configured to receive the stream of bursts in real time (i.e. live communications)). Regarding Claim 4. IIyama as modified by Van Veen also discloses the apparatus, wherein the upstream burst comprises multiple packets of information (IIyama Fig 1, Fig 2, Fig 3, where the apparatus (e.g. 5) receives the upstream burst and where it is known that the upstream burst comprises multiple packets of information (see for example Soto et al (US Pub 20090016714) Fig 7 burst from ONT J)). Regarding Claim 5. IIyama as modified by Van Veen also discloses the apparatus, wherein the sequence is a digital representation of the analog waveform (IIyama Fig 1, Fig 2, Fig 3, where the sequence (e.g. from analog-to-digital converter 12) is a digital representation of the analog waveform). Regarding Claim 18. Claim 18 is similar to claim 1, therefore, claim 18 is rejected for the same reasons as claim 1. Regarding Claim 19. A Claim 19 is similar to claim 1, therefore, claim 19 is rejected for the same reasons as claim 1. Regarding Claim 20. Claim 20 is similar to claim 4, therefore, claim 20 is rejected for the same reasons as claim 4. Allowable Subject Matter Claims 6-17 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the Examiner should be directed to DIBSON J SANCHEZ whose telephone number is (571)272-0868. The Examiner can normally be reached on Mon-Fri 10:00-6:00. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Kenneth Vanderpuye can be reached on 5712723078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DIBSON J SANCHEZ/ Primary Examiner, Art Unit 2634
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Prosecution Timeline

Nov 27, 2024
Application Filed
Aug 07, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
74%
Grant Probability
96%
With Interview (+22.3%)
2y 1m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 532 resolved cases by this examiner. Grant probability derived from career allowance rate.

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