Prosecution Insights
Last updated: October 02, 2026
Application No. 18/962,037

ISOLATED SWITCHING CIRCUIT WITH SHORT-CIRCUIT PROTECTION AND METHOD THEREOF

Non-Final OA §102§103
Filed
Nov 27, 2024
Priority
Nov 30, 2023 — CN 202311639005.4
Examiner
COMBER, KEVIN J
Art Unit
Tech Center
Assignee
Chengdu Monolithic Power Systems Co., Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
719 granted / 870 resolved
+22.6% vs TC avg
Moderate +12% lift
Without
With
+11.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
28 currently pending
Career history
882
Total Applications
across all art units

Statute-Specific Performance

§101
1.6%
-38.4% vs TC avg
§103
57.4%
+17.4% vs TC avg
§102
22.7%
-17.3% vs TC avg
§112
13.2%
-26.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 870 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are pending in this application. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement(s) (IDS) submitted on 11/27/2024 and 12/30/2025 is/are in compliance with the provisions of 37 C.F.R. § 1.97. Accordingly, the IDS has/have been considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. U.S. Patent Application 2019/0140547 (hereinafter “Chang”). Regarding claim 15, Chang teaches a method for controlling an isolated switching circuit (refer to figures 1, 3, and 5), comprising: sampling and holding (refer to sample-and-hold circuit 1323)(fig.5) an auxiliary winding voltage (refer to DMAG and tertiary winding W3)(fig.1)(refer also to fig.3) of a transformer of the isolated switching circuit (i.e. transformer 15)(fig.1) to obtain an auxiliary winding sampling voltage (implicit); providing a short-circuit indicating signal based on the auxiliary winding sampling voltage (i.e. S2)(fig.5)(refer also to [0042]); and controlling the isolated switching circuit based on the short-circuit indicating signal (refer to [0042]), and controlling the isolated switching circuit to stop operating when the short-circuit indicating signal indicates that an output terminal of the isolated switching circuit is short-circuited (refer to [0042]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1, 2, 7-9, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Majid et al. U.S. Patent No. 6,087,782 (hereinafter “Majid”) and further in view of Chang. Regarding claim 1, Majid teaches a control circuit (i.e. controller IC)(fig.1)(refer also to fig.2) for an asymmetrical half-bridge flyback converter (refer to fig.1), comprising: a short-circuit indicating circuit (i.e. over-current/over-power protection circuit 36)(fig.2)(refer also to col. 7 lines 29-45) configured to receive an auxiliary winding voltage (refer to auxiliary voltage Vaux and auxiliary winding TL4)(fig.1) of a transformer of the asymmetrical half-bridge flyback converter (i.e. transformer T)(fig.1); and a short-circuit processing circuit (i.e. logic circuit 16)(fig.2) configured to receive the short-circuit indicating signal (implicit)(refer to input bus 20)(fig.2), and to provide at least one short-circuit control signal (refer to output of comparators 48 and 50)(fig.8) to control the asymmetrical half-bridge flyback converter based on the short-circuit indicating signal (refer to col. 4 lines 38-40), wherein the short-circuit control signal is configured to control the asymmetrical half-bridge flyback converter to stop operating when the short-circuit indicating signal indicates that an output terminal of the asymmetrical half-bridge flyback converter is short-circuited (refer to col. 7 lines 54-62); however, Majid does not teach the short-circuit indicating circuit configured to provide a short-circuit indicating signal based on the auxiliary winding voltage. However, Chang teaches the short-circuit indicating circuit configured to provide a short-circuit indicating signal based on the auxiliary winding voltage (refer to DMAG and short circuit detection circuit 132)(fig.3)(refer also to fig.5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Majid to include the short-circuit indicating signal of Chang to provide the advantage of detecting a short circuit in the current sensor. Regarding claim 2, Majid and Chang teach the control circuit of claim 1, wherein the short-circuit indicating circuit comprises: a voltage detecting circuit (i.e. Chang delay time generation circuit 1320 and sample-and-hold circuit 1323)(fig.5) configured to receive an auxiliary winding sampling voltage (implicit), and to provide a voltage detecting signal based on the auxiliary winding sampling voltage (implicit)(refer to Chang fig.5), wherein the auxiliary winding sampling voltage is provided based on the auxiliary winding voltage (implicit); and a counting circuit (i.e. Chang counter 134)(fig.3) configured to receive the voltage detecting signal, and to provide the short-circuit indicating signal based on the voltage detecting signal (refer to Chang [0042]). Regarding claim 7, Majid and Chang teach the control circuit of claim 2, wherein the short-circuit indicating circuit further comprises: a sample and hold circuit (i.e. Chang sample-and-hold circuit 1323)(fig.5) configured to be coupled to an auxiliary winding of the transformer to receive the auxiliary winding voltage (implicit), and to provide the auxiliary winding sampling voltage based on the auxiliary winding voltage (implicit), wherein the auxiliary winding sampling voltage is obtained by sampling and holding the auxiliary winding voltage during a time period when a secondary switch of the asymmetrical half-bridge flyback converter is on (implicit). Regarding claim 8, Majid teaches an asymmetrical half-bridge flyback converter (refer to fig.1), comprising: a first switch (i.e. switching device Tr1)(fig.1); a second switch (i.e. switching device Tr2)(fig.1) coupled in series with the first switch (implicit) between an input terminal of the asymmetrical half-bridge flyback converter and a primary side reference ground (implicit)(refer to fig.1); a transformer (i.e. transformer T)(fig.1) having a primary winding (i.e. primary winding TL1)(fig.1), a secondary winding (i.e. secondary winding TL2)(fig.1) and an auxiliary winding (i.e. auxiliary winding TL4)(fig.1), wherein the primary winding is coupled to a switching terminal (i.e. SH output)(fig.1) between the first switch and the second switch (implicit); a resonant capacitor (i.e. capacitor C2)(fig.1) coupled in series with the primary winding of the transformer (implicit)(refer to fig.1); and a control circuit (i.e. controller IC)(fig.1)(refer also to fig.2), comprising: a short-circuit indicating circuit (i.e. over-current/over-power protection circuit 36)(fig.2)(refer also to col. 7 lines 29-45) configured to receive an auxiliary winding voltage (refer to auxiliary voltage Vaux and auxiliary winding TL4)(fig.1) of the transformer (implicit); and a short-circuit processing circuit (i.e. logic circuit 16)(fig.2) configured to receive the short-circuit indicating signal (implicit)(refer to input bus 20)(fig.2), and to provide a first short-circuit control signal (refer to output of comparator 48)(fig.8) and a second short-circuit control signal (refer to output of comparator 50)(fig.8) based on the short-circuit indicating signal (implicit) to control the first switch and the second switch, respectively (refer to col. 4 lines 38-40), wherein the first switch and the second switch are turned off when the short-circuit indicating signal indicates that an output terminal of the asymmetrical half-bridge flyback converter is short-circuited (refer to col. 7 lines 54-62); however, Majid does not teach the short-circuit indicating circuit configured to provide a short-circuit indicating signal based on the auxiliary winding voltage. However, Chang teaches the short-circuit indicating circuit configured to provide a short-circuit indicating signal based on the auxiliary winding voltage (refer to DMAG and short circuit detection circuit 132)(fig.3)(refer also to fig.5). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Majid to include the short-circuit indicating signal of Chang to provide the advantage of detecting a short circuit in the current sensor. Regarding claim 8, Majid and Chang teach the asymmetrical half-bridge flyback converter of claim 8, wherein the short-circuit indicating circuit comprises: a voltage detecting circuit (i.e. Chang delay time generation circuit 1320 and sample-and-hold circuit 1323)(fig.5) configured to receive an auxiliary winding sampling voltage (implicit), and to provide a voltage detecting signal based on the auxiliary winding sampling voltage (implicit)(refer to Chang fig.5), wherein the auxiliary winding sampling voltage is provided based on the auxiliary winding voltage (implicit); and a counting circuit (i.e. Chang counter 134)(fig.3) configured to receive the voltage detecting signal, and to provide the short-circuit indicating signal based on the voltage detecting signal (refer to Chang [0042]). Regarding claim 14, Majid and Chang teach the asymmetrical half-bridge flyback converter of claim 9, wherein the short-circuit indicating circuit further comprises: a sample and hold circuit (i.e. Chang sample-and-hold circuit 1323)(fig.5) configured to be coupled to an auxiliary winding of the transformer to receive the auxiliary winding voltage (implicit), and to provide the auxiliary winding sampling voltage based on the auxiliary winding voltage (implicit), wherein the auxiliary winding sampling voltage is obtained by sampling and holding the auxiliary winding voltage during a time period when a secondary switch of the asymmetrical half-bridge flyback converter is on (implicit). Allowable Subject Matter Claims 3-6, 10-13, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for the indication of allowable subject matter: Claims 3 and 4 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 3, especially wherein the voltage detecting circuit comprises: a comparison circuit configured to receive the auxiliary winding sampling voltage and a short-circuit reference voltage, and to provide the voltage detecting signal based on the auxiliary winding sampling voltage and the short-circuit reference voltage; and wherein the counting circuit is configured to count a number of times when the voltage detecting signal indicates that the auxiliary winding sampling voltage is less than the short-circuit reference voltage, and the short-circuit indicating signal indicates that the output terminal of the asymmetrical half-bridge flyback converter is short-circuited when the number of times reaches a set value. Claim 4 is indicated as containing allowable subject matter based on its dependency on claim 3. Claims 5 and 6 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 5, especially wherein the voltage detecting circuit comprises: a difference circuit configured to receive the auxiliary winding sampling voltage, and to provide a difference voltage based on a difference between auxiliary winding sampling voltages of two adjacent switching cycles; and a comparison circuit configured to receive the difference voltage and a difference reference voltage, and to provide the voltage detecting signal based on the difference voltage and the difference reference voltage; and wherein the counting circuit is configured to count a number of times when the voltage detecting signal indicates that the difference voltage is greater than the difference reference voltage, and the short-circuit indicating signal indicates that the output terminal of the asymmetrical half-bridge flyback converter is short-circuited when the number of times reaches a set value. Claim 6 is indicated as containing allowable subject matter based on its dependency on claim 5. Claims 10 and 11 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 10, especially wherein the voltage detecting circuit comprises: a comparison circuit configured to receive the auxiliary winding sampling voltage and a short-circuit reference voltage, and to provide the voltage detecting signal based on the auxiliary winding sampling voltage and the short-circuit reference voltage; and wherein the counting circuit is configured to count a number of times when the voltage detecting signal indicates that the auxiliary winding sampling voltage is less than the short-circuit reference voltage, and the short-circuit indicating signal indicates that the output terminal of the asymmetrical half-bridge flyback converter is short-circuited when the number of times reaches a set value. Claim 11 is indicated as containing allowable subject matter based on its dependency on claim 10. Claims 12 and 13 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 12, especially wherein the voltage detecting circuit comprises: a difference circuit configured to receive the auxiliary winding sampling voltage, and to provide a difference voltage based on a difference between auxiliary winding sampling voltages of two adjacent switching cycles; and a comparison circuit configured to receive the difference voltage and a difference reference voltage, and to provide the voltage detecting signal based on the difference voltage and the difference reference voltage; and wherein the counting circuit is configured to count a number of times when the voltage detecting signal indicates that the difference voltage is greater than the difference reference voltage, and the short-circuit indicating signal indicates that the output terminal of the asymmetrical half-bridge flyback converter is short-circuited when the number of times reaches a set value. Claim 13 is indicated as containing allowable subject matter based on its dependency on claim 12. Claims 16 and 17 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 16, especially wherein the step of providing the short-circuit indicating signal based on the auxiliary winding sampling voltage comprises: providing a voltage detecting signal based on the auxiliary winding sampling voltage and a short-circuit reference voltage; and counting a number of times when the voltage detecting signal indicates that the auxiliary winding sampling voltage is less than the short-circuit reference voltage, and providing the short-circuit indicating signal to indicate that the output terminal of the isolated switching circuit is short-circuited when the number of times reaches a set value. Claim 17 is indicated as containing allowable subject matter based on its dependency on claim 16. Claims 18-20 are indicated as containing allowable subject matter because prior art fails to teach or suggest, either alone or in combination all of the limitations of claim 18, especially wherein the step of providing the short-circuit indicating signal based on the auxiliary winding sampling voltage comprises: providing a difference voltage based on a difference between auxiliary winding sampling voltages of two adjacent switching cycles; providing a voltage detecting signal based on the difference voltage and a difference reference voltage; and counting a number of times when the voltage detecting signal indicates that the difference voltage is greater than the difference reference voltage, and providing the short-circuit indicating signal to indicate that the output terminal of the isolated switching circuit is short-circuited when the number of times reaches a set value. Claim 19 and 20 are indicated as containing allowable subject matter based on its dependency on claim 18. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Furuisuu et al. Chinese Patent Document CN 112311240 A (figures 1-3) and Xu U.S. Patent Application 2022/0416644 (figures 3-5) disclose similar circuits/methods. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN J COMBER whose telephone number is (571)272-6133. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KEVIN J COMBER/Primary Examiner, Art Unit 2838
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Prosecution Timeline

Nov 27, 2024
Application Filed
Aug 26, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
94%
With Interview (+11.8%)
2y 4m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 870 resolved cases by this examiner. Grant probability derived from career allowance rate.

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