DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/04/2026 has been entered.
Claim Objections
Claim 15 is objected to because of the following informalities:
As to claim 15, the phrase “a first scan signal” in line 15 of the claim should be changed to “a first gate signal” in order to be consistent with “the first gate signal” recited in lines 17 and 20 of the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 10 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Imamura et al. (US 2004/0257353 A1).
As to claim 1, Imamura et al. teaches a pixel circuit (Fig. 3) comprising:
a driving element (driving transistor 17 in Fig. 3) including a first electrode connected to a first node (first node in Fig. 3) to which a pixel driving voltage is applied (power source VEL in Fig. 3), a gate electrode connected to a second node (second node in Fig. 3) to which a data voltage is applied ([0074]: voltage of image signal is supplied), and a second electrode (second electrode of driving transistor 17 in Fig. 3);
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a light-emitting element (organic EL element 16 in Fig. 3) including an anode electrode (anode electrode of organic EL element 16 in Fig. 3) and a cathode electrode (cathode electrode of organic EL element 16 in Fig. 3), the light- emitting element configured to emit light by current from the driving element ([0075]: driving current flows to the organic EL element 16 through the driving transistor 17);
a first switch element (transistor 22 in Fig. 3) connected to the anode electrode (anode electrode of organic EL element 16 in Fig. 3) and the cathode electrode (cathode electrode of organic EL element 16 in Fig. 3), the first switch element (transistor 22 in Fig. 3) configured to electrically connect the anode electrode (anode electrode of organic EL element 16 in Fig. 3) and the cathode electrode electrode(cathode electrode of organic EL element 16 in Fig. 3) to each other in response to a first gate signal(write signal R in Fig. 3;[0071]); and
a second switch element (transistor 21 in Fig. 3) connected to the first node (first node in Fig. 3) and the second node (second node in Fig. 3), the second switch element (transistor 21 in Fig. 3) configured to electrically connect the first node (first node in Fig. 3) and the second node (second node in Fig. 3) to each other in response to the first gate signal (write signal R in Fig. 3;[0071]).
As to claim 10, Imamura et al. teaches a display device ([0060]: display device) comprising:
a display panel (111 in Fig. 6;[0060]) including a plurality of data lines ([0061]: data lines 12), a plurality of gate lines ([0061]: scanning lines 11), a plurality of pixel circuits ([0061]: pixels), a cathode power line (GND line in Fig. 3;[ 0074]: GND potential) configured to supply a cathode voltage to a pixel circuit from the plurality of pixel circuits ([0061]: pixels), a driving power line configured to
supply a pixel driving voltage to the pixel circuit ([0061]: power wiring line 35, Fig. 3), and an initialization power line (Vee line in Fig. 3) configured to supply an initialization voltage to the pixel circuit ([0072]: voltage Vee supplied through reset transistor 23);
a data driving circuit (15 in Fig. 6) configured to output a data voltage of pixel data to the plurality of data lines ([0061]: data line driver 15 outputting pixel driving signals to data lines); and
a gate driving circuit (14 in Fig. 6) configured to sequentially output a gate signal to the plurality of gate lines ([0061]: scanning line driver 14 for driving the plurality of scanning lines), wherein the pixel circuit ([0061]: pixel) includes:
a driving element (driving transistor 17 in Fig. 3) including a first electrode connected to a first node (first node in Fig. 3) to which a pixel driving voltage is applied (power source VEL in Fig. 3), a gate electrode connected to a second node (second node in Fig. 3) to which the data voltage is applied ([0074]: voltage of image signal is supplied), and a second electrode (second electrode of driving transistor 17 in Fig. 3);
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a light-emitting element (organic EL element 16 in Fig. 3) including an anode electrode (anode electrode of organic EL element 16 in Fig. 3) and a cathode electrode (cathode electrode of organic EL element 16 in Fig. 3) connected to the cathode power line (GND line in Fig. 3;[0072]), the light- emitting element configured to emit light by current from the driving element ([0075]: driving current flows to the organic EL element 16 through the driving transistor 17);
a first switch element (transistor 22 in Fig. 3) connected to the anode electrode (anode electrode of organic EL element 16 in Fig. 3) and the cathode electrode (cathode electrode of organic EL element 16 in Fig. 3), the first switch element (transistor 22 in Fig. 3) configured to electrically connect the anode electrode (anode electrode of organic EL element 16 in Fig. 3) and the cathode electrode electrode(cathode electrode of organic EL element 16 in Fig. 3) to each other in response to a first gate signal(write signal R in Fig. 3;[0071]); and
a second switch element (transistor 21 in Fig. 3) connected to the first node (first node in Fig. 3) and the second node (second node in Fig. 3), the second switch element (transistor 21 in Fig. 3) configured to electrically connect the first node (first node in Fig. 3) and the second node (second node in Fig. 3) to each other in response to the first gate signal (write signal R in Fig. 3;[0071]).
As to claim 15, Imamura et al. teaches a display panel ([0061]: display module 100) comprising:
a display area (111 in Fig. 6) on which an input image is displayed ([0061]: organic EL panel 111 display images);
a non-display area outside the display area (non- display area outside of display panel 111 in Fig. 6);
a plurality of cathode power lines within the display area (GND line in pixel in Fig. 3; [0061]: plurality of pixels; [0070];[0072]: ground potential GND is supplied to the source electrode of the driving transistor in pixel); and
a plurality of pixel circuits in the display area ([0061]: organic EL panel 111 have a plurality of display pixels PX),
wherein each of the plurality of pixel circuits ([0061]: pixels) includes:
a driving element (driving transistor 17 in Fig. 3) including a first electrode connected to a first node (first node in Fig. 3) to which a pixel driving voltage is applied (power source VEL in Fig. 3), a gate electrode connected to a second node (second node in Fig. 3) to which a data voltage is applied ([0074]: voltage of image signal is supplied), and a second electrode (second electrode of driving transistor 17 in Fig. 3);
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a light-emitting element (organic EL element 16 in Fig. 3) including an anode electrode (anode electrode of organic EL element 16 in Fig. 3) and a cathode electrode (cathode electrode of organic EL element 16 in Fig. 3) connected to the cathode power line (GND line in Fig. 3;[0072]), the light- emitting element configured to emit light by current from the driving element ([0075]: driving current flows to the organic EL element 16 through the driving transistor 17);
a first switch element (transistor 22 in Fig. 3) including a first electrode connected to the anode electrode (anode electrode of organic EL element 16 in Fig. 3), a second electrode connected to the cathode electrode (cathode electrode of organic EL element 16 in Fig. 3), and a gate electrode to which
a first scan signal is applied (write signal R in Fig. 3;[0071]), the first switch element (transistor 22 in Fig. 3) configured to electrically connect the anode electrode (anode electrode of organic EL element 16 in Fig. 3) and the cathode electrode to each other (cathode electrode of organic EL element 16 in Fig. 3) in response to the first gate signal (write signal R in Fig. 3;[0071]); and
a second switch element (transistor 21 in Fig. 3) connected to the first node (first node in Fig. 3) and the second node (second node in Fig. 3), the second switch element (transistor 21 in Fig. 3) configured to electrically connect the first node (first node in Fig. 3) and the second node (second node in Fig. 3) to each other in response to the first gate signal (write signal R in Fig. 3;[0071]),
wherein the cathode electrode of the light-emitting element (cathode electrode of organic EL element 16 in Fig. 3) and the second electrode of the first switch element (transistor 22 in Fig. 3) are connected to a corresponding cathode power line from the plurality of cathode power lines (GND line in pixel in Fig. 3;[0061]: plurality of pixels; [0070];[0072]: ground potential GND is supplied to the source electrode of the driving transistor in pixel).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imamura et al. (US 2004/0257353 A1) in view of Wang (CN 202796001 U, attached English machine translation is used in the rejection).
As to claim 2, Imamura et al. teaches the pixel circuit of claim 1, wherein the first switch element (transistor 22 in Fig. 3) is configured to be turned on ([0070-0071]: transistor 22 is electrically conducted) and maintain an electrical connection of the anode electrode and the cathode electrode to each other ([0070-0071]: transistor 22 electrically connecting the pixel electrode (anode electrode) and the cathode electrode), but does not explicitly disclose the first switch element is configured to be turned on until the light-emitting element emits the light by the current and maintain an electrical connection of the anode electrode and the cathode electrode to each other until the light-emitting element emits the light.
However, Wang teaches the first switch element is configured to be turned on until the light-emitting element emits the light by the current ([0066];[0068]: stage t2, transistor S109 is in the on state;[0069]: stage t3, pixel driving current flows into OLED S110, lighting up the display) and maintain an electrical connection of the anode electrode and the cathode electrode to each other until the light-emitting element emits the light ([0068]: stage t2, transistor S109 is in the on state;[0069]: stage t3, pixel driving current flows into OLED S110, lighting up the display).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Imamura et al. such that the first switch element is configured to be turned on until the light-emitting element emits the light by the current and maintain an electrical connection of the anode electrode and the cathode electrode to each other until the light-emitting element emits the light as taught by Wang in order to avoid uneven display brightness.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Imamura et al. (US 2004/0257353 A1) in view of Son et al. (US 2023/0071094 A1).
As to claim 16, Imamura et al. teaches the display panel of claim 15, but does not explicitly disclose further comprising: a first shorting bar on one side of the non-display area and connected to one end of each of the plurality of cathode power lines; and a second shorting bar on another side of the non-display area and connected to another end of each of the plurality of cathode power lines.
However, Son et al. teaches further comprising: a first shorting bar (34 in Fig. 3) on one side of the non-display area (area outside pixel array AA in Fig. 3) and connected to one end of each of the plurality of cathode power lines ([0092]: VSS lines connected to shorting bar 34); and a second shorting bar (36 in Fig. 3) on another side of the non-display area (area outside pixel array AA in Fig. 3) and connected to another end of each of the plurality of cathode power lines ([0092]: VSS lines connected to shorting bar 36).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Imamura et al. with a first shorting bar on one side of the non-display area and connected to one end of each of the plurality of cathode power lines, and a second shorting bar on another side of the non-display area and connected to another end of each of the plurality of cathode power lines as taught by Son et al. in order to improve image quality.
Allowable Subject Matter
Claims 3-9, 12-14 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 18 is allowed.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 10 and 15-16 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
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/STACY KHOO/Primary Examiner, Art Unit 2624