Prosecution Insights
Last updated: August 15, 2026
Application No. 18/962,139

TEST JIG

Non-Final OA §103
Filed
Nov 27, 2024
Priority
Jul 19, 2024 — CN 202410972983.9
Examiner
RODAK, LEE E
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fulian Precision Electronics (Tianjin) Co., Ltd.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
1y 0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
268 granted / 372 resolved
+4.0% vs TC avg
Strong +34% interview lift
Without
With
+34.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
53 currently pending
Career history
372
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
53.5%
+13.5% vs TC avg
§102
20.4%
-19.6% vs TC avg
§112
21.5%
-18.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 372 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-6 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over AKATA et al. (Pub NO. US 2023/0417844 A1; hereinafter Akata) in view of Dutta et al. (Pub NO. US 2022/0178971 A1; hereinafter Dutta). Regarding Claim 1, Akata teaches a test jig (test jig in Fig. 2 and Fig. below; See [0016]-[0035]) comprises: a first port (See the first port upper 15 in Fig. 2 and Fig. below; See [0024]-[0025]), a first end of the first port configured to connect to a first device (first end of upper 15 is connected to first device 11 in Fig. 2 and Fig. below; See [0016]-[0035]); a second port (See the second port lower 15 in Fig. 2 and Fig. below; See [0024]-[0025]), a first end of the second port configured to connect to a second device (first end of lower 15 is connected to second device 20 in Fig. 2 and Fig. below; See [0016]-[0035]); a measurement conductor (L2 in Fig. 2 and Fig. below), two ends of the measurement conductor are connected with a second end of the first port and a second end of the second port respectively (two ends of L2 are connected to second end of upper 15 and lower 15 in Fig. 2 and Fig. below; See [0016]-[0035]); a device, electrically connected with the measurement conductor in parallel (See the device 13 is connected parallel to measurement conductor L2 in Fig. 2 and Fig. below; See [0016]-[0035]); PNG media_image1.png 848 850 media_image1.png Greyscale Akata is silent about a current transformer; a current output port, electrically connected with an output end of the current transformer and configured to output a to-be-test current. Dutta teaches a current transformer (current transformer 210 in fig. 4); a current output port (current output port 420 in Fig. 4; See [0044]-[0055]), electrically connected with an output end of the current transformer and configured to output a to-be-test current (420 is electrically connected to output end of current transformer 210 and configured to output test current in Fig. 4; See [0044]-[0055]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the device of Akata by using current transformer and a current output port, electrically connected with an output end of the current transformer and configured to output a to-be-test current of Dutta in order to achieve effective sensing apparatus (Dutta; abstract). Regarding Claim 2, Akata in view of Dutta teaches the test jig of claim 1. Akata further teaches wherein the measurement conductor comprises a first piece, a second piece, and a third piece; an edge of the first piece extends a distance along a direction away from a sidewall of the first piece to form the second piece; an end of the second piece away from the first piece bends and extends a distance to form the third piece (See first, second and third pieces of L2 in Fig. 2 and Fig. below; See [0016]-[0035]). PNG media_image2.png 840 794 media_image2.png Greyscale Regarding Claim 3, Akata in view of Dutta teaches the test jig of claim 2, wherein two ends of the first piece are connected to the second end of the first port and the second end of the second port (See all pieces of L2 are connected to upper 15 and lower 15 in Fig. 2; See [0016]-[0035]); the device is electrically connected with the third piece in parallel (device 13 is connected parallel with L2 in Fig. 2; See [0016]-[0035]). Akata is silent about the current transformer. Dutta teaches a current transformer (current transformer 210 in fig. 4); a current output port (current output port 420 in Fig. 4; See [0044]-[0055]).. Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the device of Akata by using current transformer of Dutta in order to achieve effective sensing apparatus (Dutta; abstract). Regarding Claim 4, Akata in view of Dutta teaches the test jig of claim 3, wherein the first port comprises a first positive terminal (current path from positive to negative terminal of 15 in Fig. 2; See [0026]-[0035]); the second port comprises a second positive terminal (current path from positive to negative terminal of 15 in Fig. 2; See [0026]-[0035]); two ends of the first piece are connected to the first positive terminal of the second end of the first port and the second positive terminal of the second end of the second port respectively (all pieces of L2 are connected to positive terminals of 15 where current flows in fig. 2; See [0026]-[0035]). Regarding Claim 5, Akata in view of Dutta teaches the test jig of claim 1. Akata further teaches wherein the one of the first port and the second port is a chip connector (upper port 15 is connected to chip 11, therefore chip connector n Fig. 2; See [0016]-[0035). Akata is silent about another of the first port and the second port is a busbar. Dutta teaches another of the first port and the second port is a busbar (See [0077], [0115]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the device of Akata by using another of the first port and the second port is a busbar of Dutta in order to achieve effective sensing apparatus (Dutta; abstract). Regarding Claim 6, Akata in view of Dutta teaches the test jig of claim 1. Akata further teaches wherein the test jig further comprises a voltage output port (port of 12 in Fig. 2; See [0028]); the voltage output port is connected to the first port and the second port, and is configured to output a to-be-tested voltage (all ports of 12, 15 are connected in Fig. 2; See [0016]-[0035]). Regarding Claim 8, Akata in view of Dutta teaches the test jig of claim 1. Akata is silent about wherein the test jig further comprises a power port; the power port is electrically connected to a power input terminal of the current transformer; the power port is configured to connect to the power supply. Dutta teaches wherein the test jig further comprises a power port (See [0036]); the power port is electrically connected to a power input terminal of the current transformer (See [0036]); the power port is configured to connect to the power supply (See [0036]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the device of Akata by using the test jig further comprises a power port; the power port is electrically connected to a power input terminal of the current transformer; the power port is configured to connect to the power supply of Dutta in order to achieve effective sensing apparatus (Dutta; abstract). Claim(s) 7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Akata in view of Dutta in view of Lau et al. (Pub NO. US 2019/0392297 A1; hereinafter Lau). Regarding Claim 7, Akata in view of Dutta teaches the test jig of claim 6. Dutta further teaches wherein the current output port (See [0035]) and the voltage output port (See [0034]). Akata in view of Dutta is silent about port are Sub Miniature version B (SMB) connectors. Lau teaches port are Sub Miniature version B (SMB) connectors (SMB port 1005; See [0067]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the device of Akata and Dutta by using SMB ports of Lau in order to achieve effective communication system (Lau; [0067]). Regarding Claim 9, Akata in view of Dutta further in view of Lau teaches the test jig of claim 7. Akata in view of Lau is silent about wherein the test jig further comprises a housing with openings at a sidewall; opposite sides of the housing define a first notch and a second notch respectively; the first port is disposed in the first notch, and the second port is disposed in the second notch; the measurement conductor and the current transformer are disposed in the housing. Dutta teaches wherein the test jig further comprises a housing with openings at a sidewall (housing 210, 215 has opening 214 at sidewall in Fig. 2); opposite sides of the housing define a first notch and a second notch respectively (housing 210 has notch 212 and housing 215 has notch 218 in Fig. 2); the first port is disposed in the first notch, and the second port is disposed in the second notch (all ports of 310 are disposed in notch 212 in Fig. 3); the measurement conductor and the current transformer are disposed in the housing (measurement conductor 253 and current transformer 251, 252 are disposed inside housing 210, 215 in Fig. 2; See [0047]-[0049]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention was made to modify the device of Akata and Lau by using test jig further comprises a housing with openings at a sidewall; opposite sides of the housing define a first notch and a second notch respectively; the first port is disposed in the first notch, and the second port is disposed in the second notch; the measurement conductor and the current transformer are disposed in the housing of Dutta in order to achieve effective sensing apparatus (Dutta; abstract). Regarding Claim 10, Akata in view of Dutta further in view of Lau teaches the test jig of claim 9. Dutta further teaches wherein the housing defines a receiving slot (bus 1335 is receiving slot; See [0115]); the receiving slot configured to receive an insulation component (See [0115]); the current output port and the voltage output port are disposed on the insulation component (sense port 230 is disposed on insulation; See [0053]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Neumueller et al. (Patent NO. US 10,027,068 B2) discloses Current transformer is connected to input and output ports. Yagi et al. (Patent NO. US 5,586,900 A) discloses Test Jig with Connector, hood member and plate member. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZANNATUL FERDOUS whose telephone number is (571)270-0399. The examiner can normally be reached Monday through Friday 8am to 5pm (PST). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rodak Lee can be reached at 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ZANNATUL FERDOUS/Examiner, Art Unit 2858 /LEE E RODAK/Supervisory Patent Examiner, Art Unit 2858
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Prosecution Timeline

Nov 27, 2024
Application Filed
Jul 31, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
99%
With Interview (+34.3%)
2y 8m (~1y 0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 372 resolved cases by this examiner. Grant probability derived from career allowance rate.

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