DETAILED ACTION
Status of Claims
Claims 1 – 20 are pending.
Claims 1, 10, and 12 are independent.
This office action is Non-Final.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 10 and 11 are rejected under 35 U.S.C. 101 because they are directed to transitory signals. As per claims 10 and 11, they are rejected because the applicant has provided evidence that the applicant intends the term "computer-readable storage medium” to include non-statutory matter. The applicant describes a computer-readable storage medium as including open ended language and thus it is reasonable to interpret it to include all possible mediums, including non-statutory mediums (see paragraphs 0213, 0221, and 0222). The words "storage" and/or "recording" are insufficient to convey only statutory embodiments to one of ordinary skill in the art absent an explicit and deliberate limiting definition or clear differentiation between storage media and transitory media in the disclosure. As such, the claims are drawn to a form of energy. Energy is not one of the four categories of invention and therefore these claims are not statutory. Energy is not a series of steps or acts and thus is not a process. Energy is not a physical article or object and as such is not a machine or manufacture. Energy is not a combination of substances and therefore not a composition of matter.
The Examiner suggests amending the claims to read as a “non-transitory machine-readable storage medium”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 -5, 9-16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pillilli et al (US Patent Application Publication No. 2020/0349010 A1, hereinafter Pillilli ).
As per claim 1, Pillilli teaches a method for rebooting a functional component on a system on chip [0048, 0055, fig. 9: system on a chip], comprising [0148 – 0149: method for granular resets of portions of a system to independently reset a target subsystem…without preforming a system wide reboot, claim 20, claim 24]:
performing access isolation on a first bus interface of a first functional component on the system on chip [0180: Blocking may include preventing any other components of a system from using the target subsystem.]; and a shared bus [0152, 0179: processor interconnects, processor buses, and interface gaskets are used to pass information safely between core logic and subsystem] shared by at least two operating systems [0149: collaborative runtime structure involving two software (operating system or other software and BIOS)] on the system on chip in response to detecting that a state of the first functional component is a first state [0151, 0180: receiving an indication/command to reset a malfunctioning block or subsystem (the first state), the system blocks interaction with it]
rebooting the first functional component to transition the first functional component from the first state to a second state [0181: independent cycling of the target block/subsystem from an error/failed configuration into an initialized operational state (the second state)] ; and
performing access dis-isolation on the first bus interface of the first functional component and the shared bus [0199, claim 12, claim 20, claim 25: upon completion of the granular reset of the target subsystem, unblock use of the target subsystem].
As per claim 2, Pillilli teaches the method according to claim 1, wherein the performing access isolation on a first bus interface of a first functional component and a shared bus comprises:
disconnecting a transmission path between the first bus interface and the shared bus to prevent an access request of the first functional component from being transmitted to the shared bus; or terminating forwarding the access request of the first functional component to the shared bus [0177, 0199: prior to applying the reset, the system must stop traffic to the target subsystem or IP block and block the use of the subsystem].
As per claim 3, Pillilli teaches the method according to claim 1, wherein after the performing access isolation on a first bus interface of a first functional component and a shared bus, the method further comprises: detecting whether the first bus interface of the first functional component and the shared bus are in an idle state; wherein the rebooting the first functional component comprises: rebooting the first functional component in response to detecting that the first bus interface and the shared bus are in the idle state [0180: a draining step is applied directly before a reset command is issued. Verifying that all pending bus transactions are fully completed is the functional implementation of verifying an idle interface state before initiating a reboot].
As per claim 4, Pillilli teaches the method according to claim 1, wherein the performing access isolation on a first bus interface of a first functional component on the system on chip and a shared bus shared by at least two operating systems on the system on chip in response to detecting that a state of the first functional component is a first state comprises: generating an access isolation enable signal in response to detecting that the state of the first functional component is the first state; and performing access isolation on the first bus interface of the first functional component and the shared bus based on the access isolation enable signal [0151, 0172: system captures an error notification or threshold exception to activate isolation; each domain may include circuitry or logic to gate off clocks and turn of power supply to a group of IP blocks within a subsystem ].
As per claim 5, Pillilli teaches the method according to claim 1, wherein the performing access dis-isolation on the first bus interface of the first functional component and the shared bus comprises: generating an access dis-isolation signal; connecting a transmission path between the first bus interface and the shared bus based on the access dis-isolation signal to enable the first functional component to access the shared bus again; or starting forwarding an access request of the first functional component to the shared bus based on the access dis-isolation signal [0199: once the determination that the reset is complete, the component is unblocked, which prompts the BIOS to execute code to restart traffic to the subsystem].
As per claim 9, Pillilli The method according to claim 1, wherein the rebooting the first functional component to transition the first functional component from the first state to the second state comprises: transitioning a reset signal of the first functional component from a non-enabled state to an enabled state to transition the first functional component from the first state to a reset state; and transitioning the reset signal of the first functional component from an enabled state to a non-enabled state to transition the first functional component from the reset state to the second state [0181: Resetting a subsystem may include deasserting a power supply, gating clocks to the subsystem, resetting any PLLs, or applying any other suitable reset mechanism. Accordingly, a reset management circuit may cause the target subsystem to be reset by implementing one or more suitable reset mechanisms.].
As per claim 101, Pillilli teaches a [non-transitory] computer readable storage medium storing a computer program thereon, which is used for performing the following steps: performing access isolation on a first bus interface of a first functional component on the system on chip and a shared bus shared by at least two operating systems on the system on chip in response to detecting that a state of the first functional component is a first state; rebooting the first functional component to transition the first functional component from the first state to a second state; and performing access dis-isolation on the first bus interface of the first functional component and the shared bus [claim 12, claim 13, 0149].
As per claim 11, Pillilli teaches the [non-transitory] computer readable storage medium according to claim 10, wherein the performing access isolation on a first bus interface of a first functional component and a shared bus comprises: disconnecting a transmission path between the first bus interface and the shared bus to prevent an access request of the first functional component from being transmitted to the shared bus; or terminating forwarding the access request of the first functional component to the shared bus [0177, 0199: prior to applying the reset, the system must stop traffic to the target subsystem or IP block and block the use of the subsystem].
As per claims 12 – 16, and 20, it is directed to an apparatus to implement the method of steps set forth in claims 1 – 5, and 9. Pillilli teaches the claimed method steps. Therefore, Pillilli teaches the apparatus to implement the claims steps.
Allowable Subject Matter
Claims 6 – 8, and 17 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huntley; Barry E. et al. (US Patent Application Publication No. 2018/0341496 A1) “Dynamic Microsystem Reconfiguration With Collaborative Verification” is cited to teach a method that dynamically reconfigures a system on a chip (SOC) with multiple semiconductor intellectual property (IP) blocks. When booting a data processing system (DPS) includes the SOC, automatically allocating different IP blocks to multiple different microsystems within the DPS, based on a static partitioning policy (SPP). The method also includes, after booting the DPS, determining that reallocation of at least one of the IP blocks is desired, based on (a) monitored conditions of at least one of the microsystems and (b) a dynamic partitioning policy (DPP). In response to determining that reallocation of at least one of the IP blocks is desired, automatically reallocating at least one of the IP blocks from one of the microsystems to another of the microsystems without resetting at least one of the microsystems.
Ryu; Sueng-Chul et al. (US Patent Application Publication No. 2018/0157553) “System Interconnect And System On Chip Having The Same” is cited to teach a system on chip (SoC) that includes a bus matrix configured to connect a plurality of functional blocks. A monitoring unit is configured to monitor whether a transaction between the functional blocks has a hang or stall and distinguish a functional block that caused a hang or stall from among the functional blocks. A recovery signal generation unit is configured to provide a recovery signal for releasing the hang or stall to at least one of the functional blocks based on the distinguishing by the monitoring unit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERRELL S JOHNSON whose telephone number is (571)270-3485. The examiner can normally be reached 10AM-7PM EST M-F.
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/TERRELL S JOHNSON/Primary Examiner, Art Unit 2176
1 Claim 10 is rejected for reasons as set forth in the detailed rejection of claim1 hereinabove to the extent applicable.
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