DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1-20 are currently pending in the application, with claims 1, 10, and 17 being independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 25 February 2025 has been considered by the examiner.
Claim Objections
Claims 10 is objected to because of the following informalities:
Claim 10 should recite “by the stored graphics work”, since the previous limitation recites storing graphics work. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 1, given the plain and ordinary meaning of the words when afforded their broadest reasonable interpretation in light of the corresponding disclosure, the scope of the claimed limitations is unclear. For instance, it is not immediately clear as to how the power control circuitry controls power state of portions of the graphics processor based on status of multiple primary queues and assigned sets of graphics work. What are the portions of the graphics processor? What is the status of the primary queues? The examiner respectfully requests the applicant clarify the scope of the claimed limitation.
Claims 10 and 17 recite similar limitations as those noted with respect to claim 1 and are also rejected using substantially similar rationale as to that set forth with respect to claim 1.
Claims depending thereon do not cure the noted deficiencies and are also rejected using substantially similar rationale as to that of the claims from which they depend.
With respect to claim 4, given the plain and ordinary meaning of the words when afforded their broadest reasonable interpretation in light of the corresponding disclosure, the scope of the claimed limitations is unclear. For instance, it is not immediately clear as how the power state is based on a category of execution hardware of the GP in addition to the items noted in claim 1. The examiner respectfully requests the applicant clarify the scope of the claimed limitation.
Claims 13 and 19 recite similar limitations as those noted with respect to claim 4 and are also rejected using substantially similar rationale as to that set forth with respect to claim 4.
With respect to claim 6, given the plain and ordinary meaning of the words when afforded their broadest reasonable interpretation in light of the corresponding disclosure, the scope of the claimed limitations is unclear. For instance, it is not immediately clear as how the power state is based on the size of one or more sets of graphics work, in addition to the items noted in claim 1. The examiner respectfully requests the applicant clarify the scope of the claimed limitation.
Claim 14 recite similar limitations as those noted with respect to claim 6 and is also rejected using substantially similar rationale as to that set forth with respect to claim 6.
With respect to claim 7, given the plain and ordinary meaning of the words when afforded their broadest reasonable interpretation in light of the corresponding disclosure, the scope of the claimed limitations is unclear. For instance, it is not immediately clear as how the power state is based on priorities of the multiple primary queues, in addition to the items noted in claim 1. What is a priority of the multiple primary queues? The examiner respectfully requests the applicant clarify the scope of the claimed limitation.
Claim 15 recite similar limitations as those noted with respect to claim 7 and is also rejected using substantially similar rationale as to that set forth with respect to claim 7.
With respect to claim 17, given the plain and ordinary meaning of the words when afforded their broadest reasonable interpretation in light of the corresponding disclosure, the scope of the claimed limitations is unclear. For instance, it is not immediately clear as to how the instructions of a hardware description programming language to generate a computer simulation model, the model representing a graphics processor. Is the claim claiming a virtual processor? It is not clear as to how the hardware circuitry represents the claimed elements while also being a model the represents the circuit. The examiner respectfully requests the applicant clarify the scope of the claimed limitation.
Claims depending thereon do not cure the noted deficiencies and are also rejected using substantially similar rationale as to that of the claims from which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-12, 14-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fishwick et al. (US PG Publication 2023/0048951) in view of Tsien et al. (US PG Publication 2022/0091657)
Regarding claim 1, Fishwick teaches an apparatus, comprising: a graphics processor that includes: at least first and second graphics processor sub-units that respectively (Multiple programmable shader units are included in a GPU, see for instance, paragraph 39) include:
distributed work queue circuitry configured to store graphics work (The global control circuitry may assign work to the different sub-portions of the GPU which may in turn assign work to shader cores to be processed by shader pipelines, see for instance, paragraph 39. Sub-units, in some embodiments, are scaling units that may be replicated to increase the processing capabilities of a GPU, with each GPU sub-unit may be capable of independently processing instructions of a graphics program, see for instance, paragraph 48. Sub-units, in the illustrated embodiment, include circuitry that implements respective distributed hardware slots, these hardware slots may also be referred to herein as "dSlots", see for instance, paragraph 48. Primary control circuitry assigns work from a logical slot to at most one distributed hardware slot in each sub-unit, see for instance, paragraph 48. Each sub-unit includes fragment generator circuitry, shader core circuitry configured to execute shader programs, memory system circuitry (which may include one or more caches and a memory management unit), geometry processing circuitry, and distributed workload distribution circuitry, which may coordinate with primary control circuitry to distribute work to shader pipelines, see for instance, paragraph 48); and
shader circuitry configured to execute instructions specified by stored graphics work in the sub-unit's distributed work queue circuitry (The global control circuitry may assign work to the different sub-portions of the GPU which may in turn assign work to shader cores to be processed by shader pipelines, see for instance, paragraph 39. Sub-units, in some embodiments, are scaling units that may be replicated to increase the processing capabilities of a GPU, with each GPU sub-unit may be capable of independently processing instructions of a graphics program, see for instance, paragraph 48. Sub-units, in the illustrated embodiment, include circuitry that implements respective distributed hardware slots, these hardware slots may also be referred to herein as "dSlots", see for instance, paragraph 48. Primary control circuitry assigns work from a logical slot to at most one distributed hardware slot in each sub-unit, see for instance, paragraph 48. Each sub-unit includes fragment generator circuitry, shader core circuitry configured to execute shader programs, memory system circuitry (which may include one or more caches and a memory management unit), geometry processing circuitry, and distributed workload distribution circuitry, which may coordinate with primary control circuitry to distribute work to shader pipelines, see for instance, paragraph 48. A given subunit includes multiple programmable shaders, see for instance, paragraph 50);
work control circuitry that includes (see for instance, paragraph 39 and fig. 8):
queue access circuitry configured to access graphics work in multiple primary queues; distribution circuitry configured to assign portions of respective sets of graphics work accessed from the multiple primary queues to the first and second graphics processor sub-units for execution (The global control circuitry may assign work to the different sub-portions of the GPU which may in turn assign work to shader cores to be processed by shader pipelines, see for instance, paragraph 39. Control circuitry provides status information to software for the first set of graphics work. The control circuitry may support various status states, including without limitation: waiting on dependencies, waiting for configuration data for the first set of graphics work, waiting for assignment distributed slots, waiting for hardware resources, empty, programming complete, waiting for a logical slot, deallocating, and context stored, see for instance, paragraph 210);
tracking circuitry configured to track status of assigned sets of graphics work (see for instance, paragraphs 171-181 and fig. 19. Circuitry maintains the following information for each tracking slot: identifier, status, data identification, dependencies, run data, and configuration, see for instance, paragraph 172); and
power control circuitry, wherein the work control circuitry is configured to communicate with the power control circuitry to control power state of portions of the graphics processor based on: status of multiple primary queues; and status of assigned sets of graphics work tracked by the tracking circuitry (Kickslot manager is configured to perform one or more power control operations based on tracking slots, see for instance, paragraph 189. For example, control circuitry may reduce the power state of one or more circuits, see for instance, paragraph 189. Control circuitry may reduce the power state of the pixel data master even when it has a kick in a tracking slot, see for instance, paragraph 189. In some embodiments, the first action for a scheduled tracking slot is an increase in the power state of any associated circuitry, if it is in a lower power state than desired, see for instance, paragraph 190. For example, control circuitry may start pixel kicks by writing a power-on register for the pixel data master, see for instance, paragraph 190. Speaking generally, the device may power gate various types of logic and power those logic blocks on when a tracking slot will use that logic, see for instance, paragraph 190. In some embodiments, kickslot manager maintains one or more flags for each tracking slot that that indicate whether the kick assigned to the tracking slot uses one or more types of circuitry, see for instance, paragraph 190. Kickslot manager may cause those types of circuitry to meet a required power state in response to scheduling of those tracking slots, see for instance, paragraph 190. The control circuitry determines respective hold values for slots of the plurality of logical slots, where the hold values indicate status of kernels for a logical slot, see for instance, paragraph 196. The control circuitry may allow a logical slot with a first priority level to reclaim a hardware slot that is assigned to a logical slot with a second, lower priority level, based on one or more of the respective hold values, see for instance, paragraph 196.).
While Fishwick teaches the broadest reasonable interpretation of claim 1, Tsien is being brought in to teach powering different components of a system according to work issued, such as powering down in an idle state, see for instance, paragraphs 40-42. The power controller and accompanying circuitry throughout the processing node are capable of power gating components of node or reducing a power management state of the components, see for instance, paragraph 34.
Fishwick and Tsien are in the same art of processors. It would have been obvious to one of ordinary skill in the art having the teachings of Fishwick and Tsien in front of them before the effective filing date of the claimed invention to incorporate power management as taught by Tsien into Fishwick’s graphics processor system, as adjusting the power state based on workload, such as described by Tsien was well known at the time of the effective filing date invention and would have yielded predictable results in combination with Fishwick.
The modification of Fishwick with Tsien would have explicitly allowed the powering down/up the subunit based on workload.
The motivation for combining Fishwick with Tsien would have been to improve the user experience, enhance functionality and power management.
Regarding claim 2, Fishwick in view of Tsien teach the apparatus of claim 1 and further teach wherein the power control circuitry is configured to power down the first graphics processor sub-unit and not the second graphics processor sub-unit based on a request from the work control circuitry (see for instance, Fishwick paragraphs 189-192 and Tsien, paragraphs 40-42). The motivation to combine Fishwick and Tsien is the same as that which was set forth with respect to claim 1.
Regarding claim 3, Fishwick in view of Tsien teach the apparatus of claim 2 and further teach wherein the power control circuitry is configured to power down the first graphics processor sub-unit while the second graphics processor sub-unit is still executing a portion of a same set of graphics work for which the first graphics processor sub-unit has completed execution of its portion (see for instance, Fishwick paragraphs 39, 48, 49, and 189-192 and Tsien, paragraphs 40-42). The motivation to combine Fishwick and Tsien is the same as that which was set forth with respect to claim 1.
Regarding claim 5, Fishwick in view of Tsien teach the apparatus of claim 1, wherein the portions of the graphics processor include one or more first portions of the first graphics processor sub-unit but not one or more second portions of the first graphics processor sub-unit (see for instance, Fishwick paragraphs 39, 48, 49, and 189-192 and Tsien, paragraphs 40-42). The motivation to combine Fishwick and Tsien is the same as that which was set forth with respect to claim 1.
Regarding claim 6, Fishwick in view of Tsien teach the apparatus of claim 1, wherein the control of power state is based on a size of one or more sets of graphics work (see for instance, Fishwick paragraphs 39, 48, 49, and 189-192 and Tsien, paragraphs 40-42). The motivation to combine Fishwick and Tsien is the same as that which was set forth with respect to claim 1.
Regarding claim 7, Fishwick in view of Tsien teach the apparatus of claim 1 and further teach wherein the control of power state is based on priorities of the multiple primary queues (see for instance, Fishwick paragraphs 39, 48, 49, and 189-192 and Tsien, paragraphs 40-42). The motivation to combine Fishwick and Tsien is the same as that which was set forth with respect to claim 1.
Regarding claim 8, Fishwick in view of Tsien teach the apparatus of claim 1 and further teach wherein: the first and second graphics processor sub-units further include configuration registers configured to store control register data corresponding to stored graphics work; the multiple primary queues are stored in a data structure in memory and respective queues enqueue control information for multiple sets of graphics work; and the work control circuitry is configured to assign sets of graphics work to logical slots and map a logical slot to multiple graphics processor sub-units to distribute portions of a set of graphics work assigned to the logical slot to multiple distributed hardware slots of multiple graphics processor sub-units (see for instance, Fishwick paragraphs 39, 48-52, and 189-192 and Tsien, paragraphs 40-42). The motivation to combine Fishwick and Tsien is the same as that which was set forth with respect to claim 1.
Regarding claim 9, teaches the apparatus of claim 1, wherein the apparatus is a computing device that further includes: a central processing unit; a display; and network interface circuitry (see for instance, Fishwick paragraphs 39, 41, 43, and 231-240 and Tsien, paragraphs 18, and 40-42). The motivation to combine Fishwick and Tsien is the same as that which was set forth with respect to claim 1.
Regarding claims 10 and 17, claims 10 and 17 recite substantially similar limitations as to that recited in claim 1 and are rejected using substantially similar rationale as to that set forth for claim 1. In addition, Fishwick in view of Tsien teach a non-transitory computer-readable medium having instructions of a hardware description programming language stored thereon that, when processed by a computing system, program the computing system to generate a computer simulation model, wherein the model represents a hardware circuit that includes: a graphics processor (see for instance, Fishwick, paragraph 245-251)
Regarding claims 11 and 18, claims 11 and 18 recite substantially similar limitations as to that recited in claim 2 and are rejected using substantially similar rationale as to that set forth for claim 2.
Regarding claim 12, claim 12 recites substantially similar limitations as to that recited in claim 3 and are rejected using substantially similar rationale as to that set forth for claim 3.
Regarding claim 14, claim 14 recites substantially similar limitations as to that recited in claim 6 and are rejected using substantially similar rationale as to that set forth for claim 6.
Regarding claim 15, claim 15 recites substantially similar limitations as to that recited in claim 7 and are rejected using substantially similar rationale as to that set forth for claim 7.
Regarding claim 16, claim 16 recites substantially similar limitations as to that recited in claim 8 and are rejected using substantially similar rationale as to that set forth for claim 8.
Regarding claim 20, claim 20 recites substantially similar limitations as to that recited in claim 5 and are rejected using substantially similar rationale as to that set forth for claim 5.
Allowable Subject Matter
Since no prior art is being applied, claims 4, 134, and 19 would be allowable if rewritten to overcome the rejection(s), set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J COBB whose telephone number is (571)270-3875. The examiner can normally be reached Monday - Friday, 11am - 7pm ET.
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/MICHAEL J COBB/ Primary Examiner, Art Unit 2615
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