DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I (Claims 1-14) in the reply filed on 13 November 2025 is acknowledged.
Drawings
The drawings are subject to objection because the unlabeled rectangular boxes that are used in lieu of detailed illustration, shown in the drawings, should be provided with descriptive text labels (numbers alone are insufficient). See MPEP 608.02(b), Form Paragraph 6.22, Examiner Note 1; MPEP 608.02(d); 37 CFR 1.83(a). These unlabeled boxes are abstract shapes and not illustrative. Please provide descriptive text labels in Fig. 1 for rectangular boxes 120, 130, 140, 150, in Fig. 4 for boxes 130, 140, 300, 310. If there is insufficient room inside boxes, the text labels may be located adjacent to numbers outside boxes; separate from the numbers but connected by lead line; or in a legend. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 2 is subject to objection because of the following informalities.
Regarding claim 2, it is recommended that a comma be inserted in line 2 between “on the shielding layer and the common electrode” and “and interposed”, so as to read “…on the shielding layer and the common electrode, and interposed…”
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0139291 A1 (Asozu) in view of US 2023/0217734 A1 (Lee).
Regarding claim 1, Asozu teaches a display device (Abstract) comprising:
a substrate divided into a display area and a non-display area (Figs. 2 at 50, 60, 7 at 50, 60);
a gate driving circuit on the substrate and in the non-display area (Fig. 7 at 38);
a plurality of gate clock lines on the substrate, the plurality of gate clock lines outside the gate driving circuit (Figs. 5 at 11, 6 at 11: the term gate clock lines is broad enough to read on the gate scan lines 11);
a passivation layer on the plurality of gate clock lines (Fig. 6 at 31);
a common electrode on the passivation layer and non-overlapping with the plurality of gate clock lines (Fig. 6 at 4); and
a shielding layer located in the non-display area, on the passivation layer, and overlapping with the plurality of gate clock lines (Fig. 6 at 6).
Asozu does not expressly teach the passivation layer on the gate driving circuit. Lee teaches a passivation layer on the gate driving circuit (Fig. 2 at PAS, 200). Furthermore, Lee teaches the passivation layer on the gate driving circuit and the plurality of gate clock lines ([81]: the scan line SL may be formed together with the gate electrode G, which is shown in Fig. 2 below the passivation layer PAS). The suggestion to modify the teaching of Asozu by the teaching of Lee is present as both teach matrix driving including a gate driving using scan lines. Further suggestion is provided by Asozu’s teaching that the array substrate comprises the insulating layer 31 in a single layer that includes both the display and non-display area ([32], [41], [55]). The motivation is to insulate both the gate driver and scan lines. Thus, before the effective filing date of the current application, the combination of Asozu and Lee would have rendered obvious, to one of ordinary skill in the art, a passivation layer on the gate driving circuit and the plurality of gate clock lines.
Regarding claim 10, Asozu further teaches wherein the shielding layer is spaced apart from the common electrode and is non-overlapping with the common electrode in a vertical direction (Figs. 6 at 6, 4).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2017/0139291 A1 (Asozu) in view of US 2023/0217734 A1 (Lee) as applied to claim 1 above, and further in view of US 2016/0064465 A1 (Oh) and US 2020/0393936 A1 (Bok).
Regarding claim 9, Asozu and Lee do not expressly teach a ground line disposed further outside the plurality of gate clock lines. Oh teaches a ground line disposed further outside the plurality of gate clock lines (Fig. 13 at VSS). Bok teaches a ground line disposed further outside the plurality of other signal lines in a configuration similar to Asozu (Fig. 17 at GRL1, GRL3). Further suggestion and motivation to use a ground line is present as Asozu is an electronic device, and using a ground is a basic feature of most electronic devices, including display devices. Thus, before the effective filing date of the current application, the combination of Asozu, Lee, Oh, and Bok would have rendered obvious, to one of ordinary skill in the art, a ground line disposed further outside the plurality of gate clock lines.
Allowable Subject Matter
Claims 2-8, 11-13 are subject to objection as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 14 is allowed.
The following is a statement of reasons for the indication of allowable subject matter.
Claims 2-8 and 11-13, subject to objection as being dependent upon a rejected claim, would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, because the prior art cited to reject the aforementioned base and intervening claims does not subsequently teach or render obvious the dependent claims indicated as otherwise allowable in the full context of the claims. Nor does any observed additional prior art in combination with the cited prior art render obvious the dependent claims indicated as being allowable in the full context of the claims.
Regarding independent claim 14, the prior art does not anticipate or render obvious, in the context of the entire claim, wherein the shielding pattern overlaps with at least one signal line.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2024/0121989 A1, US 2024/0389394 A1, US 2024/0397752 A1, US 2024/0357872 A1, and US 2024/0114726 A1 each teach a display device comprising: a substrate including a display area and a non-display area; at least one signal line on the substrate and in the display area; a pixel electrode on the overcoat layer; a bank having a bank hole overlapping with at least a portion of the pixel electrode; a common electrode on the bank and extending inside the bank hole; and a shielding pattern on the bank, wherein the common electrode is disconnected by the shielding pattern.
US 2023/0004253 A1 (Shin) does not teach a shielding layer located in the non-display area, on the passivation layer, and overlapping with the plurality of gate clock lines, so it cannot serve as a reference under 35 USC 102 for claims 2 and 4. Regarding the question of obviousness, there is a lack of rationale to combine Shin with Asozu, particularly because the terms “ shielding layer” and “common electrode” read onto different items for Asozu than the elements they would read onto with the Shin reference. Regarding claim 14, Shin does not teach wherein the common electrode (Fig. 9 at E2) is disconnected by the shielding pattern (Fig. 9 at SE), and the shielding pattern overlaps with at least one signal line (E2-CL).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GENE W LEE whose telephone number is (571)270-7148. The examiner can normally be reached M-F 9:45am-6:15pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LunYi Lao can be reached at 571-272-7671. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Gene W Lee/Primary Examiner, Art Unit 2621