DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 8-12, 14-16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Fishwick (U.S. Publication 2023/0048951) in view of Chheda (U.S. Publication 2020/0104138).
As to claim 1, Fishwick discloses an apparatus, comprising:
a graphics processor, comprising control circuitry configured to schedule and distribute different portions of sets of assigned graphics work to multiple different graphics processor sub-units (p. 1-2, section 0031; p. 4, section 0048; a GPU assigns/schedules and distributes work to GPU sub-units);
memory circuitry (p. 20, section 0272);
and a processor configured to execute a program that coordinates to send work to the graphics processor (p. 3, sections 0045-0047; p. 5, sections 0072-0074; processors running manager programs send work to the GPUs), including to:
store, in the memory circuitry, configuration register data and queued sets of graphics work to be executed by the graphics processor (p. 4, sections 0049-0052; p. 15, section 0214; p. 16, section 0225; the memory contains configuration register data as well as sets of graphics work in a queue);
and transmit a signal, to the control circuitry of the graphics processor, to change status of one or more queued sets of graphics work in the memory circuitry, wherein, in response to the signal, the control circuitry is configured to schedule and distribute the one or more queued sets of graphics work to the graphics processor sub-units (p. 13, sections 0191-p. 14, section 0196; p. 15, sections 0209-0215; based on signaled graphics work changes from software, which would be running on the processor, the work is assigned/scheduled and distributed to different sub-units).
Fishwick does not disclose, but Chheda discloses that the processor executing the program is executing a driver program for the graphics processor and the program sending work is coordinating with the driver program (p. 1, section 0029-p. 2, section 0035; the graphics driver program is coordinated with the graphics scheduler that sends graphic work items to different queues). The motivation for this is to communicate between a user and a graphics processor (p. 15, section 0150). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Fishwick to have the processor executing the program execute a driver program for the graphics processor and have the program sending work coordinate with the driver program in order to communicate between a user and a graphics processor as taught by Chheda.
As to claim 2, Chheda discloses wherein the signal to the control circuitry is a write to a control register of the control circuitry (p. 1-2, section 0031; p. 12, section 0122; a signal indicating a reset state status change is sent by writing a reset to a register controlling the graphics hardware; this results in the graphics work being flushed and potentially resubmitted). The motivation for this is to compensate for a hung streamer or piece of graphics hardware (p. 1, section 0030). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to further modify Fishwick to write to a control register of the control circuitry in order to compensate for a hung streamer or piece of graphics hardware as taught by Chheda.
As to claim 3, Fishwick discloses an apparatus further comprising: a firmware processor configured to control one or more operations of the graphics processor (p. 11, section 0169; p. 12, section 0178; the firmware processor handles some interrupts in the control of operations); wherein the signal by the processor to the control circuitry does not utilize the firmware processor and the firmware processor does not participate in launching the one or more queued sets of graphics work (p. 11, sections 0166-0169; p. 12, sections 0176-0178; p. 13, sections 0191-p. 14, section 0196; p. 15, sections 0209-0215; control of the graphics work is offloaded from a firmware processor to dedicated hardware).
As to claim 8, Fishwick discloses wherein the control circuitry is kickslot manager circuitry that includes tracking slot circuitry configured to store software-accessible status information for tracking slots (p. 5, section 0063; the kickslot manager circuitry has tracking information regarding allocations and deallocations reported to it such that software can query status information about current tracking slot mappings); the kickslot manager circuitry is configured to assign tracking slots to logical kickslots (p. 12, section 0176; tracking slots are assigned to logical slots based on dependencies); and the kickslot manager circuitry is configured to distribute graphics work from logical kickslots to distributed hardware kickslots in the different graphics processor sub-units (p. 4, section 0048; p. 5, sections 0070-0071; p. 6, section 0077; the kickslot arbiter, which can be read as a part of kickslot management circuitry, selects logical kickslots from which to distribute graphics work batches to GPU sub-units known as mGPUs).
As to claim 9, Fishwick discloses wherein the apparatus is a computing device that further includes: a central processing unit (p. 3, section 0043); a display (p. 16, section 0231); and network interface circuitry (p. 17, section 0240).
As to claim 10, see the rejection to claim 1. Further, Fishwick discloses a non-transitory computer-readable medium having instructions of a program stored thereon that are executable by a computing device to perform operations (p. 18, sections 0246-0247). Fishwick does not disclose, but Chheda discloses that the program is a graphics driver, as discussed in the rejection to claim 1. Motivation for the combination is similar to that given in the rejection to claim 1.
As to claim 11, see the rejection to claim 2.
As to claim 12, see the rejection to claim 3.
As to claim 14, see the rejection to claim 1.
As to claim 15, see the rejection to claim 2.
As to claim 16, see the rejection to claim 3.
As to claim 20, see the rejection to claim 8.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Fishwick in view of Chheda and further in view of Venkataraman (U.S. Publication 2018/0293424) and Gu (U.S. Publication 2021/0157593).
As to claim 4, Fishwick does not disclose, but Venkataraman discloses wherein the one or more operations controlled by the firmware processor include at least a context switch operation and a partial render operation (p. 2-3, section 0039; p. 3, section 0043; p. 12, section 0134; the firmware logic/processor controls a scheduler which controls context switches and rendering, including partial rendering). The motivation for this is to enable complex scheduling and work distribution and enhance power performance (p. 13, section 0138; p. 2-3, section 0039). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Fishwick and Chheda to have the one or more operations controlled by the firmware processor include at least a context switch operation and a partial render operation in order to enable complex scheduling and work distribution and enhance power performance as taught by Venkataraman.
Fishwick does not disclose, but Gu discloses wherein the one or more operations controlled by the firmware processor include at least a page fault handling operation (p. 11, sections 0090-0091; in a GPU, a firmware routine/processor handles page faults). The motivation for this is to, along with dedicated hardware, fetch to resolve the fault and avoid further faults (p. 9, sections 0077-0078; p. 11, sections 0090-0091). It would have been obvious to one skilled in the art before the effective filing date to modify Fishwick, Chheda, and Venkataraman to have the one or more operations controlled by the firmware processor include at least a page fault handling operation in order to fetch to resolve the fault and avoid further faults as taught by Gu.
Claims 5, 13, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Fishwick in view of Chheda and further in view of Fishwick ‘666 (U.S. Publication 2024/0273666).
As to claim 5, Fishwick does not disclose, but Fishwick ‘666 discloses wherein the control circuitry is configured to: store completion data for one or more executed sets of graphics work in a completion queue in the memory; and provide a completion signal directly to the processor in response to storing the completion data, wherein the processor is configured to retrieve the completion data from the completion queue in response to the completion signal (p. 29, section 0402; completion data is stored to a queue, and registers are written as a direct signal to the processor, which can then execute firmware to retrieve the completion data). The motivation for this is to allow software to delay processing of completed kicks rather than immediately processing each kick as it completes (p. 22, section 0313). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Fishwick and Chheda to store completion data for one or more executed sets of graphics work in a completion queue in the memory and provide a completion signal directly to the processor in response to storing the completion data, wherein the processor is configured to retrieve the completion data from the completion queue in response to the completion signal in order to allow software to delay processing of completed kicks rather than immediately processing each kick as it completes as taught by Fishwick ‘666.
As to claim 13, see the rejection to claim 5.
As to claim 17, see the rejection to claim 5.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Fishwick in view of Chheda and further in view of de Cesare (U.S. Publication 2008/0168285) and Yang (U.S. Publication 2010/0295852).
As to claim 6, Fishwick does not disclose, but de Cesare disclose an apparatus further comprising: a power control processor (fig. 2, element 54; fig. 4, element 167); wherein: in response to the signal in a paused scheduling state, the control circuitry is configured to send an interrupt to the power control processor; in response to the interrupt, the power control processor is configured to power on circuitry of the graphics processor (p. 6, section 0043; p. 7, section 0046; p. 8, section 0049; p. 9, section 0052; when tasks are not currently being scheduled, which corresponds to a paused state, control circuitry can send an interrupt to power on the graphics circuitry so that future scheduled tasks can be executed); and in response to the circuitry powering on, the power control processor is configured to signal to the control circuitry to un-pause scheduling (p. 9, section 0052; the graphics subsystem resumes/un-pauses scheduling of processing tasks/instructions/operations). The motivation for this is to save power while taking into account instruction queues (p. 1, section 0005). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Fishwick and Chheda to, in response to the signal in a paused scheduling state, send an interrupt to the power control processor; in response to the interrupt, power on circuitry of the graphics processor; and in response to the circuitry powering on, un-pause scheduling in order to save power while taking into account instruction queues as taught by de Cesare.
Fishwick in view of Chheda and further in view of de Cesare does not disclose, but Yang discloses that the circuitry powering on/off is shader core circuitry (p. 1, sections 0009-0010; shader cores are powered on or off depending on whether they are necessary). The motivation for this is to save power based on demands from different applications (p. 1, section 0008). It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Fishwick, Chheda, and de Cesare to have the circuitry powering on/off be shader core circuitry in order to save power based on demands from different applications as taught by Yang.
As to claim 18, see the rejection to claim 6.
Claims 7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Fishwick in view of Chheda and further in view of Semeria (U.S. Publication 2018/0307297).
As to claim 7, Fishwick does not disclose, but Semeria discloses wherein the processor is configured to send a programmable input/output (PIO) command to the control circuitry to wake the control circuitry from a power gated state (p. 1, section 0007; p. 3, sections 0030-0031; p. 5, section 0049; a read or write PIO command is sent to wake a processor control). The motivation for this is to access the processor without a traditional boot sequence. It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to modify Fishwick and Chheda to send a programmable input/output (PIO) command to the control circuitry to wake the control circuitry from a power gated state in order to access the processor without a traditional boot sequence as taught by Semeria.
As to claim 19, see the rejection to claim 7.
Conclusion
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/AARON M RICHER/Primary Examiner, Art Unit 2617
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