DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 13, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kotra et al. (US PGPub 2023/0205693, hereafter referred to as Kotra) in view of Tomlin (US PGPub 2023/0040696) in view of Sampathkumar et al. (US PGPub 2019/0188156, hereafter referred to as Sampathkumar).
Regarding claim 1, Kotra teaches a memory device comprising: a memory bank comprising a plurality of memory cells, and a bank register corresponding to the memory bank (Fig. 1 and Paragraph [0024], shows the DRAM banks which comprise a memory array of cells that have registers associated with the banks). Kotra does not teach wherein the memory bank comprises: a main data region configured to store user data, and a metadata region configured to store metadata corresponding to the user data, and wherein the bank register comprises: a metadata register configured to cache the metadata to be stored in the metadata region, and a dirty bitmap comprising location information indicating where the metadata is to be stored in the metadata region.
Tomlin teaches the memory having a main data region configured to store user data, and a metadata region configured to store metadata corresponding to the user data (Fig. 1, Abstract, and Paragraph [0045], shows the memory that contains both a data region (user data region) and a metadata region used to store metadata pages), and wherein a cache comprises is configured to cache the metadata to be stored in the metadata region, and a map comprising location information indicating where the metadata is to be stored in the metadata region (Fig. 1 and Paragraph [0046], shows the cache in the DRAM that is used to store metadata pages and a metadata page map that is used to track the metadata pages). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kotra to use the metadata partitions and mappings that as taught in Tomlin so to minimize time needed to flush data in response to a power failure event and for minimizing scanning and time needed to ready a storage device upon power restore. Kotra and Tomlin do not teach a dirty bitmap comprising location information indicating where the metadata is to be stored in the metadata region.
Sampathkumar teaches a dirty bitmap (Paragraph [0016], states that bitmaps can be used to determine the validity of data being stored). Since both Kotra/Tomlin and Sampathkumar teach mapping structures it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the map tables of Kotra and Tomlin with the bitmap of Sampathkumar to obtain the predictable result of a dirty bitmap comprising location information indicating where the metadata is to be stored in the metadata region (as all this does is specify the type of mapping structure being used).
Regarding claim 13, claim 13 is the system claim associated with claim 1. Since Kotra, Tomlin, and Sampathkumar teach all the limitations to claim 1 and Tomlin further teaches a memory device configured to store user data and metadata corresponding to the user data; and a memory controller configured to control the memory device (Fig. 1 and Paragraphs [0045]-[0046], show the memory device and associated controller), they also teach all the limitations to claim 13; therefore the rejection to claim 1 also applies to claim 13.
Regarding claim 21, claim 21 is the method claim associated with claims 1 and 13. Since Kotra, Tomlin, and Sampathkumar teach all the limitations to claims 1 and 13, they also teach all the limitations to claim 21; therefore the rejections to claims 1 and 13 also apply to claim 21.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ong (US PGPub 2011/0251819) in view of Tomlin.
Regarding claim 20, Ong teaches a method of operating a memory system comprising a memory device and a memory controller controlling the memory device, the method comprising: enabling the memory controller to transmit an active command to the memory device to activate a selected row of a selected memory bank (Paragraph [0095], states that Active commands can be used meaning they would have to be enabled. IT SHOULD BE NOTED THAT THE ENTIRETY OF THIS CLAIM DEALS WITH ENABLING A CONTROLLER TO TRANSMIT COMMANDS AND THAT IS IT. NO ACTUAL ACTIONS ARE TAKEN, SO AS LONG AS A CONTROLLER IS ENABLED TO TRANSMIT COMMANDS REFERNCES CAN EASILY APPLY TO THE CURRENT CLAIM), enabling the memory controller to transmit a write command to store user data in the selected memory bank (Paragraph [0136], states that read and write commands can be sent meaning they would need to be enabled), enabling the memory controller to selectively transmit a store-dirty command or a store command to the memory device (Paragraph [0082], states store and load commands can be used. However there is nothing specifying the data that is stored/loaded using them), and enabling the memory controller to transmit a precharge command to the memory device (Paragraph [0182], shows that precharge commands can be used. It should also be noted that the precharge and active commands are standard parts of DRAM procedure when operating the memory). Ong does not explicitly teach enabling the memory controller to selectively transmit a store-dirty command or a store command to the memory device, the store-dirty command being transmitted based on dirty metadata being stored in a metadata register in which metadata with respect to the user data is stored, and the store command being transmitted based on the memory controller having previously transmitted a load command to the memory device.
Tomlin teaches enabling the memory controller to selectively transmit a store-dirty command or a store command to the memory device, the store-dirty command being transmitted based on dirty metadata being stored in a metadata cache in which metadata with respect to the user data is stored, and the store command being transmitted based on the memory controller having previously transmitted a load command to the memory device (Fig. 2 and Paragraphs [0052]-[0058], describes the process of updating metadata which involves performing a write (store) command of the updated (dirty) metadata). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Kotra to use the metadata partitions and mappings that as taught in Tomlin so to minimize time needed to flush data in response to a power failure event and for minimizing scanning and time needed to ready a storage device upon power restore.
Allowable Subject Matter
Claims 2-12 and 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS A PAPERNO whose telephone number is (571)272-8337. The examiner can normally be reached Mon-Fri 9:30-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NICHOLAS A. PAPERNO/Examiner, Art Unit 2132