Prosecution Insights
Last updated: April 19, 2026
Application No. 18/962,589

PIXEL CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME

Non-Final OA §102§103
Filed
Nov 27, 2024
Examiner
BOGALE, AMEN W
Art Unit
2628
Tech Center
2600 — Communications
Assignee
LG Display Co., Ltd.
OA Round
3 (Non-Final)
74%
Grant Probability
Favorable
3-4
OA Rounds
2y 5m
To Grant
78%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allow Rate
338 granted / 455 resolved
+12.3% vs TC avg
Minimal +4% lift
Without
With
+4.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
29 currently pending
Career history
484
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
56.5%
+16.5% vs TC avg
§102
34.1%
-5.9% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 455 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/09/2026 has been entered. Response to Amendment 1. Amendments filed on 03/09/2026 have been entered. Claims 1, 2, 5, 9, 10 and 12 have been amended and claims 4 and 11 have been canceled. Response to Arguments 2. Applicant’s arguments with respect to claim(s) 1-2, 5-10 and 12-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 3. Claim(s) 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son et al (US 2017/0345371). As to claim 9, Son teaches a display device comprising: a pixel array (a plurality of pixel circuits, [0103], fig. 1) in which a plurality of data lines (a plurality of data lines arranged in the display part, [0134], fig. 1), a plurality of gate lines (a plurality of second scan lines, [0055], fig. 1), and a plurality of pixel circuits are disposed (a plurality of pixel circuits, [0103], fig. 1); a data driver configured to output a data voltage to the plurality of data lines ([0133], fig. 1); and a gate driver configured to output a gate signal to the plurality of gate lines ([0054]-[0055], fig. 1), wherein each of the plurality of pixel circuits includes: a first light emitting element (OLED1, fig. 2); a second light emitting element (OLED2, fig. 2); a driving element (a first transistor T1, fig. 2) configured to drive the first and second light emitting elements ([0089]); a compensation circuit (a circuit including a capacitor, every transistors of figure 2 and the connections between except T6-1 and T6-2) connected to the driving element (a first transistor T1, fig. 2); a first switch element (T6-1, fig. 2) connected between the driving element and the first light emitting element and driven by a first mode selection signal (EL1n, fig. 2); a second switch element (T6-2, fig. 2) connected between the driving element and the second light emitting element and driven by a second mode selection signal (EL2n, fig. 2); and a third switch element (T7-1, fig. 2) configured to apply a predetermined compensation voltage (Vint, fig. 2) to at least one of anode electrodes of the first light emitting element and the second light emitting element (OLED1, fig. 2), wherein the pixel circuit is configured to be driven in a pre-charging period (a second period b, fig. 3) where the predetermined compensation voltage (Vint, fig. 2) is applied to the at least one of the anode electrodes (anode of OLED1, fig. 2), and a charge share period after the pre-charging period (a third period c, fig. 3), and during the charge share period, the anode electrode of the first light emitting element and the anode electrode of the second light emitting element are connected to each other to share the predetermined compensation voltage (as illustrated in figs. 2 and 3, during the third period c following the second period b, both EM1n and EM2n become low to turn on T6-1 and T6-2 so that the anode of OLED1 can be connected to the anode of OLED2 through node N3). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 4. Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al (US 2017/0345371) in view of Cho et al (US 20230335056). As to claim 1, Son teaches a pixel circuit comprising: a first light emitting element (OLED1, fig. 2); a second light emitting element (OLED2, fig. 2); a driving element (a first transistor T1, fig. 2) configured to drive the first and second light emitting elements ([0089]); a compensation circuit (a circuit including a capacitor, every transistors of figure 2 and the connections between except T6-1 and T6-2) connected to the driving element (a first transistor T1, fig. 2); a first switch element (T6-1, fig. 2) connected between the driving element and the first light emitting element and driven by a first mode selection signal (EL1n, fig. 2); a second switch element (T6-2, fig. 2) connected between the driving element and the second light emitting element and driven by a second mode selection signal (EL2n, fig. 2); and a third switch element (T7-1, fig. 2) configured to apply a predetermined compensation voltage (Vint, fig. 2) to at least one of anode electrodes of the first light emitting element and the second light emitting element (OLED1, fig. 2), wherein the pixel circuit is configured to be driven in a pre-charging period (a second period b, fig. 3) where the predetermined compensation voltage (Vint, fig. 2) is applied to the at least one of the anode electrodes (anode of OLED1, fig. 2), and a charge share period after the pre-charging period ( a third period c, fig. 3), and during the charge share period, the anode electrode of the first light emitting element and the anode electrode of the second light emitting element are connected to each other to share the predetermined compensation voltage (as illustrated in figs. 2 and 3, during the third period c following the second period b, both EM1n and EM2n become low to turn on T6-1 and T6-2 so that the anode of OLED1 can be connected to the anode of OLED2 through node N3). Son does not teach wherein the predetermined compensation voltage is set to be greater than a reference voltage and is set to be less than a voltage across both ends of each of the first light emitting element and the second light emitting element. However, Cho teaches wherein the predetermined compensation voltage is set to be greater than a reference voltage and is set to be less than a voltage across both ends of each of the first light emitting element and the second light emitting element ([0097] a voltage level of the pre-charging voltage Vpre may be higher than the voltage level of the second initialization voltage Vint2. The voltage level of the pre-charging voltage Vpre may be determined (e.g., may be set) in consideration of the threshold voltage of the light emitting element LD. For example, when a difference between the pre-charging voltage Vpre and the second power voltage VSS exceeds the threshold voltage of the light emitting element LD, because the light emitting element LD may emit light in the non-emission period, a maximum value that may be determined (e.g., that may be set) as the voltage level of the pre-charging voltage Vpre may be less than a value obtained by adding the threshold voltage of the light emitting element LD with the second power voltage VSS. For example, the pre-charging voltage Vpre may have a voltage level that is about 1V to 2V higher than the voltage level of the second initialization voltage Vint2). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Son to include, wherein the predetermined compensation voltage is set to be greater than a reference voltage and is set to be less than a voltage across ends of the light emitting element, as suggested by Cho. The motivation would have been in order to improve a luminance non-uniformity phenomenon due to a deterioration of the light emitting element ([0004]). 3. (Canceled) 4. (Canceled) 11. (Canceled) 5. Claim(s) 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Son et al (US 2017/0345371) in view of Shin et al (US 2022/0399529). As to claim 12, Son does not teach the display device as claimed. However, Shin teaches the display device, wherein the compensation circuit includes: a capacitor (cst, fig. 12) connected between a first node (p1, fig. 12) and a second node (p2, fig. 12) to which a gate electrode of the driving element is connected (Tdr, fig. 12); a fourth switch element (T1, fig. 12) including a first electrode connected to a data line (Data, fig. 12), a second electrode connected to the first node (p1, fig. 12), and a gate electrode to which a first gate signal is applied (SCAN1, fig. 12); a fifth switch element (T2, fig. 12) including a first electrode connected to the second node (p2, fig. 12), a second electrode connected to a third node to which a source electrode of the driving element is connected (p3, fig. 12), and a gate electrode to which a second gate signal is applied (SCAN2, fig. 12); a sixth switch element (T3, fig. 12) including a first electrode connected to the first node, a second electrode connected to a reference voltage line (Vref, fig. 12), and a gate electrode to which a fourth gate signal is applied (EM1, fig. 12); a seventh switch element (T6, fig. 12) including a first electrode connected to the third node (p3, fig. 12), a second electrode connected to a fourth node (p9, fig. 12), and a gate electrode to which the fourth gate signal is applied (EM2, fig. 12); an eighth switch element (T5, fig. 12) including a first electrode connected to the reference voltage line (Vref, fig. 12), a second electrode connected to a fifth node to which the anode electrode of the first light emitting element is connected (p8, fig. 12), a gate electrode to which the second gate signal is applied (SCAN2, fig. 12); and a ninth switch element (T7, fig. 12) including a first electrode connected to the reference voltage line, a second electrode connected to a sixth node connected to which the anode electrode of the second light emitting element is connected (P9, fig. 12), and a gate electrode to which the second gate signal is applied (SCAN2, fig. 12). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Son to include, the compensation circuit, as suggested by Shin. The motivation would have been in order to overcome a decrease in luminance ([0012]). As to claim 14, Son does not teach the display device as claimed. However, Shin the display device, further comprising a timing controller, wherein the first and second mode selection signals are received from the timing controller ([0267] the timing controller 40 may apply the first light-emission control signal to the first light-emission control signal application line EM2 to turn on the first light-emission control thin-film transistor T4 and may not apply the second light-emission control signal to the second light-emission control signal application line EM3 ). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Son to include, a timing controller, as suggested by Shin. The motivation would have been in order to overcome a decrease in luminance ([0012]). Allowable Subject Matter 6. Claims 2, 5-8, 10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AMEN W BOGALE/Examiner, Art Unit 2628 /NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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Prosecution Timeline

Nov 27, 2024
Application Filed
Aug 08, 2025
Non-Final Rejection — §102, §103
Nov 13, 2025
Response Filed
Jan 07, 2026
Final Rejection — §102, §103
Mar 09, 2026
Request for Continued Examination
Mar 11, 2026
Response after Non-Final Action
Apr 01, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
74%
Grant Probability
78%
With Interview (+4.0%)
2y 5m
Median Time to Grant
High
PTA Risk
Based on 455 resolved cases by this examiner. Grant probability derived from career allow rate.

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