DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP § 2123.
Claim Status
Claims 1-20 are currently pending. Claims 11 and 14 are canceled as per Applicant’s amendment filed on 30 June 2026.
Response to Arguments
Examiner withdraws the 112 rejection in favor of the canceled claims.
Applicant's arguments filed 30 June 2026 have been fully considered but they are not persuasive.
With regards to Applicant’s arguments on pages 1-3, in essence, “The prior art references, over Lin (20110078393) and Shin (20180196602), fail to disclose scheduling certain tasks and commands for processing at an idle time, as claimed by Applicant.”. This has not been found persuasive. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “scheduling certain tasks and commands for processing at an idle time”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The broadest reasonable interpretation of claims as currently presented are that commands are queued at an idle time. Examiner suggests Applicant amend the claims to further distinguish the claims along what has been argued and what is supported by the specification.
A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. see MPEP § 804
The remaining rejections are maintained.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-10, 12-13, and 15-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of U.S. Patent No. 12159062, claim 11 of U.S. Patent No. 11669277, claims 9 and 15 of U.S. Patent No. 11106393, or claims 9 and 15 of U.S. Patent No. 10489085 in view of Lin (US 20110078393 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because they recite substantially similar subject matter and the claims of the issued Patent/Copending make obvious the claims of the current application as shown in the example claims in the table below.
U.S. Patent No. 12159062, U.S. Patent No. 11669277, U.S. Patent No. 11106393, or U.S. Patent No. 10489085 do not explicitly disclose “determine that content stored at a logical address is scheduled to be modified by at least a first command of the plurality of commands and a second command of the plurality of commands”.
Lin teaches determine that content stored at a logical address is scheduled to be modified by at least a first command of the plurality of commands and a second command of the plurality of commands ([Lin abstract, 0006, 0008, 0021, claims 1-2] storing a plurality of commands received from a host in a command queue; calculating a plurality of logical address ranges of the commands; selecting a plurality of write commands from the commands stored in the command queue, wherein the logical address ranges of the write commands are overlapping with each other).
Instant Application
U.S. Patent No. 12159062
U.S. Patent No. 11669277
1. An apparatus, comprising: a storage medium; and a logic circuit configured to: place a plurality of commands into a queue scheduled for execution while at least a portion of the apparatus is in an idle state; determine that content stored at a logical address is scheduled to be modified by at least a first command of the plurality of commands and a second command of the plurality of commands; and combine the first command and the second command.
11. A method, comprising:
receiving, in an apparatus having a storage medium and via an interface from a host system, a command;
determining whether the command has a latency requirement; and
placing, in response to a determination that the command has no latency requirement, the command into a queue scheduled for execution when the apparatus reaches an idle state.
12. The method of claim 11, wherein the command is configured to instruct the apparatus to store data into the storage medium;
wherein the determination is based on an indication specified in the command; and
wherein the method further comprises:
extracting the indication from the command.
13. The method of claim 12, wherein the indication is further configured to identify a priority level of the command.
14. The method of claim 13, wherein the idle state is reached upon completion of execution of commands that are received via the interface but are not placed in the queue.
17. The method of claim 14, further comprising:
optimizing write amplification via combining write operations during execution of commands in the queue.
1. An apparatus, comprising:
a communication interface;
a storage medium; and
a processing device configured via instructions to:
receive, via the communication interface, a command to store data into the storage medium;
extract, from the command, an indication of a priority level specified for the command;
select, based at least in part on the priority level, the command; schedule, in response to the command being selected, the command in a queue; and
postpone execution of commands in the queue until a portion of the apparatus reaches an idle state.
2. The apparatus of claim 1, wherein the communication interface is configured to be connected to a host computer.
3. The apparatus of claim 2, wherein the communication interface is configured to communicate with the host computer via a peripheral component interconnect express bus in accordance with a non-volatile memory host controller interface specification.
4. The apparatus of claim 3, wherein the communication interface is configured to access a plurality of submission queues on the host computer to retrieve commands for execution in the apparatus; and the portion of the apparatus reaches the idle state after a determination that the plurality of submission queues are empty.
5. The apparatus of claim 4, wherein the storage medium includes flash memory; and the processing device is further configured to perform operations of garbage collection after the portion of the apparatus reaches the idle state.
11. The apparatus of claim 5, wherein the processing device is configured to combine write operations requested by the commands in the queue.
A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional. As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. see MPEP § 804
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 10, 12, 13, 15, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20110078393 A1) in view of Shin (US 20180196602 A1).
Referring to claims 1, 13, and 18, taking claim 1 as exemplary, Lin teaches
An apparatus, comprising: a storage medium; ([Lin 0009, 0021, Fig. 1] the memory device is coupled to a host, and comprises a memory and a controller. The memory is for data storage. Referring to FIG. 1, a block diagram of a memory device 104 according to the invention is shown. The memory device 104 is coupled to a host 102 and stores data for the host 102.) and a logic circuit configured to: place a plurality of commands into a queue scheduled for execution ([Lin 0021, Fig. 1] The controller 112 comprises a command queue 122 and a buffer 124. When the controller 112 receives a plurality of commands from the host 102, the controller 112 stores the commands in the command queue 122.) determine that content stored at a logical address is scheduled to be modified by at least a first command of the plurality of commands and a second command of the plurality of commands; ([Lin abstract, 0006, 0008, 0021, claims 1-2] storing a plurality of commands received from a host in a command queue; calculating a plurality of logical address ranges of the commands; selecting a plurality of write commands from the commands stored in the command queue, wherein the logical address ranges of the write commands are overlapping with each other) and combine the first command and the second command ([Lin 0006-0008, 0021, Fig. 2B] A data access method is therefore required, which combines a plurality of write commands with overlapping logical address ranges; thus, improving system performance. When the at least one read command does not exist, write data corresponding to the write commands are combined together to obtain combined write data according to the logical address ranges of the write commands. A combined write command and the combined write data are then sent to the memory to request that the memory executes the write commands. When the logical address ranges of the write commands are overlapping with each other, the controller 112 combines the data of the write commands together to obtain combined write data and stores the combined write data in the buffer 124. The controller 112 then sends a single write command and the combined write data to the memory 114 to request that the memory 114 writes the combined write data thereto. The memory 114 is therefore merely written to with the combined write data of the combined write command instead of repeatedly being written to with data of the write commands.).
Lin does not explicitly disclose while at least a portion of the apparatus is in an idle state.
Shin teaches while at least a portion of the apparatus is in an idle state; ([Shin 0034-0035, 0048, Fig. 4] Summarizing these, command processing of the data storage device 200 may start in response to an update of the submission queue pointer SQPT, and end in response to an update of the completion queue pointer CQPT. The controller 210 may determine whether or not it is in an idle state, based on the submission queue pointer SQPT and the completion queue pointer CQPT.).
Lin and Shin are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Lin and Shin before him or her to modify the memory device of Lin to include the idle state command processing of Shin, thereafter the memory device is connected to the idle state command processing. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory device to have better management or processing during idle states as suggested by Shin. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Lin with Shin to obtain the invention as specified in the instant application claims.
With regards to the non-exemplary limitations of claim 18, Lin teaches ([]) and adjust a mapping of logical to physical addresses of the storage medium to a total number of writes for executing the plurality of write commands ([Lin abstract, 0008, 0024-0025] First, a plurality of commands received from a host is stored in a command queue. A plurality of logical address ranges of the commands is then calculated. A plurality of write commands is then selected from the commands, wherein the logical address ranges of the write commands are overlapping with each other. After the controller obtains the logical address ranges of the commands stored in the command queue 122, the controller 112 determines whether the logical address ranges of a plurality of write commands selected from the commands stored in the command queue 122 overlap with each other (step 206). For example, assume that the command queue 122 stores a first write command and a second write command. the controller 112 determines whether a logical address range of the read command is overlapping with an overlapping segment of the logical address ranges of the write commands (step 210).).
As per the non-exemplary claim(s), this/these claim(s) has/have similar limitations and is/are rejected based on the reasons given above.
Referring to claims 2 and 19, taking claim 2 as exemplary, Lin in view of Shin teaches
The apparatus of claim 1, wherein the plurality of commands are received from a host system via an interface operable for a connection to the host system ([Lin 0021, Fig. 1] Referring to FIG. 1, a block diagram of a memory device 104 according to the invention is shown. The memory device 104 is coupled to a host 102 and stores data for the host 102. The host 102 supports a native command queuing (NCQ) function. When the controller 112 receives a plurality of commands from the host 102, the controller 112 stores the commands in the command queue 122.).
Referring to claim 3, Lin in view of Shin teaches
The apparatus of claim 2, wherein the interface is configured to communicate with the host system via a peripheral component interconnect express bus ([Shin 0028, 0068] While the host device 100 and the data storage device 200 may interface with each other, based on, for example, a nonvolatile memory (NVM) express (Examiner notes NVMe is a high-speed storage protocol that runs over the PCI Express (PCIe) interface), it is to be noted that an interfacing method is not limited thereto.).
Lin and Shin are analogous art because they are from the same field of endeavor in storage systems. Before the effective filing date of the invention, it would have been obvious to a person of ordinary skill in the art, having the teaching of Lin and Shin before him or her to modify the memory device of Lin to include the nonvolatile memory (NVME) express of Shin, thereafter the memory device is connected to the nonvolatile memory (NVME) express. The suggestion and/or motivation for doing so would be obtaining the advantage of allowing the memory device to have more support for broadly supported interface standards through NVME/PCIE as suggested by Shin. It is known to combine prior art elements according to known methods to yield predictable results. Therefore, it would have been obvious to combine Lin with Shin to obtain the invention as specified in the instant application claims.
Referring to claim 4, Lin in view of Shin teaches
The apparatus of claim 3, wherein the peripheral component interconnect express bus is configured in accordance with a non-volatile memory host controller interface specification ([Shin 0028, 0068] While the host device 100 and the data storage device 200 may interface with each other, based on, for example, a nonvolatile memory (NVM) express (Examiner notes NVMe is a high-speed storage protocol that runs over the PCI Express (PCIe) interface), it is to be noted that an interfacing method is not limited thereto.).
The same motivation that was utilized for combining Lin and Shin as set forth in claim(s) 3 is equally applicable to this/these claim(s).
Referring to claim 10, Lin in view of Shin teaches
The apparatus of claim 1, wherein the storage medium includes flash memory ([Lin 0003] The invention relates to memories, and more particularly to flash memories).
Referring to claims 12 and 15, taking claim 12 as exemplary, Lin in view of Shin teaches
The apparatus of claim 1, wherein the first command being combined with the second command reduces a number of writes performed at the logical address as compared to carrying out both of the first command and the second command ([Lin 0006-0008, 0021, 0029, Fig. 2B] Thus, reducing system resources consumed for executing the write commands and improving the performance of the memory device 104. A data access method is therefore required, which combines a plurality of write commands with overlapping logical address ranges; thus, improving system performance. When the at least one read command does not exist, write data corresponding to the write commands are combined together to obtain combined write data according to the logical address ranges of the write commands. A combined write command and the combined write data are then sent to the memory to request that the memory executes the write commands. When the logical address ranges of the write commands are overlapping with each other, the controller 112 combines the data of the write commands together to obtain combined write data and stores the combined write data in the buffer 124. The controller 112 then sends a single write command and the combined write data to the memory 114 to request that the memory 114 writes the combined write data thereto. The memory 114 is therefore merely written to with the combined write data of the combined write command instead of repeatedly being written to with data of the write commands.).
Allowable Subject Matter
Claims 5-9, 16-17, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and double patenting rejection addressed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRANCISCO A GRULLON whose telephone number is (571)272-8318. The examiner can normally be reached Monday - Friday, 9-5.
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/FRANCISCO A GRULLON/Primary Examiner, Art Unit 2132
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