DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Claim 1 has been cancelled. Claims 2-21 remain pending and are ready for examination.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on February 10th, 2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-6, 8-9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata et al. (US Publication No. 2017/0337969 – “Shikata”) in view of Tanpairoj et al. (US Publication No. 2019/0369899 – “Tanpairoj”).
Regarding claim 2, Shikata teaches An apparatus comprising: one or more first memory devices; and control circuitry coupled with the one or more first memory devices and configured to cause the apparatus to: (Shikata paragraphs [0038-0040], The semiconductor memory device 10 is a NAND flash memory that stores data in a nonvolatile manner. The details of the configuration of the semiconductor memory device 10 will be described below. The controller 20 commands the semiconductor memory device 10 to execute reading, writing, erasing, or the like in response to a command from an external host apparatus (not illustrated). The controller 20 manages a memory space of the semiconductor memory device 10. As illustrated in FIG. 1, the controller 20 includes a processor (CPU) 21, an internal memory (RAM) 22, an ECC circuit 23, a NAND interface circuit 24, a buffer memory 25, and a host interface circuit 26. A control circuit may be coupled with a memory device to perform various memory operations/commands) whether to use a first write format or a second write format to write the data to the one or more first memory devices, (Shikata paragraph [0196], The semiconductor memory device 10 can execute a write operation of a triple level cell (TLC) scheme of storing 3-bit data in one memory cell or a write operation of a quadruple level cell (QLC) scheme of storing 4-bit data in one memory cell. The memory system can choose to utilize a tri-level write format or a quad-level write format depending on various factors related to the data write operation, also see Shikata paragraph [0199], In this way, when the memory cell retains the data of a plurality of bits, the number of peaks of the threshold voltage distribution increases as the number of bits to be stored increases. When a write operation and a read operation are executed on the memory cells storing the 3-bit data and the 4-bit data, a verifying voltage and a reading voltage are set as in the case of 2 bits described in FIG. 4) the second write format associated with a greater quantity of bits per memory cell than the first write format; (Shikata paragraph [0196], The semiconductor memory device 10 can execute a write operation of a triple level cell (TLC) scheme of storing 3-bit data in one memory cell or a write operation of a quadruple level cell (QLC) scheme of storing 4-bit data in one memory cell. The memory system can choose to utilize a tri-level write format or a quad-level write format depending on various factors related to the data write operation, also see Shikata paragraph [0199], In this way, when the memory cell retains the data of a plurality of bits, the number of peaks of the threshold voltage distribution increases as the number of bits to be stored increases. When a write operation and a read operation are executed on the memory cells storing the 3-bit data and the 4-bit data, a verifying voltage and a reading voltage are set as in the case of 2 bits described in FIG. 4) perform a write operation to write the data to the one or more first memory devices using the first write format based at least in part on selecting the first write format; (Shikata paragraph [0196], The semiconductor memory device 10 can execute a write operation of a triple level cell (TLC) scheme of storing 3-bit data in one memory cell. The first write format (i.e., TLC) may be executed and performed in a write operation).
Shikata does not teach select, based at least in part on a command to write data from one or more second memory devices to the one or more first memory devices, determine, after writing the data to the one or more first memory devices using the first write format, a time period during which to convert the data from the first write format to the second write format; and convert, during the time period, the data from the first write format to the second write format.
However, Tanpairoj teaches select, based at least in part on a command to write data from one or more second memory devices to the one or more first memory devices, (Tanpairoj paragraph [0072], At operation 520 the NAND memory device may evaluate any initiation rules in the SLC cache migration profile using the retrieved NAND operational conditions to determine whether the rules in the cache migration profile are satisfied (e.g., return an indication that the migration should be initiated). If the rules are not satisfied, then processing may terminate. Processing of FIG. 5 may occur periodically, in response to a particular event (e.g., a queue depth being zero), or the like. At operation 525 if the rules are satisfied, then the system may begin migrating data in the SLC cache to MLC/TLC memory cells. The command may include a migration command involving writing data from one memory device to a different memory device) determine, after writing the data to the one or more first memory devices using the first write format, a time period during which to convert the data from the first write format to the second write format; and convert, during the time period, the data from the first write format to the second write format (Tanpairoj paragraphs [0063-0064], Operational parameters are one or more measurements of a current operational state of the NAND device. Example operational parameters include a host command queue depth, a temperature of the NAND device, a power consumption of the NAND device, a memory configuration of the NAND device, a level of data fragmentation in the SLC cache, a level of data fragmentation in the MLC cells, a current block erase count of the SLC cache, a current block erase count in the MLC cache, a current Write Amplification Factor (WAF) of the SLC cache, a current write amplification factor of the MLC cache, a power consumption of the NAND, and the like. Rules in the SLC cache migration profile may evaluate one or more of these operational parameters against a threshold to determine when to start the migration, determine which data to migrate, how fast to perform the migration, determine whether or not to terminate the migration, and the like. The time period for the data conversion from the first to second write format (in this case SLC to MLC) can be determined and the data can be converted at that time).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata with those of Tanpairoj. Tanpairoj teaches converting data from a first write format to a second write format with more bits per memory cell during a particular time interval, which can help reduce performance impact associated with the data conversion (i.e., see Tanpairoj paragraphs [0061-0062], Eventually, data written to the SLC cache may fill up the SLC cache. To continue to use the increased performance of the SLC cache for new requests, the NAND memory device can move data in SLC to MLC/TLC. The choice of how and when to move the data can have serious performance impacts. For example, if the NAND is busy, the extra processing needed to move the data can slow down performance of host commands requested by a host over a host interface. In addition, NAND devices that are part of a battery powered computing device (e.g., a mobile phone, etc.) have strict power targets. If the migration is not properly managed, the extra processing required may consume too much power and put the NAND device over its prescribed power limit. Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules in an SLC cache migration profile that are evaluated using current operational parameters of the NAND device. In some examples, the SLC cache migration process may utilize NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data).
Regarding claim 3, Shikata in view of Tanpairoj teaches The apparatus of claim 2, wherein, to convert the data from the first write format to the second write format, the control circuitry is configured to cause the apparatus to: read the data from the one or more first memory devices in accordance with the first write format; and rewrite the data to the one or more first memory devices in accordance with the second write format (Tanpairoj paragraphs [0094-0095], Operating a memory cell, as used herein, includes reading from, writing to, or erasing the memory cell. The operation of placing a memory cell in an intended state is referred to herein as “programming,” and can include both writing to or erasing from the memory cell (e.g., the memory cell may be programmed to an erased state). According to one or more embodiments of the present disclosure, a memory controller (e.g., a processor, controller, firmware, etc.) located internal or external to a memory device, is capable of determining (e.g., selecting, setting, adjusting, computing, changing, clearing, communicating, adapting, deriving, defining, utilizing, modifying, applying, etc.) a quantity of wear cycles, or a wear state (e.g., recording wear cycles, counting operations of the memory device as they occur, tracking the operations of the memory device it initiates, evaluating the memory device characteristics corresponding to a wear state, etc.). The memory cells being converted may include reading and re-writing operations to move from SLC to MLC, such as migrating as seen in Tanpairoj paragraph [0112], In Example 13, the subject matter of any one or more of Examples 9-12 optionally include wherein the operations further comprise: determining, based upon the SLC migration profile, a rate for the migration operations, and wherein migrating the at least the portion of data stored in the SLC cache to MLC memory cells of the NAND comprises migrating the the at least the portion of data stored in the SLC cache to MLC memory cells of the NAND at the rate).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata with those of Tanpairoj. Tanpairoj teaches converting data from a first write format to a second write format with more bits per memory cell during a particular time interval, which can help reduce performance impact associated with the data conversion (i.e., see Tanpairoj paragraphs [0061-0062], Eventually, data written to the SLC cache may fill up the SLC cache. To continue to use the increased performance of the SLC cache for new requests, the NAND memory device can move data in SLC to MLC/TLC. The choice of how and when to move the data can have serious performance impacts. For example, if the NAND is busy, the extra processing needed to move the data can slow down performance of host commands requested by a host over a host interface. In addition, NAND devices that are part of a battery powered computing device (e.g., a mobile phone, etc.) have strict power targets. If the migration is not properly managed, the extra processing required may consume too much power and put the NAND device over its prescribed power limit. Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules in an SLC cache migration profile that are evaluated using current operational parameters of the NAND device. In some examples, the SLC cache migration process may utilize NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data).
Regarding claim 4, Shikata in view of Tanpairoj teaches The apparatus of claim 2, wherein the time period is associated with an idle mode of the one or more first memory devices, one or more background operations of the one or more first memory devices, or any combination thereof (Tanpairoj paragraph [0124], Example 25 is a device of operating a NAND device, the device comprising: at a NAND controller: means for retrieving an SLC cache migration profile, the SLC cache migration profile including a first and second initiation rule for initiating a migration of data stored in an SLC cache to MLC memory cells, the first and second rules comprising one of: an idle rule, a data fragmentation rule, a current block erase count, a current Write Amplification Factor (WAF), or a power consumption level rule, wherein the first rule is different than the second rule; means for retrieving a first NAND operational condition specified by the first rule, and determining that the first NAND operational condition satisfies the first rule; means for retrieving a second NAND operational condition specified by the second rule, and determining that the second NAND operational condition satisfies the second rule; means for responsive to the first and second rule being satisfied, migrating at least a portion of data stored in the SLC cache to MLC memory cells of the NAND device. One rule for migrating data from SLC to MLC can include an idle period detection).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata with those of Tanpairoj. Tanpairoj teaches converting data from a first write format to a second write format with more bits per memory cell during a particular time interval, which can help reduce performance impact associated with the data conversion (i.e., see Tanpairoj paragraphs [0061-0062], Eventually, data written to the SLC cache may fill up the SLC cache. To continue to use the increased performance of the SLC cache for new requests, the NAND memory device can move data in SLC to MLC/TLC. The choice of how and when to move the data can have serious performance impacts. For example, if the NAND is busy, the extra processing needed to move the data can slow down performance of host commands requested by a host over a host interface. In addition, NAND devices that are part of a battery powered computing device (e.g., a mobile phone, etc.) have strict power targets. If the migration is not properly managed, the extra processing required may consume too much power and put the NAND device over its prescribed power limit. Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules in an SLC cache migration profile that are evaluated using current operational parameters of the NAND device. In some examples, the SLC cache migration process may utilize NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data).
Regarding claim 5, Shikata in view of Tanpairoj teaches The apparatus of claim 2, wherein the control circuitry is further configured to cause the apparatus to: determine, based at least in part on writing the data to the one or more first memory devices, whether the write operation was successful, wherein determining the time period is based at least in part on determining that the write operation was successful (Tanpairoj paragraph [0071], As previously described, the migration profile may contain one or more initiation rules that specify operational conditions under which the migration process is run. At operation 515, the NAND memory device may retrieve and/or determine one or more NAND operational characteristics used to evaluate the initiation rules in the SLC cache profile retrieved at operation 510. Examples include a current level of fragmentation, current block erase counts, current WAF, power consumption and the like. In some examples, the operational conditions include a command queue depth for a command queue or other indicators of whether or not the NAND memory device is idle. In some examples, the SLC cache migration profile has at least two initiation rules using at least two different operational characteristics. For example, an operational characteristic indicating the NAND is idle (e.g., a queue depth of a host queue), and a second operational characteristic (e.g., current level of fragmentation). In other examples, the SLC cache migration profile has more than two rules. The time period for determining data conversion/migration may be based on the success of the SLC writes and factors related to success rate of said writes).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata with those of Tanpairoj. Tanpairoj teaches converting data from a first write format to a second write format with more bits per memory cell during a particular time interval, which can help reduce performance impact associated with the data conversion (i.e., see Tanpairoj paragraphs [0061-0062], Eventually, data written to the SLC cache may fill up the SLC cache. To continue to use the increased performance of the SLC cache for new requests, the NAND memory device can move data in SLC to MLC/TLC. The choice of how and when to move the data can have serious performance impacts. For example, if the NAND is busy, the extra processing needed to move the data can slow down performance of host commands requested by a host over a host interface. In addition, NAND devices that are part of a battery powered computing device (e.g., a mobile phone, etc.) have strict power targets. If the migration is not properly managed, the extra processing required may consume too much power and put the NAND device over its prescribed power limit. Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules in an SLC cache migration profile that are evaluated using current operational parameters of the NAND device. In some examples, the SLC cache migration process may utilize NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data).
Regarding claim 6, Shikata in view of Tanpairoj teaches The apparatus of claim 2, wherein the control circuitry is configured to cause the apparatus to: select the first write format based at least in part on whether a production operation for the one or more first memory devices is complete, whether a threshold amount of space is available within the one or more first memory devices, whether the data is sequential, or any combination thereof (Tanpairoj paragraph [0066], Example conditions for initiating the migration process may include an amount of free space in the SLC cache, a level of data fragmentation in the SLC cache that is above a threshold, an amount of space in the MLC cache, a level of fragmentation in an MLC cache below a particular threshold. For example, a low amount of free space, or a high level of SLC cache fragmentation may indicate that the NAND may begin to have trouble fulfilling new host write requests if the size of the request is too large to fit in the remaining contiguous SLC pages. On the other hand, even if the SLC cache space is highly fragmented or running low on space if there is not enough space in the MLC storage, or if the MLC fragmentation is too high, there may be no room for the data from the SLC cache in the MLC storage and migration may not be initiated. The first write format (i.e., SLC) may be selected based on a variety of factors including available space).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata with those of Tanpairoj. Tanpairoj teaches converting data from a first write format to a second write format with more bits per memory cell during a particular time interval, which can help reduce performance impact associated with the data conversion (i.e., see Tanpairoj paragraphs [0061-0062], Eventually, data written to the SLC cache may fill up the SLC cache. To continue to use the increased performance of the SLC cache for new requests, the NAND memory device can move data in SLC to MLC/TLC. The choice of how and when to move the data can have serious performance impacts. For example, if the NAND is busy, the extra processing needed to move the data can slow down performance of host commands requested by a host over a host interface. In addition, NAND devices that are part of a battery powered computing device (e.g., a mobile phone, etc.) have strict power targets. If the migration is not properly managed, the extra processing required may consume too much power and put the NAND device over its prescribed power limit. Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules in an SLC cache migration profile that are evaluated using current operational parameters of the NAND device. In some examples, the SLC cache migration process may utilize NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data).
Regarding claim 8, Shikata teaches An apparatus comprising: one or more first memory devices of a memory system; and control circuitry coupled with the one or more first memory devices and configured to cause the apparatus to: (Shikata paragraphs [0038-0040], The semiconductor memory device 10 is a NAND flash memory that stores data in a nonvolatile manner. The details of the configuration of the semiconductor memory device 10 will be described below. The controller 20 commands the semiconductor memory device 10 to execute reading, writing, erasing, or the like in response to a command from an external host apparatus (not illustrated). The controller 20 manages a memory space of the semiconductor memory device 10. As illustrated in FIG. 1, the controller 20 includes a processor (CPU) 21, an internal memory (RAM) 22, an ECC circuit 23, a NAND interface circuit 24, a buffer memory 25, and a host interface circuit 26. A control circuit may be coupled with a memory device to perform various memory operations/commands) using a first write format or a second write format based at least in part on receiving a command associated with a write operation for the data, (Shikata paragraph [0196], The semiconductor memory device 10 can execute a write operation of a triple level cell (TLC) scheme of storing 3-bit data in one memory cell or a write operation of a quadruple level cell (QLC) scheme of storing 4-bit data in one memory cell. The memory system can choose to utilize a tri-level write format or a quad-level write format depending on various factors related to the data write operation, also see Shikata paragraph [0199], In this way, when the memory cell retains the data of a plurality of bits, the number of peaks of the threshold voltage distribution increases as the number of bits to be stored increases. When a write operation and a read operation are executed on the memory cells storing the 3-bit data and the 4-bit data, a verifying voltage and a reading voltage are set as in the case of 2 bits described in FIG. 4) the second write format associated with a greater quantity of bits per memory cell than the first write format; (Shikata paragraph [0196], The semiconductor memory device 10 can execute a write operation of a triple level cell (TLC) scheme of storing 3-bit data in one memory cell or a write operation of a quadruple level cell (QLC) scheme of storing 4-bit data in one memory cell. The memory system can choose to utilize a tri-level write format or a quad-level write format depending on various factors related to the data write operation, also see Shikata paragraph [0199], In this way, when the memory cell retains the data of a plurality of bits, the number of peaks of the threshold voltage distribution increases as the number of bits to be stored increases. When a write operation and a read operation are executed on the memory cells storing the 3-bit data and the 4-bit data, a verifying voltage and a reading voltage are set as in the case of 2 bits described in FIG. 4) select the first write format instead of the second write format for writing the data to the one or more first memory devices based at least in part on a timing to complete writing the data to the one or more first memory devices using the second write format; (Shikata paragraphs [0236-0237], As the data stored in the memory system, there are data of which a rewriting frequency is high and data of which a rewriting frequency is low. For example, image data can be exemplified as the data of which the rewriting frequency is low, and document data can be exemplified as the data of which the rewriting frequency is high. For either data, an error at the time of reading is preferably small. An operation speed of a write operation in which reliability is enhanced is lower than an operation speed of a normal write operation in some cases. For data of which the rewriting frequency is high, an operation speed may be prioritized even if a few fail-bits are allowed. The first write format may be selected due to a higher operation speed than the higher bit writes, such as the QLC of the second format) write the data to the one or more first memory devices using the first write format based at least in part on selecting the first write format; (Shikata paragraph [0196], The semiconductor memory device 10 can execute a write operation of a triple level cell (TLC) scheme of storing 3-bit data in one memory cell. The first write format (i.e., TLC) may be executed and performed in a write operation).
Shikata does not teach determine whether to write data from one or more second memory devices to the one or more first memory devices; and convert the data from the first write format to the second write format after writing the data to the one or more first memory devices using the first write format.
However, Tanpairoj teaches determine whether to write data from one or more second memory devices to the one or more first memory devices (Tanpairoj paragraph [0072], At operation 520 the NAND memory device may evaluate any initiation rules in the SLC cache migration profile using the retrieved NAND operational conditions to determine whether the rules in the cache migration profile are satisfied (e.g., return an indication that the migration should be initiated). If the rules are not satisfied, then processing may terminate. Processing of FIG. 5 may occur periodically, in response to a particular event (e.g., a queue depth being zero), or the like. At operation 525 if the rules are satisfied, then the system may begin migrating data in the SLC cache to MLC/TLC memory cells. The command may include a migration command involving writing data from one memory device to a different memory device) and convert the data from the first write format to the second write format after writing the data to the one or more first memory devices using the first write format (Tanpairoj paragraphs [0063-0064], Operational parameters are one or more measurements of a current operational state of the NAND device. Example operational parameters include a host command queue depth, a temperature of the NAND device, a power consumption of the NAND device, a memory configuration of the NAND device, a level of data fragmentation in the SLC cache, a level of data fragmentation in the MLC cells, a current block erase count of the SLC cache, a current block erase count in the MLC cache, a current Write Amplification Factor (WAF) of the SLC cache, a current write amplification factor of the MLC cache, a power consumption of the NAND, and the like. Rules in the SLC cache migration profile may evaluate one or more of these operational parameters against a threshold to determine when to start the migration, determine which data to migrate, how fast to perform the migration, determine whether or not to terminate the migration, and the like. The time period for the data conversion from the first to second write format (in this case SLC to MLC) can be determined and the data can be converted at that time).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata with those of Tanpairoj. Tanpairoj teaches converting data from a first write format to a second write format with more bits per memory cell during a particular time interval, which can help reduce performance impact associated with the data conversion (i.e., see Tanpairoj paragraphs [0061-0062], Eventually, data written to the SLC cache may fill up the SLC cache. To continue to use the increased performance of the SLC cache for new requests, the NAND memory device can move data in SLC to MLC/TLC. The choice of how and when to move the data can have serious performance impacts. For example, if the NAND is busy, the extra processing needed to move the data can slow down performance of host commands requested by a host over a host interface. In addition, NAND devices that are part of a battery powered computing device (e.g., a mobile phone, etc.) have strict power targets. If the migration is not properly managed, the extra processing required may consume too much power and put the NAND device over its prescribed power limit. Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules in an SLC cache migration profile that are evaluated using current operational parameters of the NAND device. In some examples, the SLC cache migration process may utilize NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data).
Regarding claim 9, Shikata in view of Tanpairoj teaches The apparatus of claim 8, wherein the one or more first memory devices support writing the data using the first write format and also support writing the data using the second write format (Shikata paragraph [0196], The semiconductor memory device 10 can execute a write operation of a triple level cell (TLC) scheme of storing 3-bit data in one memory cell or a write operation of a quadruple level cell (QLC) scheme of storing 4-bit data in one memory cell. The memory system can choose to utilize a tri-level write format or a quad-level write format depending on various factors related to the data write operation, also see Shikata paragraph [0199], In this way, when the memory cell retains the data of a plurality of bits, the number of peaks of the threshold voltage distribution increases as the number of bits to be stored increases. When a write operation and a read operation are executed on the memory cells storing the 3-bit data and the 4-bit data, a verifying voltage and a reading voltage are set as in the case of 2 bits described in FIG. 4).
Regarding claim 16, Shikata in view of Tanpairoj teaches The apparatus of claim 8, wherein the control circuitry is configured to cause the apparatus to: convert the data from the first write format to the second write format during a time period that is associated with an idle mode of the one or more first memory devices, one or more background operations of the one or more first memory devices, or any combination thereof (Tanpairoj paragraph [0124], Example 25 is a device of operating a NAND device, the device comprising: at a NAND controller: means for retrieving an SLC cache migration profile, the SLC cache migration profile including a first and second initiation rule for initiating a migration of data stored in an SLC cache to MLC memory cells, the first and second rules comprising one of: an idle rule, a data fragmentation rule, a current block erase count, a current Write Amplification Factor (WAF), or a power consumption level rule, wherein the first rule is different than the second rule; means for retrieving a first NAND operational condition specified by the first rule, and determining that the first NAND operational condition satisfies the first rule; means for retrieving a second NAND operational condition specified by the second rule, and determining that the second NAND operational condition satisfies the second rule; means for responsive to the first and second rule being satisfied, migrating at least a portion of data stored in the SLC cache to MLC memory cells of the NAND device. One rule for migrating data from SLC to MLC can include an idle period detection).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata with those of Tanpairoj. Tanpairoj teaches converting data from a first write format to a second write format with more bits per memory cell during a particular time interval, which can help reduce performance impact associated with the data conversion (i.e., see Tanpairoj paragraphs [0061-0062], Eventually, data written to the SLC cache may fill up the SLC cache. To continue to use the increased performance of the SLC cache for new requests, the NAND memory device can move data in SLC to MLC/TLC. The choice of how and when to move the data can have serious performance impacts. For example, if the NAND is busy, the extra processing needed to move the data can slow down performance of host commands requested by a host over a host interface. In addition, NAND devices that are part of a battery powered computing device (e.g., a mobile phone, etc.) have strict power targets. If the migration is not properly managed, the extra processing required may consume too much power and put the NAND device over its prescribed power limit. Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules in an SLC cache migration profile that are evaluated using current operational parameters of the NAND device. In some examples, the SLC cache migration process may utilize NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata in view of Tanpairoj as applied to claim 2 above, and further in view of Doyle (US Publication No. 2018/0121128 – “Doyle”).
Regarding claim 7, Shikata in view of Tanpairoj in further view of Doyle teaches The apparatus of claim 2, wherein the control circuitry is configured to cause the apparatus to perform the write operation in accordance with a trim setting, a page map, or a combination thereof (Doyle paragraph [0017], Page maps 110 provide information regarding the current state of the memory array 106. For example, the page maps 110 may indicate whether each page in the SLC blocks 112 and/or the MLC blocks 114 have data stored in them at any given point in time. There may be one page map 110 for each block in the memory array 106. The page map for a particular block may include a list of entries including one entry for each page in the block. The list entries may indicate whether data are stored in the page. Based on whether the pages have data stored in them, the control circuit 108 may determine whether a page can be written to. The page maps may be updated after each write operation or erase operation so that the page maps always accurately reflect the state of the memory array 106. Page maps are discussed in further detail below with respect to FIGS. 2-3C. A page map can be used in the process of write operations).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj with those of Doyle. Doyle teaches using a page map for performing write operations, which can ensure that the data is up to date and accurately reflects the state of the memory device (i.e., see Doyle paragraph [0017], Page maps 110 provide information regarding the current state of the memory array 106. For example, the page maps 110 may indicate whether each page in the SLC blocks 112 and/or the MLC blocks 114 have data stored in them at any given point in time. There may be one page map 110 for each block in the memory array 106. The page map for a particular block may include a list of entries including one entry for each page in the block. The list entries may indicate whether data are stored in the page. Based on whether the pages have data stored in them, the control circuit 108 may determine whether a page can be written to. The page maps may be updated after each write operation or erase operation so that the page maps always accurately reflect the state of the memory array 106. Page maps are discussed in further detail below with respect to FIGS. 2-3C).
Claim(s) 10-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata in view of Tanpairoj as applied to claim 8 above, and further in view of Zhou (US Publication No. 2022/0100406 – “Zhou”).
Regarding claim 10, Shikata in view of Tanpairoj in further view of Zhou teaches The apparatus of claim 8, wherein the control circuitry is configured to cause the apparatus to: select the first write format instead of the second write format based at least in part on an amount of available space within the one or more first memory devices satisfying a threshold (Zhou paragraph [0007], detecting whether an amount of user data stored in the storage device meets a first amount condition, where the storage device includes a first storage area, the first storage area stores data in a first mode, and the first mode is one of an SLC mode, an MLC mode, a TLC mode, and a QLC mode; and when the amount of stored user data meets the first amount condition, converting a data storage mode of a first sub-area in the first storage area from the first mode to a second mode, where the second mode is one of the SLC mode, the MLC mode, the TLC mode, and the QLC mode, and the second mode is different from the first mode. The first write format may be selected if the available space meets a predetermined threshold value, also see Zhou paragraph [0057], In the flash memory array, only storage space in which data is stored in the SLC mode may be preset, or storage space in which data is stored in an MLC mode, a TLC mode, or a QLC mode may be preset).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj with those of Zhou. Zhou teaches comparing the available space for a write operation to a preset threshold value for determining if a data migration needs to occur. Zhou uses the data migration when the threshold is exceeded and the available memory capacity is insufficient, which allows the memory system to continue operating while still completing said memory write commands (Zhou paragraphs [0060-0061], For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. When the controller 11 detects that the amount of user data stored in the flash memory array is greater than or equal to the first preset value, the controller 11 converts the data storage mode of the at least a part of storage space in the flash memory array from the first mode to the second mode. For example, when the amount of user data stored in the flash memory array in step 501 is greater than or equal to 409.6 GB, the controller 11 may convert the data storage mode of the 50 GB storage space in which data is stored in the SLC mode in the two QLC hard disks to the MLC mode, to obtain 100 GB storage space in which data is stored in the MLC mode. In this way, the total storage space in the flash memory array is 462 GB storage space in which data is stored in the SLC mode and the 100 GB storage space in which data is stored in the MLC mode. The storage space in the flash memory array may be expanded).
Regarding claim 11, Shikata in view of Tanpairoj in further view of Zhou teaches The apparatus of claim 10, wherein the amount of available space within the one or more first memory devices satisfying the threshold comprises the amount of available space within the one or more first memory devices exceeding the threshold (Zhou paragraph [0007], detecting whether an amount of user data stored in the storage device meets a first amount condition, where the storage device includes a first storage area, the first storage area stores data in a first mode, and the first mode is one of an SLC mode, an MLC mode, a TLC mode, and a QLC mode; and when the amount of stored user data meets the first amount condition, converting a data storage mode of a first sub-area in the first storage area from the first mode to a second mode, where the second mode is one of the SLC mode, the MLC mode, the TLC mode, and the QLC mode, and the second mode is different from the first mode. The first write format may be selected if the available space meets a predetermined threshold value, also see Zhou paragraph [0057], In the flash memory array, only storage space in which data is stored in the SLC mode may be preset, or storage space in which data is stored in an MLC mode, a TLC mode, or a QLC mode may be preset).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj with those of Zhou. Zhou teaches comparing the available space for a write operation to a preset threshold value for determining if a data migration needs to occur. Zhou uses the data migration when the threshold is exceeded and the available memory capacity is insufficient, which allows the memory system to continue operating while still completing said memory write commands (Zhou paragraphs [0060-0061], For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. When the controller 11 detects that the amount of user data stored in the flash memory array is greater than or equal to the first preset value, the controller 11 converts the data storage mode of the at least a part of storage space in the flash memory array from the first mode to the second mode. For example, when the amount of user data stored in the flash memory array in step 501 is greater than or equal to 409.6 GB, the controller 11 may convert the data storage mode of the 50 GB storage space in which data is stored in the SLC mode in the two QLC hard disks to the MLC mode, to obtain 100 GB storage space in which data is stored in the MLC mode. In this way, the total storage space in the flash memory array is 462 GB storage space in which data is stored in the SLC mode and the 100 GB storage space in which data is stored in the MLC mode. The storage space in the flash memory array may be expanded).
Regarding claim 12, Shikata in view of Tanpairoj in further view of Zhou teaches The apparatus of claim 11, wherein, when the amount of available space does not satisfy threshold, the control circuitry is configured to cause the apparatus to: select the second write format instead of the first write format; and write the data to the one or more first memory devices using the second write format based at least in part on selecting the second write format (Zhou paragraphs [0058-0060], It should be noted that the controller 11 in the flash memory array may detect an amount of user data in each hard disk by using the flash memory controller 121 of each hard disk in the flash memory array, to determine the amount of user data in the entire flash memory array, and then to determine whether the amount of user data in the flash memory array is greater than or equal to the first preset value. The controller 11 may interact with the flash memory controller 121 of each hard disk, to obtain an amount of real-time user data in each hard disk. 502: When detecting that the amount of user data stored in the storage array is greater than or equal to the first preset value, the controller 11 converts a data storage mode of at least a part of storage space in the flash memory array from a first mode to a second mode. For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. The data migration technique is employed based on the storage space available in comparison to a preset value (i.e. threshold). In the event of the capacity needing to be expanded (insufficient space, threshold exceeded), then a different data migration technique to the initial one may be employed, as described above).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj with those of Zhou. Zhou teaches comparing the available space for a write operation to a preset threshold value for determining if a data migration needs to occur. Zhou uses the data migration when the threshold is exceeded and the available memory capacity is insufficient, which allows the memory system to continue operating while still completing said memory write commands (Zhou paragraphs [0060-0061], For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. When the controller 11 detects that the amount of user data stored in the flash memory array is greater than or equal to the first preset value, the controller 11 converts the data storage mode of the at least a part of storage space in the flash memory array from the first mode to the second mode. For example, when the amount of user data stored in the flash memory array in step 501 is greater than or equal to 409.6 GB, the controller 11 may convert the data storage mode of the 50 GB storage space in which data is stored in the SLC mode in the two QLC hard disks to the MLC mode, to obtain 100 GB storage space in which data is stored in the MLC mode. In this way, the total storage space in the flash memory array is 462 GB storage space in which data is stored in the SLC mode and the 100 GB storage space in which data is stored in the MLC mode. The storage space in the flash memory array may be expanded).
Regarding claim 13, Shikata in view of Tanpairoj in further view of Zhou teaches The apparatus of claim 8, wherein the control circuitry is configured to cause the apparatus to: select the first write format instead of the second write format based at least in part on the data being sequential (Zhou paragraph [0047], Each erase block includes a plurality of pages. The hard disk writes the data on a page when performing the data write request. For example, the controller 11 sends a data write request to the flash memory controller 121. The data write request includes a logical address of data. After receiving the data write request, the flash memory controller 121 continuously writes the data into one or more erase blocks in a receiving time sequence. “Continuously writes the data into one or more erase blocks” refers that: The flash memory controller 121 searches for a blank erase block, and writes the data into the blank erase block until the blank erase block is fully filled; and when an amount of data exceeds a capacity of the erase block, the flash memory controller 121 searches for a next blank erase block, and continues to write the data into the next blank erase block. The flash translation layer establishes and stores a correspondence between the logical address and an actual address of a page into which the data is written. When the controller 11 sends a data read request to the flash memory controller 121 to request to read the data, the data read request includes the logical address. The flash memory controller 121 reads the data based on the logical address and the correspondence between the logical address and the actual address, and sends the data to the controller 11. The data may be written in a continuous manner for a data write request into the same data page. This results in the data being written sequentially in logical address).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj with those of Zhou. Zhou teaches determining that a data migration technique be used when the available space for data exceeds the threshold and the data is sequential. Using sequential data allows the memory system to know that the data can be grouped together via logical address and be related to a high degree. This means that data migration can occur in larger sections of memory at once which can speed up the process of data migration/transfer and reduce the risk of invalid data (Zhou paragraph [0046-0047], The hard disk generally includes one or more flash memory chips. Each flash memory chip includes a plurality of erase blocks. The data is read from or written into the hard disk on a page, but an erase operation can be performed only on one erase block. The erase operation is used to set all bits of the block to 1. Before erasing, the flash memory controller needs to first copy valid data in the erase block to a blank page of another block. The valid data in the erase block is data that is stored in the block and that is not modified, and the data may be read. Invalid data in the erase block is data that is stored in the block and that is modified, and the data may not be read).
Regarding claim 15, Shikata in view of Tanpairoj in further view of Zhou teaches The apparatus of claim 8, wherein the control circuitry is configured to cause the apparatus to: select the first write format instead of the second write format based at least in part on a production operation for the one or more first memory devices being complete (Zhou paragraph [0011-0012], Optionally, the storage device further includes a second storage area, the second storage area stores data in the second mode, and before the converting a data storage mode of a first sub-area in the first storage area from the first mode to a second mode, the method further includes: migrating at least a part of user data in the user data in the first storage area to the second storage area of the storage device; and releasing an area occupied by the at least a part of user data. In this way, the user data may be first migrated, and the storage space is released. This can ensure data security. Optionally, the method further includes: receiving a data write request, where the data write request includes target data; and writing the target data into the converted first sub-area in the second mode. After the data storage mode of the first sub-area in the first storage area is converted from the first mode to the second mode. If the storage device receives the data write request again, the storage device writes the target data into the converted first sub-area in the second mode. The data migration may occur based on the production (i.e., write) operation being complete or in progress).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj with those of Zhou. Zhou teaches using a data migration technique for moving data based on the execution status of a given production (i.e., write) command operation. Waiting to migrate the data until after the command is complete allows the memory controller to know the full size of the data being migrated and how the size of the data compares to a given size of a different storage unit or storage format (Zhou paragraph [0011-0012], Optionally, the storage device further includes a second storage area, the second storage area stores data in the second mode, and before the converting a data storage mode of a first sub-area in the first storage area from the first mode to a second mode, the method further includes: migrating at least a part of user data in the user data in the first storage area to the second storage area of the storage device; and releasing an area occupied by the at least a part of user data. In this way, the user data may be first migrated, and the storage space is released. This can ensure data security. Optionally, the method further includes: receiving a data write request, where the data write request includes target data; and writing the target data into the converted first sub-area in the second mode. After the data storage mode of the first sub-area in the first storage area is converted from the first mode to the second mode. If the storage device receives the data write request again, the storage device writes the target data into the converted first sub-area in the second mode).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata in view of Tanpairoj in further view of Zhou as applied to claim 13 above, and further in view of Sprouse et al. (US Publication No. 2011/0153911 – “Sprouse”).
Regarding claim 14, Shikata in view of Tanpairoj in further view of Zhou and further in view of Sprouse teaches The apparatus of claim 13, wherein, when the data is not sequential, the control circuitry is configured to cause the apparatus to: select the second write format instead of the first write format; and write the data to the one or more first memory devices using the second write format based at least in part on selecting the second write format (Sprouse paragraph [0048], The above-described techniques of writing sequentially addressed data to binary blocks and then folding multiple binary blocks into MLC blocks in parallel may be implemented as part of an overall data flow in a memory system. The process and system discussed above is suitable for sequential writes to binary blocks and parallel folds into MLC blocks for data coming from multiple sources. For example, the data that triggers a fold operation may be received at the memory system from an external host. Alternatively, the trigger for a folding operation may be data previously received from the host and already in the memory system. The fold operation would then be triggered by a housekeeping function. Examples of housekeeping functions might be the eviction of data from a binary cache in the memory when enough non-sequential data runs have been collected to assemble a complete sequentially addresses virtual update block. Non-sequential data may be compiled and written from one memory device to another in a MLC folding operation).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj and Zhou with those of Sprouse. Sprouse teaches using a second write format (i.e., MLC write format) when data is determined to be non-sequential, which can allow for better data compression and more efficient use of storage space (i.e., see Sprouse paragraph [0048], Examples of housekeeping functions might be the eviction of data from a binary cache in the memory when enough non-sequential data runs have been collected to assemble a complete sequentially addresses virtual update block. Other housekeeping functions that might trigger a fold operation may be wear leveling operations that would result in a MLC-to-MLC block copy that would go through a virtual update block. Another example of a housekeeping operation capable of triggering a fold operation may be the process of cleaning up and closing binary blocks in a way that leads to the creation of a virtual update block. Thus the creation of virtual update blocks may be through sequentially written data received directly from an external source (e.g. host) or sources internal to the memory where previously received host data is moved about by housekeeping functions).
Claim(s) 17 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata et al. (US Publication No. 2017/0337969 – “Shikata”) in view of Tanpairoj et al. (US Publication No. 2019/0369899 – “Tanpairoj”) in further view of Byun (US Publication No. 2020/0310688 – “Byun”).
Regarding claim 17, Shikata teaches An apparatus comprising: one or more first memory devices; and control circuitry coupled with the one or more first memory devices and configured to cause the apparatus to: (Shikata paragraphs [0038-0040], The semiconductor memory device 10 is a NAND flash memory that stores data in a nonvolatile manner. The details of the configuration of the semiconductor memory device 10 will be described below. The controller 20 commands the semiconductor memory device 10 to execute reading, writing, erasing, or the like in response to a command from an external host apparatus (not illustrated). The controller 20 manages a memory space of the semiconductor memory device 10. As illustrated in FIG. 1, the controller 20 includes a processor (CPU) 21, an internal memory (RAM) 22, an ECC circuit 23, a NAND interface circuit 24, a buffer memory 25, and a host interface circuit 26. A control circuit may be coupled with a memory device to perform various memory operations/commands) determine whether to write the data to the one or more first memory devices using a first write format or a second write format (Shikata paragraph [0196], The semiconductor memory device 10 can execute a write operation of a triple level cell (TLC) scheme of storing 3-bit data in one memory cell or a write operation of a quadruple level cell (QLC) scheme of storing 4-bit data in one memory cell. The memory system can choose to utilize a tri-level write format or a quad-level write format depending on various factors related to the data write operation, also see Shikata paragraph [0199], In this way, when the memory cell retains the data of a plurality of bits, the number of peaks of the threshold voltage distribution increases as the number of bits to be stored increases. When a write operation and a read operation are executed on the memory cells storing the 3-bit data and the 4-bit data, a verifying voltage and a reading voltage are set as in the case of 2 bits described in FIG. 4) the second write format associated with a greater quantity of bits per memory cell than the first write format; (Shikata paragraph [0196], The semiconductor memory device 10 can execute a write operation of a triple level cell (TLC) scheme of storing 3-bit data in one memory cell or a write operation of a quadruple level cell (QLC) scheme of storing 4-bit data in one memory cell. The memory system can choose to utilize a tri-level write format or a quad-level write format depending on various factors related to the data write operation, also see Shikata paragraph [0199], In this way, when the memory cell retains the data of a plurality of bits, the number of peaks of the threshold voltage distribution increases as the number of bits to be stored increases. When a write operation and a read operation are executed on the memory cells storing the 3-bit data and the 4-bit data, a verifying voltage and a reading voltage are set as in the case of 2 bits described in FIG. 4).
Shikata does not teach receive, from a host device, a command associated with a transfer of data from one or more second memory devices to the one or more first memory devices; determine, based at least in part on receiving the command, whether an amount of data associated with the transfer exceeds a threshold; based at least in part on whether the amount of data exceeds the threshold, and write the data to the one or more first memory devices using the first write format based at least in part on determining that the amount of data exceeds the threshold.
However, Tanpairoj teaches receive, from a host device, a command associated with a transfer of data from one or more second memory devices to the one or more first memory devices; (Tanpairoj paragraph [0072], At operation 520 the NAND memory device may evaluate any initiation rules in the SLC cache migration profile using the retrieved NAND operational conditions to determine whether the rules in the cache migration profile are satisfied (e.g., return an indication that the migration should be initiated). If the rules are not satisfied, then processing may terminate. Processing of FIG. 5 may occur periodically, in response to a particular event (e.g., a queue depth being zero), or the like. At operation 525 if the rules are satisfied, then the system may begin migrating data in the SLC cache to MLC/TLC memory cells. The command may include a migration command involving writing data from one memory device to a different memory device).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata with those of Tanpairoj. Tanpairoj teaches converting data from a first write format to a second write format with more bits per memory cell during a particular time interval, which can help reduce performance impact associated with the data conversion (i.e., see Tanpairoj paragraphs [0061-0062], Eventually, data written to the SLC cache may fill up the SLC cache. To continue to use the increased performance of the SLC cache for new requests, the NAND memory device can move data in SLC to MLC/TLC. The choice of how and when to move the data can have serious performance impacts. For example, if the NAND is busy, the extra processing needed to move the data can slow down performance of host commands requested by a host over a host interface. In addition, NAND devices that are part of a battery powered computing device (e.g., a mobile phone, etc.) have strict power targets. If the migration is not properly managed, the extra processing required may consume too much power and put the NAND device over its prescribed power limit. Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules in an SLC cache migration profile that are evaluated using current operational parameters of the NAND device. In some examples, the SLC cache migration process may utilize NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data).
Shikata in view of Tanpairoj does not teach determine, based at least in part on receiving the command, whether an amount of data associated with the transfer exceeds a threshold; based at least in part on whether the amount of data exceeds the threshold, and write the data to the one or more first memory devices using the first write format based at least in part on determining that the amount of data exceeds the threshold.
However, Byun teaches determine, based at least in part on receiving the command, whether an amount of data associated with the transfer exceeds a threshold; based at least in part on whether the amount of data exceeds the threshold, (Byun paragraph [0040], The controller 1200 may control the memory device 1100 to perform a read reclaim operation of detecting and selecting a victim memory block having a read count greater than a preset reference count and storing, in a target memory block of the plurality of memory blocks, valid data stored in the victim memory block. The target memory block may be selected from among free blocks each having an erased status included in the memory device 1100. Furthermore, the controller 1200 may control, during the read reclaim operation, a program mode of storing valid data in a target memory block depending on the amount of valid data read from the memory device 1100. For example, in the case where during the read reclaim operation the amount of valid data read from the victim memory block is equal to or less than a preset reference amount, the valid data may be stored in the target memory block in a lower level cell program mode than a program mode of the victim memory block. For instance, if the victim memory block has been programmed in a triple level cell (TLC) program mode, the target memory block may store the valid data in a single level cell (SLC) program mode, or a multi-level cell (MLC) program mode. In the case where the amount of valid data read from the victim memory block is greater than the preset reference amount, the valid data may be stored in the target memory block in the program mode of the victim memory block. The preset reference amount may be adjusted depending on the number of free blocks of the plurality of memory blocks included in the memory device 1100. For example, as the number of free blocks is increased, the preset reference amount may be increased. As the number of free blocks is reduced, the preset reference amount may be reduced. The amount of data involved in the transfer may be compared to a preset threshold to determine if the data is written in the first or second formatting, where the data amount exceeding the threshold can result in the data being written in the higher bit level, also see Byun paragraph [0071]) and write the data to the one or more first memory devices using the first write format based at least in part on determining that the amount of data exceeds the threshold (Byun paragraph [0071], The program mode setting block 1244 may set a program mode of the valid data by comparing the amount of valid data counted by the valid data counter 1243 with the preset reference amount. For example, in the case where during the read reclaim operation the amount of valid data read from the victim memory block is equal to or less than the preset reference amount, the program mode setting block 1244 may set a program mode of the target memory block to a lower level cell program mode than a program mode of the victim memory block. For example, if the victim memory block has been programmed in a TLC program mode, the program mode of the target memory block may be set to an SLC program mode or an MLC program mode. If the amount of data exceeds the threshold, it may be written in the first write format).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj with those of Byun. Byun teaches using an amount of data involved in a data command to determine a write format for performing the data transfer, which can minimize data loss and provide more efficient data transfers/storage (i.e., see Byun paragraph [0116], As described above, in various embodiments of the present disclosure, during a read reclaim operation, when valid data read from a victim memory block is programmed to a target memory block, the read valid data is programmed in a lower level cell program mode than the program mode of the victim memory block, whereby the reliability of the valid data may be improved. Furthermore, the program mode is selected depending on the amount of valid data, so that the number of free blocks may be prevented from being reduced to a predetermined value or less).
Regarding claim 21, Shikata in view of Tanpairoj in further view of Byun teaches The apparatus of claim 17, wherein the control circuitry is further configured to cause the apparatus to: convert, after writing the data to the one or more first memory devices using the first write format, the data from the first write format to the second write format during a time period that is associated with an idle mode of the one or more first memory devices, one or more background operations of the one or more first memory devices, or any combination thereof (Tanpairoj paragraph [0124], Example 25 is a device of operating a NAND device, the device comprising: at a NAND controller: means for retrieving an SLC cache migration profile, the SLC cache migration profile including a first and second initiation rule for initiating a migration of data stored in an SLC cache to MLC memory cells, the first and second rules comprising one of: an idle rule, a data fragmentation rule, a current block erase count, a current Write Amplification Factor (WAF), or a power consumption level rule, wherein the first rule is different than the second rule; means for retrieving a first NAND operational condition specified by the first rule, and determining that the first NAND operational condition satisfies the first rule; means for retrieving a second NAND operational condition specified by the second rule, and determining that the second NAND operational condition satisfies the second rule; means for responsive to the first and second rule being satisfied, migrating at least a portion of data stored in the SLC cache to MLC memory cells of the NAND device. One rule for migrating data from SLC to MLC can include an idle period detection).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata with those of Tanpairoj and Byun. Tanpairoj teaches converting data from a first write format to a second write format with more bits per memory cell during a particular time interval, which can help reduce performance impact associated with the data conversion (i.e., see Tanpairoj paragraphs [0061-0062], Eventually, data written to the SLC cache may fill up the SLC cache. To continue to use the increased performance of the SLC cache for new requests, the NAND memory device can move data in SLC to MLC/TLC. The choice of how and when to move the data can have serious performance impacts. For example, if the NAND is busy, the extra processing needed to move the data can slow down performance of host commands requested by a host over a host interface. In addition, NAND devices that are part of a battery powered computing device (e.g., a mobile phone, etc.) have strict power targets. If the migration is not properly managed, the extra processing required may consume too much power and put the NAND device over its prescribed power limit. Disclosed in some examples are systems, methods, NAND memory devices, and machine readable mediums for intelligent SLC cache migration processes that move data written to SLC cache to MLC storage based upon a set of rules in an SLC cache migration profile that are evaluated using current operational parameters of the NAND device. In some examples, the SLC cache migration process may utilize NAND operational parameters to determine when to move the data written to SLC cache to MLC, how much data to move from SLC to MLC, and the parameters for moving the data).
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shikata in view of Tanpairoj in further view of Byun as applied to claim 17 above, and further in view of Zhou.
Regarding claim 18, Shikata in view of Tanpairoj in further view of Byun and further in view of Zhou teaches The apparatus of claim 17, wherein, when the amount of data does not exceed the threshold, the control circuitry is configured to cause the apparatus to write the data to the one or more first memory devices using the second write format (Zhou paragraphs [0058-0060], It should be noted that the controller 11 in the flash memory array may detect an amount of user data in each hard disk by using the flash memory controller 121 of each hard disk in the flash memory array, to determine the amount of user data in the entire flash memory array, and then to determine whether the amount of user data in the flash memory array is greater than or equal to the first preset value. The controller 11 may interact with the flash memory controller 121 of each hard disk, to obtain an amount of real-time user data in each hard disk. 502: When detecting that the amount of user data stored in the storage array is greater than or equal to the first preset value, the controller 11 converts a data storage mode of at least a part of storage space in the flash memory array from a first mode to a second mode. For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. The data migration technique is employed based on the storage space available in comparison to a preset value (i.e. threshold). In the event of the capacity needing to be expanded (insufficient space, threshold exceeded), then a different data migration technique to the initial one may be employed, as described above).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj and Byun with those of Zhou. Zhou teaches comparing the available space for a write operation to a preset threshold value for determining if a data migration needs to occur. Zhou uses the data migration when the threshold is exceeded and the available memory capacity is insufficient, which allows the memory system to continue operating while still completing said memory write commands (Zhou paragraphs [0060-0061], For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. When the controller 11 detects that the amount of user data stored in the flash memory array is greater than or equal to the first preset value, the controller 11 converts the data storage mode of the at least a part of storage space in the flash memory array from the first mode to the second mode. For example, when the amount of user data stored in the flash memory array in step 501 is greater than or equal to 409.6 GB, the controller 11 may convert the data storage mode of the 50 GB storage space in which data is stored in the SLC mode in the two QLC hard disks to the MLC mode, to obtain 100 GB storage space in which data is stored in the MLC mode. In this way, the total storage space in the flash memory array is 462 GB storage space in which data is stored in the SLC mode and the 100 GB storage space in which data is stored in the MLC mode. The storage space in the flash memory array may be expanded).
Regarding claim 19, Shikata in view of Tanpairoj in further view of Byun and further in view of Zhou teaches The apparatus of claim 17, wherein the control circuitry is further configured to cause the apparatus to: determine whether to write the data to the one or more first memory devices using the first write format or the second write format based at least in part on whether an amount of available space within the one or more first memory devices exceeds a second threshold (Zhou paragraphs [0058-0060], It should be noted that the controller 11 in the flash memory array may detect an amount of user data in each hard disk by using the flash memory controller 121 of each hard disk in the flash memory array, to determine the amount of user data in the entire flash memory array, and then to determine whether the amount of user data in the flash memory array is greater than or equal to the first preset value. The controller 11 may interact with the flash memory controller 121 of each hard disk, to obtain an amount of real-time user data in each hard disk. 502: When detecting that the amount of user data stored in the storage array is greater than or equal to the first preset value, the controller 11 converts a data storage mode of at least a part of storage space in the flash memory array from a first mode to a second mode. For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. The data migration technique is employed based on the storage space available in comparison to a preset value (i.e. threshold). In the event of the capacity needing to be expanded (insufficient space, threshold exceeded), then a different data migration technique to the initial one may be employed, as described above).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj and Byun with those of Zhou. Zhou teaches comparing the available space for a write operation to a preset threshold value for determining if a data migration needs to occur. Zhou uses the data migration when the threshold is exceeded and the available memory capacity is insufficient, which allows the memory system to continue operating while still completing said memory write commands (Zhou paragraphs [0060-0061], For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. When the controller 11 detects that the amount of user data stored in the flash memory array is greater than or equal to the first preset value, the controller 11 converts the data storage mode of the at least a part of storage space in the flash memory array from the first mode to the second mode. For example, when the amount of user data stored in the flash memory array in step 501 is greater than or equal to 409.6 GB, the controller 11 may convert the data storage mode of the 50 GB storage space in which data is stored in the SLC mode in the two QLC hard disks to the MLC mode, to obtain 100 GB storage space in which data is stored in the MLC mode. In this way, the total storage space in the flash memory array is 462 GB storage space in which data is stored in the SLC mode and the 100 GB storage space in which data is stored in the MLC mode. The storage space in the flash memory array may be expanded).
Regarding claim 20, Shikata in view of Tanpairoj in further view of Byun and further in view of Zhou teaches The apparatus of claim 19, wherein the control circuitry is configured to cause the apparatus to: write the data to the one or more first memory devices using the first write format based at least in part on determining that the amount of available space within the one or more first memory devices exceeds the second threshold (Zhou paragraphs [0058-0060], It should be noted that the controller 11 in the flash memory array may detect an amount of user data in each hard disk by using the flash memory controller 121 of each hard disk in the flash memory array, to determine the amount of user data in the entire flash memory array, and then to determine whether the amount of user data in the flash memory array is greater than or equal to the first preset value. The controller 11 may interact with the flash memory controller 121 of each hard disk, to obtain an amount of real-time user data in each hard disk. 502: When detecting that the amount of user data stored in the storage array is greater than or equal to the first preset value, the controller 11 converts a data storage mode of at least a part of storage space in the flash memory array from a first mode to a second mode. For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. The data migration technique is employed based on the storage space available in comparison to a preset value (i.e. threshold). In the event of the capacity needing to be expanded (insufficient space, threshold exceeded), then a different data migration technique to the initial one may be employed, as described above).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Shikata and Tanpairoj and Byun with those of Zhou. Zhou teaches comparing the available space for a write operation to a preset threshold value for determining if a data migration needs to occur. Zhou uses the data migration when the threshold is exceeded and the available memory capacity is insufficient, which allows the memory system to continue operating while still completing said memory write commands (Zhou paragraphs [0060-0061], For ease of description, the SLC mode is used as an example of the first mode, and the MLC mode is used as an example of the second mode. A hard disk storing data in the second mode has a higher data density than a hard disk storing data in the first mode. After the data storage mode of the at least a part of storage space in the flash memory array is converted from the first mode to the second mode, the capacity of the flash memory array may be expanded, and more data may be stored. It should be noted that, after the first mode is converted to the second mode, a user cannot perceive a change in the capacity of the flash memory array. When the controller 11 detects that the amount of user data stored in the flash memory array is greater than or equal to the first preset value, the controller 11 converts the data storage mode of the at least a part of storage space in the flash memory array from the first mode to the second mode. For example, when the amount of user data stored in the flash memory array in step 501 is greater than or equal to 409.6 GB, the controller 11 may convert the data storage mode of the 50 GB storage space in which data is stored in the SLC mode in the two QLC hard disks to the MLC mode, to obtain 100 GB storage space in which data is stored in the MLC mode. In this way, the total storage space in the flash memory array is 462 GB storage space in which data is stored in the SLC mode and the 100 GB storage space in which data is stored in the MLC mode. The storage space in the flash memory array may be expanded).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JONAH C KRIEGER whose telephone number is (571)272-3627. The examiner can normally be reached Monday - Friday 8 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kenneth Lo can be reached at (571) 272-9774. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.C.K./ Examiner, Art Unit 2136
/KENNETH M LO/ Supervisory Patent Examiner, Art Unit 2136