DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/24/2026 has been entered.
Claim Objections
Claim 17 (dependent on claim 12) is objected to as being a substantial duplicate of claim 12. Claim 17 (dependent on claim 12) recites “the driving element is turned on in the initialization period” which is disclosed in claim 12, lines 21-22 (i.e. “in the initialization period, the second switch element, the third switch element, and the driving element are turned on”). Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 11-15, and 17-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang (US 2021/0174743 A1).
As to claim 1, Chang teaches a pixel circuit ([0065]: pixel driving circuit) comprising:
a driving element (transistor DT in Fig. 3A) including a gate electrode connected to a first node (node n1 in Fig. 3A), a first electrode connected to a second node (node connecting electrode of transistor DT and high potential voltage line VDD in Fig. 3A), and a second electrode connected to a third node (node n2 in Fig. 3A);
a light-emitting element (light-emitting element EL in Fig. 3A) connected to the second electrode of the driving element (transistor DT in Fig. 3A);
a first capacitor (capacitor C1 in Fig. 3A) connected to the first node (node n1 in Fig. 3A) and a fourth node (node n3 in Fig. 3A);
a second capacitor (capacitor C2 in Fig. 3A) connected to the fourth node (node n3 in Fig. 3A) and the second node (node connecting electrode of transistor DT and high potential voltage line VDD in Fig. 3A);
a first switch element (transistor T4 in Fig. 3A) directly connected to the first node (node n1 in Fig. 3A) and the third node (node n2 in Fig. 3A);
a second switch element (transistor T3 in Fig. 3A) connected to the fourth node (node n3 in Fig. 3A) and a reference voltage supply line (voltage V3 line in Fig. 3A);
a third switch element (transistor T1 in Fig. 3A) connected to the first node (node n1 in Fig. 3A) and an initialization voltage supply line (voltage V1 line in Fig. 3A); and
a fourth switch element (transistor T5 in Fig. 3A) connected to the fourth node (node n3 in Fig. 3A) and a data voltage supply line (Vdata line in Fig. 3A),
wherein the pixel circuit is driven in an initialization period ([0066-0067]: initialization period), a sampling period ([0068]: sampling period), a programming period ([0043]: programming period), and an emission period ([0082]: emission period),
wherein during the initialization period ([0067]: initialization period), the second switch element (transistor T3 in Fig. 3A), the third switch element (transistor T1 in Fig. 3A), and the driving element (transistor DT in Fig. 3A) are turned on ([0067]: turned on), and the first switch element (transistor T4 in Fig. 3A) and the fourth switch element (transistor T5 in Fig. 3A) are turned off ([0067]: turned off), and
wherein the first capacitor (capacitor C1 in Fig. 3A), the second capacitor (capacitor C2 in Fig. 3A), the second switch element (transistor T3 in Fig. 3A), and the fourth switch element (transistor T5 in Fig. 3A) are directly connected to the fourth node (node n3 in Fig. 3A).
As to claim 2, Chang teaches the pixel circuit of claim 1, wherein a reference voltage applied from the reference voltage supply line (voltage V3 line in Fig. 3A) is greater than an initialization voltage applied from the initialization voltage supply line (voltage V1 line in Fig. 3A; [0072]: V3 voltage higher than V5 voltage; [0155]; claim 12: the V1 voltage and the V5 voltage are a same voltage).
As to claim 3, Chang teaches the pixel circuit of claim 2, wherein the first capacitor (capacitor C1 in Fig. 3A) is initialized by applying the reference voltage (voltage V3 in Fig. 3A) and the initialization voltage (voltage V1 in Fig. 3A) to both ends of the first capacitor respectively (capacitor C1 in Fig. 3A).
As to claim 4, Chang teaches the pixel circuit of claim 3, wherein the second capacitor (capacitor C2 in Fig. 3A) is initialized by applying the reference voltage (voltage V3 in Fig. 3A) and a pixel driving voltage ([0062]: provide voltage Vref to node n4 which is directly connected to capacitor C2, Fig. 3A) to both ends of the second capacitor respectively (capacitor C2 in Fig. 3A).
As to claim 5, Chang teaches the pixel circuit of claim 1, comprising:
a fifth switch element (T8 in Fig 3A) configured to connect the initialization voltage supply line (voltage V1 line in Fig. 3A; note that transistor T8 is connected to voltage V1 line through transistors T4 and T1) and an anode of the light-emitting element (light- emitting element EL in Fig. 3A);
a first gate line (S(n-2) line in Fig. 3A) connected to gate electrodes of the third switch element (transistor T1 in Fig. 3A) and the fifth switch element (T8 in Fig 3A; note that the claim does not recite “directly” connected. All of the elements in Fig. 3A are connected to each other).
As to claim 7, Chang teaches the pixel circuit of claim 1, comprising:
a first gate line (S(n-2) line in Fig. 3A) that applies a first gate voltage to a gate electrode of the third switch element (transistor T1 in Fig. 3A);
a second gate line (S(n-2) line in Fig. 3A) that applies a second gate voltage to a gate electrode of the second switch element (transistor T3 in Fig. 3A);
a third gate line (line directly connected to gate of transistor T4 in Fig. 3A) that applies a third gate voltage to a gate electrode of the first switch element (transistor T4 in Fig. 3A); and
a fourth gate line (S(n) line in Fig. 3A) that applies a fourth gate voltage to a gate electrode of the fourth switch element (transistor T5 in Fig. 3A).
As to claim 11, Chang teaches the pixel circuit of claim 1, wherein the initialization voltage supply line (voltage V1 line in Fig. 3A and 4A) is electrically isolated from the second electrode of the driving element (transistor DT in Figs. 3A and 4A; note: when transistor T1 is turned off, the initialization voltage supply line V1 is electrically isolated from the second electrode of transistor DT in Figs. 3A and 4A;[0074]: T1 is turned off).
As to claim 12, Chang teaches a display device ([0002]: display device) comprising:
a data driving circuit ([0034]: data driving circuit);
a gate driving circuit ([0034]: gate driving circuit); and
a pixel circuit ([0065]: pixel driving circuit) comprising:
a driving element (transistor DT in Fig. 3A) including a gate electrode connected to a first node (node n1 in Fig. 3A), a first electrode connected to a second node (node connecting electrode of transistor DT and high potential voltage line VDD in Fig. 3A), and a second electrode connected to a third node (node n2 in Fig. 3A);
a light-emitting element (light-emitting element EL in Fig. 3A) connected to the second electrode of the driving element (transistor DT in Fig. 3A);
a first capacitor (capacitor C1 in Fig. 3A) connected to the first node (node n1 in Fig. 3A) and a fourth node (node n3 in Fig. 3A);
a second capacitor (capacitor C2 in Fig. 3A) connected to the fourth node (node n3 in Fig. 3A) and the second node (node connecting electrode of transistor DT and high potential voltage line VDD in Fig. 3A);
a first switch element (transistor T4 in Fig. 3A) directly connected to the first node (node n1 in Fig. 3A) and the third node (node n2 in Fig. 3A);
a second switch element (transistor T3 in Fig. 3A) connected to the fourth node (node n3 in Fig. 3A) and a reference voltage supply line (voltage V3 line in Fig. 3A);
a third switch element (transistor T1 in Fig. 3A) connected to the first node (node n1 in Fig. 3A) and an initialization voltage supply line (voltage V1 line in Fig. 3A); and
a fourth switch element (transistor T5 in Fig. 3A) connected to the fourth node (node n3 in Fig. 3A) and a data voltage supply line (Vdata line in Fig. 3A),
wherein the pixel circuit is driven in an initialization period ([0066-0067]: initialization period), a sampling period ([0068]: sampling period), a programming period ([0043]: programming period), and an emission period ([0082]: emission period),
in the initialization period ([0067]: initialization period), the second switch element (transistor T3 in Fig. 3A), the third switch element (transistor T1 in Fig. 3A), and the driving element (transistor DT in Fig. 3A) are turned on ([0067]: turned on), and the first switch element (transistor T4 in Fig. 3A) and the fourth switch element (transistor T5 in Fig. 3A) are turned off ([0067]: turned off), and
wherein the first capacitor (capacitor C1 in Fig. 3A), the second capacitor (capacitor C2 in Fig. 3A), the second switch element (transistor T3 in Fig. 3A), and the fourth switch element (transistor T5 in Fig. 3A) are directly connected to the fourth node (node n3 in Fig. 3A).
As to claim 13, Chang teaches the display device of claim 12, wherein:
in the initialization period ([0067]: initialization period), the first capacitor (C1 in Fig. 3A) is initialized by applying a reference voltage from the reference voltage supply line (voltage V3 line in Fig. 3A;[0072]); and an initialization voltage from the initialization voltage supply line (voltage V1 line in Fig. 3A;[0068]) to both ends of the first capacitor, respectively (C1 in Fig. 3A),
in the sampling period ([0078]: sampling period), a threshold voltage of the driving element is sampled ([0008];[0078]: voltage of the first node n1 continues to rise to be the sum of the high potential voltage VDD and the threshold voltage Vth of the driving transistor DT, and the first capacitor C1 senses the threshold voltage Vth of the driving transistor DT) using the reference voltage ([0072]: the V3 voltage higher than or equal to the voltage V5, thereby increasing the range in which the threshold voltage Vth of the driving transistor DT can be sensed) and a pixel driving voltage (0078]: voltage of the first node n1 continues to rise to be the sum of the high potential voltage VDD and the threshold voltage Vth of the driving transistor DT, and the first capacitor C1 senses the threshold voltage Vth of the driving transistor DT).
in the programming period ([0043]: sampling period includes a programming period), a data voltage is applied to the pixel circuit ([0047];[0107]: data voltage applied to the pixel driving circuit) and the data voltage is stored in a second capacitor ([0107]: capacitor C2 stores data voltage).
As to claim 14, Chang teaches the display device of claim 13, wherein the sampling period is longer or shorter than one horizontal period ([0073]: sampling period has two horizontal scanning periods (2H time)).
As to claim 15, Chang teaches the display device of claim 13, wherein the initialization period and the sampling period are a same in time length ([0066]: initialization period has two horizontal scanning periods (2H time); [0073]: sampling period has two horizontal scanning periods (2H time)).
As to claim 17, Chang teaches the display device of claim 12, wherein the driving element (transistor DT in Fig. 3A) is turned on in the initialization period ([0067]: initialization period, transistor DT is turned on).
As to claim 18, Chang teaches the display device of claim 13, wherein, in the programming period ([0043]: sampling period includes a programming period), a voltage applied to the fourth node (node n3 in Fig. 4A) is not distributed by the first capacitor and the second capacitor ([0076]: transistor T5 is turned on; [0078] voltage V5 is stored in first capacitor C1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2021/0174743 A1) in view of Mao (US 2019/0385521 A1).
As to claim 9, Chang teaches the pixel circuit of claim 1, but does not explicitly disclose wherein a reference voltage applied from the reference voltage supply line is greater than a data voltage applied from the data voltage supply line.
However, Mao teaches wherein a reference voltage applied from the reference voltage supply line is greater than a data voltage applied from the data voltage supply line ([0049]: reference voltage is greater than data voltage).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang such that a reference voltage applied from the reference voltage supply line is greater than a data voltage applied from the data voltage supply line as taught by Mao in order for the organic light-emitting diode to emit light normally.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2021/0174743 A1) in view of Liu et al. (WO 2025/137823 A1, attached English machine translation is used in the rejection).
As to claim 10, Chang teaches the pixel circuit of claim 1, wherein the driving element (transistor DT in Fig. 3A) is p-channel transistor, but does not explicitly disclose the first switch element to the fourth switch element are all p-channel transistors.
However, Liu et al teaches the first switch element to the fourth switch element are all p-channel transistors (transistors T11, T7, T6 and T5 in Fig. 185 are p-channel transistors).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Chang such that the first switch element to the fourth switch element are all p-channel transistors as taught by Liu in order to improve display performance.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2021/0174743 A1) in view of Yang et al. (US 2021/0248961 A1).
As to claim 16, Chang teaches the display device of claim 13, but does not explicitly disclose wherein the initialization period and the sampling period are equally adjusted.
However, Yang et al. teaches wherein the initialization period (P1 in Fig. 3A;[0082-0083])
and the sampling period (P2 in Fig. 3A; [0071]) are equally adjusted ([0083];[0118]; Fig. 3A shows P1
and P2 are four horizontal time intervals. As shown in FIG. 3B, a width of a first period P1′ and
second period P2’ are three horizontal time intervals).
It would have been obvious to one of ordinary skill in the art before the effective filing
date of the claimed invention to modify the device of Chang such that the initialization period and the
sampling period are equally adjusted as taught by Yang et al. in order to minimize afterimage and
improve display quality.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7, 9-18 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624
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